Handy Board Operations
Accessing the Data Bus
Pete Jackson
(Senior Electrical Engineering)
December 5, 1997
hb_pj_02.doc
Executive Summary
The Handy Board (HB) was developed by the Media Laboratory at the Massachusetts Institute of
Technology. The Handy Board is based on the 52-pin Motorola MC68HC11 processor, and
includes 32K of battery-backed static RAM, four outputs for DC motors, a connector system that
allows active sensors to be individually plugged into the board, an LCD screen, and an
integrated, rechargeable battery pack. Additionally, the Handy Board is compatible with
Interactive C, the programming environment created for the MIT LEGO Robot Design project.
Interactive C (IC) is a multi-tasking, C language based compiler that includes a user command
line for dynamic expression implementation. The HB is the latest in a series of boards released
under MIT’s free licensing policy, in which the printed circuit board artwork, schematics, and
driver software may be freely licensed for personal, educational, and commercial use. The HB
may be purchased fully assembled or in kit form from several vendors. Information on the HB
and links to vendors may be found on the World Wide Web at:
 http://lcs.www.media.mit.edu/groups/el/Projects/handy-board/
Michigan State University is evaluating the HB for use in electrical engineering classes that
address microprocessor architecture, bus interfacing, data transfer, interrupt structure,
analog/digital interfacing, and the general application of embedded microcontrollers.
This document provides detailed information about interfacing with the HB’s eight bit data bus.
The purpose is to allow students with basic electrical engineering studies to implement a data
interface with the Handy Board.
This demonstration consists of three hardware devices and a software component. Each of the
hardware devices the HB, a proto-board, and the Switch Register Box (SRB) are fully described
in subsections of this document. A software subsection provides an overview of IC and the
program code and procedures required for the interface.
The purpose of this demonstration is to provide an external 8-bit, bi-directional data bus
connection to the HB’s data bus.
2
Table of Contents
SYSTEM-LEVEL DESCRIPTION ...........................................................................................................................4
HB Microcontroller ...................................................................................................................................................4
SRB (User I/O) ..........................................................................................................................................................4
Glue Logic (Proto-board interface) ............................................................................................................................5
 HB TO PROTO-BOARD BUS (I/O BUS #1) .................................................................................................5
 SRB TO PROTO-BOARD BUS (I/O BUS #2)................................................................................................6
System Behavior ........................................................................................................................................................6
A CLOSER LOOK AT THE HANDY BOARD .......................................................................................................7
Features Common To The HB ...................................................................................................................................7
Handy Board Physical Layout ...................................................................................................................................8
Configuring The HB For Use .................................................................................................................................. 10
HB Memory ............................................................................................................................................................. 10
The HB Data Bus ..................................................................................................................................................... 11
The HB Expansion Bus ........................................................................................................................................... 11
I/O BUSES .................................................................................................................................................................. 13
I/O Bus #1................................................................................................................................................................ 13
 PART ONE ................................................................................................................................................... 13
 PART TWO .................................................................................................................................................. 13
I/O Bus #2................................................................................................................................................................ 14
PHYSICAL SETUP ................................................................................................................................................... 14
HB Setup ................................................................................................................................................................. 14
Proto-Board Setup ................................................................................................................................................... 15
INTERACTIVE C (IC) ............................................................................................................................................. 17
General Description ................................................................................................................................................. 17
Running IC .............................................................................................................................................................. 17
SOFTWARE .............................................................................................................................................................. 19
Program Code .......................................................................................................................................................... 19
SUMMARY ................................................................................................................................................................ 20
APPENDIX ................................................................................................................................................................ 21
DM74AS374 Octal D-Type Edge-Triggered Flip-Flop with TRI-STATE Ouputs ................................................. 21
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
System Level Schematic ...............................................................................................................................4
Latched Data Flow ........................................................................................................................................5
Labeled Handy Board Diagram .....................................................................................................................8
CPU and Memory Circuit ........................................................................................................................... 12
Interface Schematic ..................................................................................................................................... 15
HB Header Pin-outs .................................................................................................................................... 16
IC Initialization Screen Shot ....................................................................................................................... 18
Loading User Program Screen Shot ............................................................................................................ 18
Running Simple Interactive Command ....................................................................................................... 19
List of Tables
Table 1: HB Memory Map .......................................................................................................................................... 10
Table 2: Decoder Operation......................................................................................................................................... 11
Table 3: DM74374 Truth Table ................................................................................................................................... 13
3
System-Level Description
The purpose of this demonstration is to provide an external 8-bit, bi-directional data bus
connection to the HB. This section describes operation at the system-level, which is comprised of
three main components connected by two busses.
8
HB
#1
User I/O
I/O Bus
I/O Bus
HB Microcontroller
8
Proto-board
Inter face
Glue Logic
#2
SRB
Figure 1: System Level Schematic
HB Microcontroller
The goal of this demonstration is to read and write single byte data on the HB’s data bus. There
is only one connection on the HB where access to the entire byte of the data bus is readily
available. This access is through the LCD header (see Figure 4). The HB looks for a functioning
LCD upon start-up. Therefore, the LCD must be relocated to the proto-board. The relocation
of the LCD is discussed in the HB Setup section.
SRB (User I/O)
The Switch Register Box (SRB) is a hardware device which contains an array of eight LED’s,
two 7-segment displays, eight digital outputs (two position switches), and various clock signals.
The array of LED’s are used in this demonstration to display a representation of the latched data
from the HB’s data bus. Each LED lights when a 5V signal is received from I/O bus #2. One of
the 7-segment displays also provides a representation of this data by converting the entire 8-bits,
present at the LED array, into its hexadecimal equivalent and displaying that value. Both the
LED array and the 7-segement displays are generated from the same 8-pins on the SRB header.
The eight digital output switches are used to generate the individual bits of the single byte of data
that is latched onto the HB data bus. Each switch provides a 0V signal in one position and a 5V
signal in its other position. The second 7-segment display provides the hexadecimal equivalent
of the byte generated by the positions of the digital output switches.
4
Glue Logic (Proto-board interface)
The proto-board is the hardware interface between the HB and the SRB. For this demonstration,
it consists of two DM74AS374 Tri-State Octal Latch IC’s and two male headers for connections
to the HB and to the SRB. The data sheets for these latches may be obtained from National
Semiconductors web site at : http://www.national.com
Latch-1
Vcc
Data in
from HB
1D..8D
74374
OC
8
I/O Bus
#2
Latch-2
Vcc
8
GND
74374
OC
Data out
to HB
1Q..8Q
8
CLK
GND
I/O Bus
#1
Data out
to SRB
1Q..8Q
8
Data in
from SRB
1D..8D
CLK
Pin-out for DM74374 Tri-State Octal Latches
Pin #
Pin #
1- output control (OC)
20- VCC
2- data out (1Q)
19- data out (8Q)
3- data in (1D)
18- data in (8D)
4- data in (2D)
17- data in (7D)
5- data out (2Q)
16- data out (7Q)
6- data out (3Q)
15- data out (6Q)
7- data in (3D)
14- data in (6D)
8- data in (4D)
13- data in (5D)
9- data out (4Q)
12- data out (5Q)
10- ground (GND)
11- clock
(CLK)
Pins 1-10 are from top to bottom on the left side of the IC.
Pins 20-11 are from top to bottom on the right side of the IC.
Notes: The output control is a Tri-State design.
The clock is Positive edge-triggered.
Figure 2: Latched Data Flow
Described fully, in the HB Expansion Bus section, software generated control signals latch data
onto and off of both I/O buses #1 and #2. These signals control each latch’s output control (OC)
and clock (CLK) pins.

HB to proto-board bus (I/O bus #1)
The purpose of I/O bus #1 is to transfer data to and from the HB. Data is latched onto the protoboard by a single latch (latch-1) connected to the HB by a 16-pin cable. Data is latched onto the
HB by a second latch (latch-2) also utilizing the 16-pin cable.
This cable provides the physical path for I/O between the HB and the proto-board. The cable
also supplies six control signals, power and ground, and the eight data bits of the data bus to the
LCD. This cable also supplies the two control signals for operation of the latches. The control
signals for the LCD are transparent to the user, while the control signals for the operation of the
latches are software driven created by the users program code.
I/O #1 bus is significantly different from I/O bus #2, because the 8-data bits flowing between the
HB and the proto-board, whether as input or output, use the same eight paths on the cable. On
I/O bus #2, there must exist separate paths for the SRB’s LED’s connection and the SRB’s data
out connection.
5

SRB to proto-board bus (I/O bus #2)
The purpose of I/O bus #2 is to transfer data between the SRB and the proto-board. For this
demonstration, the SRB requires one byte of data from the HB to operate its LED’s. This data is
latched from I/O bus #1 and flows to the SRB through 8-pins of a 16-pin cable. The additional
8-pins on this cable provide a path for the SRB’s data output to the proto-board. The SRB’s
data output is latched from I/O bus #2 and is provided to I/O bus #1.
System Behavior
Software reads and writes to specific address ranges enable pins on the HB’s expansion bus
(which is connected to the proto-board), thus latching data onto or off of the HB’s data bus. For
this demonstration, a simple looping program was written in C to continually perform these reads
and writes.
After the program has been started it continually samples (reads) data on the HB’s data bus,
stores the data to memory, and then writes the stored data back to the HB’s data bus. During this
process, the program enables the transfer of data from the HB’s memory to the SRB’s bank of
LED’s, and enables the flow of data from the SRB onto the HB’s data bus to be read and stored.
This continuous read/write cycle allows the user to select the position of any or all of the eight
digital switches on the SRB and see the results displayed on the SRB’s LED’s and 7-segment
display.
6
A Closer Look At The Handy Board
Features Common To The HB

Microprocessor. The 68HC11A1FN (6811) with 256 bytes internal RAM, timer/counter &
analog-to-digital subsystems. Systems clock runs at 2MZ.

Memory. 32K bytes of static RAM. Battery protected so that memory retains data even
when board power is switched off. Memory is mapped to the upper half of the 6811’s 64K
address space.

Addressing. Lower half of memory is decoded to provide signals for four digital output
latches and four digital input latches. One of each of these is present on the HB, and the
other six select signals are made available on an Expansion Bus.

Display. 16x2 character-based LCD display, with printf() function for displaying messages
and dynamic data. Two user push-buttons and one knob allows manual input for menu
navigation; piezo beeper for audio output.

Battery. Integral 9.6V rechargeable battery pack (8 AA nickel cadmium cells with 600 mA
capacity). Two battery charging options are provided: a trickle-charge on the HB itself and a
switchable trickle-charge/zap charge mode on the serial interface board

Motor Outputs. The digital output latch drives two TI H-bridge motor driver chips,
providing outputs for four bidirectionally controllable DC motors. Each motor output can
supply 1 ampere of current at 9.6V.

Sensor Inputs. Sixteen sensor headers (9 digital, 7 analog). Each sensor header provides
polarized 3-wire connection (+5V, ground, and signal). Three of the digital inputs connect to
the built-in 6811 timer hardware. The analog inputs connect to the 6811’s built-in A/D
subsystem, providing an 8-bit conversion each 17 microseconds.

Infrared Subsystem. Integral Sharp infrared decoder receives signals from household
TV/VCR remotes; built-in 40KHz modulator and drive transistor allows easy attachment of
IR LED’s to broadcast such signals. Supplied software allows decoding of Sony infrared
protocol; other manufactures’ formats available.

Interactive C. Multi-tasking, C-based development system. Compile and download
programs from MS-DOS, Macintosh, or Unix host computers. Features include standard C
control statements (if, else, for, while, break, continue) and data types (16- and 32-bit
integers, floating point numbers, characters, strings, and one-dimensional arrays).

Driver Software. Software available for a variety of devices, including shaft encoders,
Polaroid ultrasonic ranging devices, and servo motors.
7
Handy Board Physical Layout
(18) piezo
beeper
OFF
(17) LCD screen
(1) power
switch
ON
(16) SPI
expansion
header
(2) computer
connector
(3) 4 DC
motor outputs
and
indicators
(15) charge
indicator
(14) battery
trickle-charge
connector
(19) power
expansion
header
(13) user
knob
(4) “Start
(8)
button (5) “Stop”
9 digital
button
inputs
(6) low battery
indicator
(7) power/ready
indicator
(12) analog
expansion
header
(9)
7 analog
inputs
(11)
IR input
sensor
(10)
IR output
and
indicator
Figure 3: Labeled Handy Board Diagram
1- Power Switch. The power switch is used to turn the HB on and off. The HB retains the
contents of its memory even when the board is switched off.
2- Computer Connector. Via this RJ11 connector, the HB attaches to a desktop computer
(using the separate Interface/Charger Board).
3-
4 DC Motor Outputs and Indicators. The HB’s four motor outputs are located at this
single 12-pin connector. Each motor output consists of three pins; the motor connects to the
outer two pins and the center pin is not used. Red and green LED’s indicate motor direction.
From top to bottom, the motor outputs are numbered 0 to 3.
4- Start Button. The Start button is used to control the execution of Interactive C programs.
Also, its state may be read under user program control.
5- Stop Button. The Stop button is used to put the HB into a special bootstrap download mode.
Also, its state may be read under user program control.
8
6-
Low Battery Indicator. The red Low Battery LED lights when for a brief interval each time
the HB is switched on. If this LED is on steadily, it indicates that the battery is low and that
the CPU is halted.
7-
Power/Ready Indicator. The green Power/Ready LED lights when the HB is in normal
operation, and flashes when the HB is transmitting serial data. If the board is powered on and
this LED is off, then the HB is in special bootstrap mode.
8-
Digital Inputs (9). The bank of digital input ports is here. From right to left, the digital
inputs are numbered 7 to 15.
9-
Analog Inputs (7). The bank of analog input ports is here. From right to left, the analog
inputs are numbered 0 to6.
10- IR Output and Indicator. The infrared output port is here. The red indicator LED lights
when the output is enabled.
11- IR Input Sensor. The dark green-colored infrared sensor is here.
12- Analog Expansion Header. The analog expansion header is a 1x4 connector row located
above analog inputs 0 to 3.
13- User Knob. The user knob is a trimmer potentiometer whose value can be read under user
program control.
14- Battery Trickle-Charge Connector. The battery charge connector is a coaxial power jack
capable of accepting a 12V signal for trickle-charging the HB’s internal battery.
15- Charge Indicator. The yellow charge indicator LED lights when the HB is charging via the
coaxial power jack.
16- SPI Expansion Header. The SPI expansion header is a 2x4 pin jack that allows connection
with the 6811’s serial peripheral interface circuit. See the CPU and memory schematic
diagram for a pin-out of this connector.
17- LCD Screen. The HB is provided with a 16x2 LCD screen which can display data under
user control.
18- Piezo Beeper. The HB has a simple piezo beeper for generating tones under user control.
19- Power Expansion Header. The power expansion header is a 1x4 pin jack that provides
access to the unregulated motor power and ground signals.
9
Configuring The HB For Use
The HB, as any other microcontroller board, requires the programmer to download their
programs Motorola hex file (also called an S19 record) into the HB memory. This hex file is
created when an assembly code program is assembled. For the HB to run IC (the ability to run C
programs interactively), a program named “pcode_hb.s19” must be downloaded into memory.
The downloader must also modify the CONFIG register, initializing the 6811’s memory map
(see table 1). This configuring of the CONFIG register is automatic for the Handy Board
downloader (hbdl) shipped with the HB. Hbdl is specifically written for MS Windows, however
there are other downloaders available for use with Macintosh and Unix host computers.
To use the downloader, run the hbdl.exe application and select “pcode_hb.s19”. Also verify that
the text box for the CONFIG register has the value “0c” to properly configure the memory map.
HB Memory
The HB has 32K of on board RAM which is external to its CPU, the 6811. This causes one
peculiarity that requires attention before writing program code that contains interrupt vectors.
The HB operates in a special mode. This special mode allows the 6811 to switch between
expanded mode operation (the mode in which the external RAM is active) and single-chip mode.
The HB uses the single-chip mode to communicate with the LCD. This causes the 6811’s
interrupt vector bank to be located at $bfc0 to $bfff rather than the normal area of $ffc0 to $ffff.
Device
68HC11 internal
RAM
68HC11 control
registers
Expansion I/O
Bank 0
Location
$0000-$00ff
(A1 chip)
$1000-$103f
$4000-$4fff
Notes
Built-in. Because of varying internal RAM with different
chips this area may extend out to $01ff.
Built-in
Expansion I/O
Bank 1
Expansion I/O
Bank 2
Digital inputs
$5000-$5fff
Memory reads in this range enable the Y1 latch selector,
present on the HB expansion bus. Memory writes in this range
enable the Y0 latch selector, present on the HB expansion bus.
Reads enable Y3; writes enable Y2. See explanation above.
$6000-$6fff
Reads enable Y5; writes enable Y4. See explanation above.
$7000-$7fff
Motor outputs
$7000-$7fff
External RAM
$8000-$ffff
The digital inputs consist of the two switches and sensor ports
10 through 15. A memory read from this range returns the
value of the digital input byte.
A memory write to this range controls the motor outputs. The
low four bits are motor direction, and the high four bits are
motor enable (1=on).
The 32K of battery-backed memory is mapped to the upper
32K block of the 6811 address space.
Table 1: HB Memory Map
10
The HB Data Bus
The HB’s 8-bit data bus has three primary functions: Interfacing with the LCD and the two
motor controllers, and bussing in data from the digital input header on the HB. Port C on the
6811 is used for the data bus connection to the 6811. The HB allows external devices to
communicate with it. The HB incorporates an expansion bus to select which external devices are
active on the data bus by enabling latch selects. For this demonstration, the expansion bus will
provide control signals for two latches on the proto-board, latching data onto and off of the data
bus.
The HB Expansion Bus
The expansion bus uses a memory mapped I/O scheme. There are a total of eight latch select
pins (Y0-Y7) available to control devices connected to the HB’s data bus, one of these are used
by the output motor selection and another is used by digital input from the HB’s digital input
header. The other latch select pins are available for use on the expansion bus. The 74HC138 IC
labeled U6 (see figure 4, CPU and Memory Circuit) is an 8-3 decoder. The outputs of this
decoder are the eight latch select bits Y0-Y7. The operation of this decoder is shown in table 2
below.
A13 A12 R/W'
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Address Range
$4000-$4FFF
$4000-$4FFF
$5000-$5FFF
$5000-$5FFF
$6000-$6FFF
$6000-$6FFF
$7000-$7FFF
$7000-$7FFF
I/O
O
I
O
I
0
I
O
I
Latch selector
Y0- enabled by a write
Y1- enabled by a read
Y2- enabled by a write
Y3- enabled by a read
Y4- enabled by a write
Y5- enabled by a read
Y6- in use by digital input
Y7- in use by motors
Address bits A13, A12 and the R/W bit are used as inputs in the 8-3 decoder.
The outputs of the decoder are latch select bits Y0-Y7.
Table 2: Decoder Operation
The scheme is to read or write to one of the address ranges which then generates the appropriate
signals on A13, A12, and R/W'. These signals are then decoded and a signal is directed to one of
the 8 latch select pins. For this demonstration Y0 and Y1 were chosen to be the latch selector
pins.
11
Figure 4: CPU and Memory Circuit
12
I/O Buses
Data on I/O buses #1 and #2 are controlled by the use of two Dm74374 latches characterized by
the following truth table.
Output Control
L
L
L
H
Clock


L
X
D
H
L
X
X
Output (Qn+1)
H
L
Qn
Z
Qn+1
Qn
Z
H
L
X
= Next Output
= Present Output
= High Impedance
= True (5V)
= False (0V)
= Don’t Care
Table 3: DM74374 Truth Table
I/O Bus #1
Because I/O buses #1 and #2 terminate at the same latches, their physical and logical structures
are best described in two parts. For I/O bus #1, part one describes the flow of data from the
HB’s data bus to the output of first latch (this output is then directed to the SRB’s LED’s), while
part two describes the data flow from the input of the second latch (this input is from the SRB’s
data output) to the HB’s data bus.

Part one
When a write statement to the address range $4000-$4fff is encountered in program code, a
signal is generated on pin Y0 of the expansion header which is connected to latch-1’s clock
pin. Y0 is normally in a high state and the write statement drives it low for several clock
cycles. On the rising edge of this signal (Y0), the data is latched into latch-1’s D-type flipflops. With the data held in the latch, the output control pin must be driven low to release
this data from the output gates of latch-1 to the SRB’s LED’s. Because the output of this
latch drives only the SRB’s LED’s, and we desire the LED’s to continually display the most
recently latched data, the output control pin is not driven low but is grounded to the protoboard.

Part two
Similarly, when a read statement to the address range $4000-$4fff is encountered in program
code, a signal is generated on pin Y1 of the expansion header which is connected to both the
clock and output control pins of latch-2. Y1 is normally in a high state and the read
statement drives it low for several clock cycles. On the rising edge of this signal (Y1), the
data from the SRB is latched into latch-2’s D-type flip-flops. Because the output of this latch
is connected to the HB’s data bus it cannot remain in a constant output state as is the case for
latch-1. Therefore, the control signal on (Y1) also puts the output gates of latch-2 back into
a high impedance state (Z) as it returns to a high state.
13
As explained above, the rising edge of Y1 triggers the latching of data from the SRB, yet the
output control releases the data to the HB’s data bus as soon as Y1 goes low. Therefore, the
data being released to the HB’s data bus is one latching cycle behind the most recent data.
This could easily be remedied through hardware or software. However, this latching cycle is
less than 50s which is much faster than the data can actually change coming from the
SRB’s digital data output switches.
I/O Bus #2
The characterization of the latching process from the HB’s data bus to the output of the latch-1
and the latching of the data from the SRB’s data output at latch-2’s input to the HB’s data bus
was described above. Data bus #2 is simply the physical conduit for the transfer of data between
the proto-board and the SRB. The actual connection from the proto-board to the SRB is
described in the proto-board setup section.
Physical Setup
HB Setup
To gain access to the data and control pins of the LCD header on the HB, a 16-pin cable must be
used. Unfortunately, most cables provide female connections on each end, which creates a
problem with the HB header connections. Specifically, the HB’s LCD header, as well as all the
headers on the HB, is a female header. Eight of these pins are data bus connections and the
additional six pins are used for control of the LCD. The proto-board uses standard male headers.
Any size header may be used. For this demonstration (because of availability), a 34-pin header
is used and the extra eighteen pins are simply not connected. A cable with standard female
connectors on each end can be used by inserting pins into one end of the cable, thus enabling a
male configuration on one end of the cable. For this demonstration, the sixteen pins inserted into
the cables end were extracted from a spare header. This male end of the cable is then connected
to the female LCD header on the HB, and the female end of the cable is connected to the male
header on the proto-board.
As discussed earlier, the LCD must be present upon start-up of the HB. Therefore, the LCD
must be relocated. The LCD detaches as a self contained unit form the HB, and its row of
fourteen pins can be plugged directly into the proto-board. Then all that is required to operate
the LCD on the proto-board is to route each of the 14-pins from the proto-board header to the
relocated LCD.
Two of these 14-pins are power and ground from the HB. For this demonstration, the power pin
(5V) supplied power to the LCD only, while the ground pin (0V) supplied a common ground
between the HB and the proto-board. Because the SRB and the latches on the proto-board also
require a 5V power source, and the HB could not supply enough power to operate the SRB, an
additional power supply is connected to the proto-board and the SRB. The proto-boards power
and ground terminals should also be connected to this power supply to provide power for the
proto-board and a common ground to all components. However, do not connect the HB’s power
pin, at the HB to proto-board header, to the additional power supply.
14
Proto-Board Setup
The header connection for the HB to proto-board was explained above. The only other header
connection on the proto-board is the proto-board to SRB header. Fortunately, the SRB cable is a
standard 34-pin female cable that will plug directly into a standard 34-pin header. For this
demonstration, sixteen pins on the proto-board to SRB header must be used. Eight of these pins
drive the LED’s and one 7-segment display and the other eight pins except the eight data outputs
from the SRB. See figure 3 for the pin-out of the SRB cable.
Vcc
74374
8
D0-D7
GND
OC
8
8
<
CLK
Latch-2
Vcc
GND
8
<
8
6
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
Latch-1
74374
Y0
Y1
Y2
Y3
Y4
Y5
Toc3
AS
A15
Mem
Pwr
OC
LCD
GND
+5V
VR
A9
A8
Toc4
D0
D1
D2
D3
D4
D4
D6
D7
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
SRB
Header
CLK
Relocated from HB
Expansion Header
(Handy Board)
LCD Header
The proto-board also supplies power to the latches. Route power from the proto-boards power
terminal to the power pin (Vcc) of each latch. Also, route the proto-boards ground terminal to the
ground pin (GND) of each latch. Figure 3 is the interface schematic and shows all connections
for this demonstration.
(proto-board)
Figure 5: Interface Schematic
15
8
SRB
Switches
0-7
SRB LED’s
0-7
8
 LCD Header
Header
 Expansion
Figure 6: HB Header Pin-outs
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Interactive C (IC)
General Description
IC is a C language consisting of a compiler and run-time machine language module. IC
implements a subset of C. This subset includes control structures (for, while, if, else), local and
global variables, arrays, pointers, structures, 16-bit and 32-bit integers, and 32-bit floating point
numbers.
IC works by compiling into pseudo-code for a custom stack machine, rather than compiling
directly into native code for a particular processor. This pseudo-code (p-code) is then interpreted
by the run-time machine language program. This unusual approach to compiler design allows IC
to offer the following design tradeoffs:

Error Checking. Interpreted execution that allows run-time error checking.

Small objective code.
representation.

Multi-tasking. Because the pseudo-code is fully stack-based, a process’s state is defined
solely by its stack and its program counter. It is then easy to task-switch simply by loading a
new stack pointer and program counter. This task-switching is handled by the run-time
module, not by the compiler.
Stack machine code tends to be smaller than a native code
Since IC’s ultimate performance is limited by the fact that its output p-code is interpreted, these
advantages are taken at the expense of raw execution speed.
The concept behind IC is to allow interactive program debugging and testing. Once a working
program is written it is downloaded into the HB’s memory, and then the HB may be
disconnected from the host PC. The HB is now in stand-alone operation and may be interfaced
with a device, machine, robot, or for the purpose of this demonstration, the proto-board
interfacing with the SRB.
Running IC
The HB must be configured as explained in “Configuring the HB for use” before IC may be
executed from the host PC. This configuring procedure is a one time event as long as the HB’s
battery pack is cable of powering the static ram IC’s on the HB. Assuming that the HB has been
properly configured, and the proto-board has been supplied power to run the LCD and latches,
you simply run the IC executable file from the host PC.
When IC is run it synchronizes with the HB and then downloads various files including C
functions that the HB uses to operate its on board devices such as the motor driver IC’s and the
LCD. Figure 7 is a screen shot of the host PC after IC has been executed.
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Welcome to Interactive C v3.1
Copyright © 1997 Newton Research Labs. All Rights Reserved.
http://www.newton labs.com/ic
Bugs to ic@newtonlabs.com
This IC license is for Windows (Educational/personal license).
6- user license for: Michigan State University
Synchronizing with board
Pcode version 3.10 present on board
Loading C:\TEMP\pete\IC\libs\lib_hb.lis
Loading C:\TEMP\pete\IC\libs\lib_hb.c
Loading C:\TEMP\pete\IC\libs\r22_ir.lis
Loading C:\TEMP\pete\IC\libs\r22_ir.icb
Loading C:\TEMP\pete\IC\libs\lr22_ir.c
Initializing interrupts
Downloading 1724 bytes (address 8000-86BB) : 1724 loaded
Downloading 78 bytes (address 86BC-8709) : 78 loaded
Downloading 1724 bytes (address 870A-8719) : 16 loaded
Code loaded.
IC>
Figure 7: IC Initialization Screen Shot
The final line in figure 7 shows the IC command prompt (IC>). IC is now ready for user input.
A user written program must be downloaded to run on the HB. Figure 8 shows the simple
procedure for downloading and the running a user written program.
IC> load srb_interface.c
Loading C:\TEMP\pete\IC\|libs|srb_interface.c.
Initializing interrupts
Downloading 2436 bytes (address 8000-8983) : 2436 loaded
Downloading 78 bytes (address 8984-89D1) : 78 loaded
Downloading 16 bytes (address 89D2-89E1) : 16 loaded
Code loaded.
IC>srb_io();
Downloading 6 bytes (addresses C200-C205) : 6 loaded
Figure 8: Loading User Program Screen Shot
The first seven lines of figure 8 show a user written C program being loaded into the HB’s
memory. The last two lines of this figure show how a function from a C program is executed
simply by typing the exact syntax of a line of C code. Notice that a semicolon is the last
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character on the command line just as it would be in a C program. In the above example, a
function within srb_interface.c was run. Many other C instructions may be run from the
command line. Notice in figure 6 that after the function call was made from the command line,
the code was downloaded but there was no return to the IC command line. The function was an
infinite loop written for this demonstration and never returns control to IC.
Figure 9 shows a simple C instruction for adding two integers that does return control to IC, and
in this example it returns data along with control.
IC> 2+2;
Downloading 7 bytes (addresses C200-C206) : 7 loaded
<int> 4
IC>
Figure 9: Running Simple Interactive Command
Software
Program Code
For this demonstration, the following C program code was used to read and write data onto and
off of the HB’s data bus.
/************************************************************/
/* srb_interface.c
*/
/* Target: MC68HC11 on a Handy Board
*/
/* by:
*/
/* Pete Jackson
*/
/* Michigan State University
*/
/* jacks234@pilot.msu.edu
11-22-97
*/
/************************************************************/
/* This C program reads in data from the SRB and sends it */
/* back out, for display, to the SRB's array of LED's.
*/
/************************************************************/
void srb_io()
{
int data;
/* SRB switches 1-8
*/
while(1)
{
data = peek(16385);
/* infinite loop */
poke(16385, data);
/* latch data from HB data bus */
/* to SRB LED's
*/
/* latch data onto HB data bus */
/* from SRB.
*/
}
}
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The while(1) expression provides for an infinite data bus monitoring loop. Memory mapping is
used by the peek and poke expressions to control the latches via the HB’s expansion bus. The
latch selector pins Y0 and Y1, are enabled by accessing the memory range $4000-$4FFF. Notice
that the peek and poke expressions use the decimal equivalent of $4000 which is 16385 decimal.
Summary
The purpose of this demonstration was to guide junior level electrical engineering students
through the process of accessing the HB’s data bus. The student should have introductory
courses in digital logic and microprocessor architecture.
This report was written in a “step by step” format. First, a system-level description was provided
to give the student an overall view and allow them the opportunity to generalize what materials
and skills would be required to complete the demonstration. Second, an in-depth look at the HB
itself, from both a hardware and software perspective, provided all the necessary information to
complete the demonstration. Third, the software control of latching data onto and off of the I/O
buses was described. Fourth, the actual physical setup was described. Finally, a brief outline of
IC and how it was incorporated in this demonstration was provided. Additionally, screen shots
of actual IC sessions along with the C code for this demonstration were provided.
Included in the format of this report were various tables and schematics provided at key locations
to reduce ambiguity and help the student understand physical components and their connections,
system setup, and software use.
20
Appendix
DM74AS374 Octal D-Type Edge-Triggered Flip-Flop with TRI-STATE Ouputs
This appendix contains the technical data sheet for the DM74AS374 Octal Lacth and was
downloaded from National Semiconductor’s web site at:

http://www.national.com
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