Efficiency Comparison Paper
ECE445 – Winter 2011
Portland State University
Tuan Tran Trong
David Rusnac
Dat Nguyen
Introduction:
Circuits that have a voltage conversion ratio of M(D) = D all step down voltages and our
task is to find a way to compare these different converters to be able to pick the most
efficient one. When working with an ideal converter circuit, the voltage conversion ratio
V/Vg can be found. In this case all circuits will have a conversion ratio of V/Vg = D which is
a step down converter. When doing the same analysis with non-ideal components, the
same conversion ratio will be found, but with an additional factor. This factor will be the
efficiency of the circuit. An efficiency analysis was done for all converters that had a
conversion ratio of D and we limited our analysis to only converters that had two switches
and at most 2 inductors and capacitors. Only inductor losses were accounted for and
switching losses were neglected.
Part 1: Summary
Efficiency (  )
Converter
A1

C1





1

  
2
2
 D R1 D' R2 
1



R
R 





1

  
 R2 D'2 R1 


1
R 
 R
D4

D6


 1 

  
RL 

1 
 R 

E2





1

  
2



D R1 R2 
 
1
R
R 





1

  


R
R
1 1  2 


 R R 





1

  


1 R1  R2 


 R R 





1

  


R
R
2
1 2  1 D' 



 R R
E5
F1




1

  
 D2 R1 R2 
 
1
R
R 

F3


Conclusion:
Based on the results, two distinctions come to light. The first is that A1 has only 1 inductor
so in most cases; this circuit will be most efficient because of less inductor losses. The
second observation can be made that not all of the converter’s efficiency depend on the
duty cycle. Their efficiency will be constant with any duty cycle where as the rest of the
circuits will vary based on duty cycle. This is most easily viewed in graphical form. If R1
and R2 are assumed to be similar in resistance value, and the load resistance is significantly
larger that both R1 and R2, we can plot efficiencies against duty cycle.
From this graph we can see that in the most general case A1 will be the most efficient due
to it lack of second inductor but if we compare only converters that have 2 inductors we
see that C1 will be the most efficient converter. Converter D4 is more efficient at higher
duty cycles but we see at lower duty cycles it’s efficiency drops off significantly.
In general we can conclude that if there is no preference to complexity, A1 will be the most
efficient converter but when comparing the converters with 2 switches and two inductors
C1 will provide on average the greatest efficiency of the discussed converters.
Part II: Analysis
A1 Efficiency Analysis: S2: M=D
For Time Interval DTs
For Time Interval DTs
Inductor Voltage
Inductor Voltage
Vg  v L  iRL  V  0
vL  IRL  V  0
vL  IRL V
vL  Vg  IRL V

Capacitor Current


iL  iC 
V
R

iC  iL 
V
R

iC  I 


V
R

Capacitor Current
iC  I 
V
R
Volt-Second Balance
0  DVg  IRL V  D' IRL V 
V  DVg  IRL

I is substituted in from average capacitor current

I
V
R
V  DVg 


VRL
R
 R 
V 1 L  DVg
 R 




V
1 

 D
RL 
Vg

1 
 R 



 1 

  
RL 

1 
 R 

C1 Efficiency Analysis: S2: M=D
For Time Interval DTs
For Time Interval DTs
L2 average voltage
L2 Average Voltage
V  vC1  vL 2 I 2R2
vL2  i2R2  V
v L 2  V  I2 R2
v L 2  V  VC1 I 2R2

For DC:

No DC current through C1 and C2

VC1  V I1R1 I 2R2

I 2 
v L 2  V  Vg I1R1 I 2 R2 I 2 R2

v L 2  V  Vg  I1R1

No DC current through C1 or C2

I1
V
R
v L 2  V Vg 

vL 2  V 


V
R1
R
V
R
V
R2
R
Volt-second balance for Inductor L2:

 V 
V 
0  DV Vg  R1 D'V  R2 


R 
R 
V  D


V
V
R1  D' R2  DVg
R
R
 DR1 D' R2 
V 1

 DVg

R
R 





V
1
 D
DR1 D' R2 
Vg
1



R
R 





1
  
DR1 D' R2 
1



R
R 

D4 Efficiency Analysis: S1: M=D
For Time Interval D’Ts
For Time Interval DTs
Inductor Voltages
Vg  vC1  v L1  I1R1  0
Inductor Voltages
vL1  Vg  I1R1 VC1
Vg  vC1  v L1 i1 R1  0
vL1  Vg VC1  I1R1


Vg  v L 2 i 2 R2  V  0


vL 2  Vg I 2R2 V

VC1  Vg I1R1 (ForDC)
Capacitor Currents

VC1  Vg I1R1 (ForDC)


Capacitor Currents


iC 2  iL 2 
V
R
iC 2  I2 



iC1  I1
V
R
Vg  vC1  v L 2 I 2 R2  V
vL2  Vg I 2R2 V VC1
iC 2  I2 
V
R
iC1  I1  I2


Volt-Second Balance for L2:
0  DVg I 2R2 V  D' Vg I 2R2 V VC1
0  DVg I 2R2 V  D' Vg I 2R2 V Vg I1R1

Charge balance for C1:

0  DI1  D' I1  I2 
I1  D' I2 

Charge balance for C2

 V 
 V 
0  DI2   D'I2  


R 
R 
I2 
V
R
I1 
D'V
R




Substituting Currents back into charge balance equation


 V
V
D'V 
0  DVg  R2 V  D' R2 V 
R1 


 R

R
R
 R D'2 R1 
V 1 2 
 DVg
R 
 R





V
1
 D

2
Vg
1 R2  D' R1 
 R
R 





1
  

2
1 R2  D' R1 
 R
R 

D6 Efficiency Analysis: S2: M=D
+
I1
VL1
+
DTs:
I1
+
I2
-
V
VL2
+
V1
V2
-
-
D’Ts:
+
I2
VL1
+
+
V
VL2
+
V1
V2
-
-
Volt-second balance:
Charge balance:
I1
+
VL1
+
+
I2
V
VL2
V1
+
V2
-
-
E2 Efficiency Analysis: S2: M = D
I1
I2
V
I1
DTs:
D’Ts:
I2
+ V1 I1
+ VL1
-
+ VL2
-
+
-
Volt-second balance:
Charge balance:
V
E5 Efficiency Analysis: S1: M = D
DTs:
DTs:
Charge balance on C1, C2:
Volt-second on L1, L2:
F1 Efficiency Analysis: S2: M=D
For Time Interval DTs
For Time Interval D’Ts
Inductor Voltages
vL1  i1R1 VC1  V
Inductor Voltages
v L1  I1R1  VC1  V


vL1  VC1 i 2 R2  V
v L 2  i 2 R2  Vg  V
vL 2  I 2R2  Vg V
v L1  VC1 I 2 R2  V

vL2  i 2 R2 VC1

Capacitor Currents

v L 2  I 2 R2  VC1

iC1  iL1  I1

Capacitor Currents

iC1  i1  i2
iC 2  iL 2  iL1 

V
V
 I2  I1 
R
R
iC1  I1  I2



iC 2  i1 
V
R
iC 2  I1 

V
R
 Average Inductor Voltage for L1:
0  DI1R1  VC1  V   D' VC1 I1R1  V 
Average Inductor Voltage for L2:

0  DI 2R2  Vg V  D' I 2R2 VC1
Charge balance for C1:

0  DI1  D' I1  I2 
I1  D' I2 

Charge balance for C2



V 
V 
0  DI2  I1   D'I1  


R 
R 
Substituting I1 and I2



I2 
V
R
I1 
D'V
R
Substituting Currents back into volt-second balance equations



V
V 
0  DVg  R2 V  D'VC1  R2 



R
R 
0




V
R2  DVg  DV  D'VC1
R




VD'
VD'
0  DVC1 
R1  V  D'VC1 
R1  V 




R
R
 R 
VC1  V 1 1 D'
 R 
 R 
VR2
 DVg  DV  D'V 1 1 D' 0
 R 
R


 R R

DVg  V 1 2  1 D'2 
 R R

V
1
D
 R2 R1 2 
Vg
 D' 
1
 R R




1
 R2 R1 2 
 D' 
1
 R R

F3 Efficiency Analysis: S1: M=D
For Time Interval D’Ts
For Time Interval DTs
Inductor Voltages
Inductor Voltages
v L1  Vg i1R1  VC1  V
v L1  Vg  V  VC1 i1R1
vL1  Vg V VC1 I1R1
vL1  Vg I1R1 VC1 V

vL2  i 2 R2 VC1

vL2  V i 2 R2
v L 2  V I 2 R2

v L 2  I 2 R2  VC1


Capacitor Currents

Capacitor Currents

iC1  iL1  iL 2

iC1  i1
iC1  I1
iC1  I1  I2


iC 2  iL1 
V
R
iC 2  I1 


V
R


iC 2  i1  i2 
V
R
iC 2  I1  I2 

V
R
 Average Inductor Voltage for L1:
0  DVg I1R1 VC1 V  D' Vg V VC1 I1R1
Vg  V  VC1 I1R1  0

Average Inductor Voltage for L2:

0  DI 2 R2  VC1   D' V I 2 R2 
VC1D D'V I 2R2  0

Charge balance for C1:

0  DI1  I2   D' I1 
I1  DI2 

Charge balance for C2

 V 

V 
0  DI1   D'I1  I2  
 R 

R 
Substituting I1 and I2



I2 
V
R
I1 
DV
R
Substituting Currents back into volt-second balance equations
 D 
VC1  Vg V 1 R1 
 R 
VC1  VD'



VR2
0
R
 D 
V
0  Vg D  V 1 R1 D  VD' R2
 R 
R
D2 R1
R 
V 
 D  D' 2  Vg D
R 
 R

V
1
D
2
 D R1 R2 
Vg
 
1
R
R 




1
 D R1 R2 
 
1
R
R 

2