ELEC 350L
Electronics I Laboratory
Fall 2005
Lab #13: MOSFET Amplifier Bias Design
Introduction
MOSFET amplifier circuits must have the proper biasing levels in order to work properly. A
frequent requirement is to design the bias circuit so that the quiescent voltages and currents
remain close to target values in spite of variations in device parameters. In other situations the
repeatability of specific voltage and current levels is not so important, but their stability is. In
these cases the bias currents and voltages must not vary as environmental conditions (mostly
temperature) change. In this lab exercise you will design and test a bias circuit for a 2N7000
n-channel enhancement-mode MOSFET.
Theoretical Background
The bias levels in MOSFET amplifiers are often stabilized using the source degeneration
technique, in which a resistor is placed between the device’s source and ground. The resistor
creates negative feedback, which forces the quiescent drain current to remain at its design value
regardless of changes in the MOSFET’s parameters (Kn = 0.5nCoxW/L and Vt). Shown in
Figure 1 is a common-source MOSFET amplifier that uses this bias stabilization method. If the
drain current ID begins to rise above its intended quiescent value, the voltage drop across RS
increases. Since the gate-source voltage VGS is the difference between the gate potential VG and
the voltage across RS, a rise in the voltage across RS causes VGS to drop, which in turn forces ID to
move back toward its original value. The opposite chain of events occurs if environmental
factors cause ID to drop below its intended value.
VDD
RA
ID
RD
Ci
vg
VD
VG
+
+
VGS
−
Co
RB
RL
−
+
VRS
RS
−
Figure 1. Common-source amplifier using an n-channel enhancement-mode
MOSFET with source degeneration.
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The quiescent drain current ID in an amplifier with source degeneration must simultaneously
satisfy the two relations
2
and VGS  VG  I D RS ,
I D  K n VGS  Vt 
where Kn is the conductance parameter of the MOSFET, and Vt is the threshold voltage. The
quantity VG is the gate voltage measured with respect to ground. Combining the two equations
by eliminating VGS leads to the quadratic equation
1

2
RS2 I D2    2 RS VG  Vt  I D  VG  Vt   0 .
K

The solution is
ID 
VG  Vt
1
1


1  4 KRS VG  Vt  .
2
RS
2 KRS 2KRS2
The sign ambiguity is resolved by applying the constraint VGS > Vt. Since VGS = VG – IDRS, then
VG  I D RS  Vt

VG  Vt
 ID .
RS
Substituting the expression for ID into the inequality makes it evident that the lower sign (−)
corresponds to the physically meaningful solution. Thus,
ID 
VG  Vt
1
1


1  4 KRS VG  Vt  .
2
RS
2KRS 2 KRS2
A plot of this expression for ID versus K shows that the drain current is relatively insensitive to
this parameter. However, changes in the threshold voltage Vt can cause significant changes in ID.
Nevertheless, the changes are much less severe than if the source resistor RS were not present.
The complicated expression for ID derived above does not suggest a straightforward approach for
selecting values of VG and RS to achieve a target bias level. Furthermore, the input-to-output
voltage transfer characteristic (vD vs. vG, where each voltage is now the sum of bias and signal
voltages) of the common-source amplifier, even with a source degeneration resistor, is nonlinear.
It is therefore difficult to determine an optimum value to which the quiescent drain voltage VD
and/or the quiescent drain current ID should be set. Because of the square-law nature of the
relationship between ID and VGS, the output voltage swing is not symmetrical. In practice, most
designers turn to a common rule of thumb in which the quiescent voltages across RD, across the
drain-source terminals (i.e., VDS), and across RS are simply each set equal to approximately onethird of VDD. That is,
1
I D RD  VDS  I D RS  VDD ,
3
from which the values for RD and RS can be found directly if the nominal value of ID is specified.
(The bias level of the drain current is often dictated by the desired value for the small-signal
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transconductance gm.) The appropriate value of the quiescent gate voltage VG can then be found
by combining the relationships
I D  K n VGS  Vt 
2
which leads to
and
VGS  VG  I D RS ,
I D  K n VG  I D RS  Vt 
2
VG  I D RS  Vt  I D K n
VG  I D RS  Vt  I D K n .
The positive value of the square root is used because it corresponds to the requirement that VGS >
Vt. Of course, this method for selecting the value of VG depends on knowing the values of Kn
and Vt, which vary considerably because of manufacturing tolerances and temperature effects.
(The parameters n and Vt are especially sensitive to temperature.) For example, a typical range
for Vt might be 1-3 V. It is therefore difficult, if not impossible, to set a quiescent drain current
value that is repeatable from circuit to circuit. Bear in mind, however, that the presence of the
source degeneration resistor RS will force the drain current to remain close to whatever value it
happens to have. Thus, even though we cannot set ID to a specific value with much precision, we
can make sure that it has negligible drift. In practice the nominal values of Kn and Vt, obtained
either from a data sheet or via measurements, are used to find VG. Since the value of VGS must be
greater than Vt in order to avoid the cut-off region, it is often advisable to set VG slightly higher
than the value suggested by the formula above. The voltage divider network formed by RA and
RB establishes the value of VG in the circuit. Since zero current flows into the gate, VG is related
to VDD by
RB
.
VG  VDD
R A  RB
The parallel combination of the gate biasing resistors (i.e., RA || RB) is typically set to a large
value (1 M or more) in order to maintain a high input impedance for the amplifier.
In most design situations the actual value of ID is less important than ensuring that the MOSFET
operates in its constant current region. Amplifiers like the one shown in Figure 1 are usually
used with very small signals (i.e., those that have peak-to-peak amplitudes of a few mV or less).
In these cases the output voltage swing, and therefore the drain current swing, will be tiny
compared to the corresponding quiescent values (a few millivolts vs. a few volts). Although the
transfer characteristic of a MOSFET amplifier is highly nonlinear over its full extent, it is
approximately linear over small portions of that range. The small-signal voltage gain is equal to
the slope of the transfer characteristic at the Q-point. If the actual quiescent output voltage
differs from its intended value, the small-signal voltage gain will differ from the target value as
well, but usually this difference is not too great and can be tolerated in a practical circuit. If
many copies of a circuit are needed with predictable bias levels, then it might be necessary to
screen the stock of MOSFETs that will be used in the production of the circuit to eliminate those
devices that have parameters outside the acceptable limits. If very precise bias control is
required, however, then other circuits should be used.
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Experimental Procedure
You will not be required to record lab notebook entries this week. Instead, your grade will be
based on the successful completion of the following four tasks (one point per task). Each
member of your lab group will receive the same grade.

Select three 2N7000 MOSFETs from the available stock. Devise a way to use the circuit
shown in Figure 2 to determine Vt and Kn for all three MOSFETs. Use the 0-6 V power
supply to create a variable gate-to-source voltage VGS, and adjust the 0-25 V power supply to
provide a VDD of around 10 V. The drain resistor RD can be just about any value in the range
of 5-10 k or so. Hint: Use the multi-meter to monitor the voltage across RD as you change
VGS. Record the values of Vt and Kn for all three MOSFETs. Demonstrate your circuit and
your parameter determination method to the instructor.
VDD
ID
VGS
RD
+
−
Figure 2. Test configuration for determining Vt and Kn.

Design a four-resistor bias circuit (RD , RS, RA, and RB) for a 2N7000 amplifier circuit with
source degeneration like the one shown in Figure 1. The design specifications call for a
power supply voltage VDD of 12 V and a quiescent drain current of ID = 2 mA. Use any
reasonable rule of thumb for the quiescent voltages across RD and RS. Base your design on
the range of values for Vt and Kn either given in the data sheet or measured by you. For each
bias resistor, use a single unit with the standard value closest to your calculated value. Show
a brief outline of your design, with resistor values clearly indicated, to the instructor.

Insert three different MOSFETs into the four-resistor bias circuit and measure the quiescent
output voltage VD for each one. For each MOSFET, calculate the percentage error by which
the measured value of VD varies from the target value. Hold each MOSFET between your
fingers for 30 seconds to warm it up, and record the new VD value at the higher temperature.
Demonstrate the behavior of the circuit to the instructor.

Rebuild the circuit shown in Figure 2, using the same value for RD as you used in your fourresistor bias circuit. Insert one of the MOSFETs into the circuit, and adjust the value of VGS
(the 6-V supply) until VD = 8 V. With the instructor observing, hold the MOSFET between
your fingers for 30 seconds, and then measure the new value of VD. Compare the
temperature stability of this circuit to that of the four-resistor bias circuit.
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