Arieh Nachum
Decoders,
Multiplexers and
Adders
EB-3152
Arieh Nachum
Decoders,
Multiplexers and
Adders
EB-3152
1_11
© All rights reserved to DEGEM Systems.
The material in this book may not be copied, duplicated, printed,
translated, re-edited or broadcast without prior agreement in writing
from DEGEM Systems.
 20a Eliyau Eitan St., Rishon-Lezion  P.O.Box 5340, Rishon-Lezion 75151 Israel 
 Tel: 972-3-9535400  Fax: 972-3-9535423 
 E-mail: info@degem.com  Site: www.degem.com 
I
Contents
Preface ............................................................................................................. II
Experiment 1 – Constructing a Decoder ....................................................... 1
Experiment 2 – The Decoder........................................................................ 10
2.1
2.2
2.3
2.4
2.5
2.6
Integrated logic components ............................................................... 10
Binary and BCD decoders .................................................................. 11
1 of n decoder ...................................................................................... 16
The decoder as a decoder .................................................................... 19
Primary and secondary decoding ........................................................ 20
BCD to decimal as a 1 of 8 decoder ................................................... 22
Experiment 3 – Using a Decoder to Materialize a Function ..................... 32
Experiment 4 – Multiplexer Applied as a Multiplexer .............................. 41
4.1
A 1 of n mulitplexe ............................................................................. 41
Experiment 5 – Using a Multiplexer to Materialize Functions ................ 51
Experiment 6 – Binary Addition.................................................................. 59
6.1
Binary addition .................................................................................... 59
Experiment 7 – Binary Subtraction ............................................................ 70
Experiment 8 – Binary Comparison............................................................ 78
Experiment 9 – Troubleshooting ................................................................. 84
EB-3152 – Decoders, Multiplexers and Adders
II
Preface
The experiments in this manual are meant to be run on the experiment board
EB-3515 with the Universal Training System EB-3100.
The EB-3100 includes:
 5 voltages power supply (+12V, +5V, –5V, –12V and –12V to +12V
variable voltage).
 2 voltmeters.
 Ampere-meter.
 Frequency counters up to 1MHz.
 Logic probe (High, Low, Open, Pulse, Memory).
 Logic analyzer with 8 digital inputs and trigger input.
 Two channel oscilloscope (with spectrum analysis while connecting to the
PC).
 Function generator (sine, triangle and square wave signals) up to 1MHz.
 3.2" color graphic display with touch panel for signal and measurement
display.
 USB wire communication with the PC.
 20 key terminal keyboard.
 10 relays for switching the plug-in boards or for planting faults.
 48 pin industrial very low resistance connector for plug-in boards
connection.
 Transparent sturdy cover covers the upper part of the plug-in boards in
order to protect the board's components that should be protected.
EB-3152 – Decoders, Multiplexers and Adders
III
The EB-3100 boards are:
Electricity and Electronics
EB-3121
Ohm and Kirchoff Laws and DC circuits
EB-3122
Norton, thevenin and superposition
EB-3123
AC circuits, signals and filters
EB-3124
Magnetism, electromagnetism, induction and transformers
Semiconductor Devices
EB-3125
Diodes, Zener, bipolar and FET transistors characteristics and DC circuits
EB-3126
Bipolar and FET transistor amplifiers
EB-3127
Industrial semiconductors – SCR, Triac, Diac and PUT
EB-3128
Optoelectronic semiconductors – LED, phototransistor, LDR, 7-SEG.
Linear Electronics
EB-3131
Inverter, non-inverter, summing, difference operational amplifiers
EB-3132
Comparators, integrator, differentiator, filter operational amplifiers
EB-3135
Power amplifiers
EB-3136
Power supplies and regulators
EB-3137
Oscillators, filters and tuned amplifiers
Motors, Generators and Inverters
EB-3141
Analog, PWM DC motor speed control, step motor control, generators
EB-3142
Motor control – optical, Hall effect, motor closed control
EB-3143
AC-DC and DC-AC conversion circuits
EB-3144
3 Phase motor control
Digital Logic and Programmable Device
EB-3151
AND, OR, NOT, NAND, NOR, XOR logic components & Boolean algebra
EB-3152
Decoders, multiplexers and adders
EB-3153
Flip-flops, registers, and counters sequential logic circuits
EB-3154
555, ADC, DAC circuits
EB-3155
Logic families
Microprocessor/Microcontroller Technology
EB-3191
Introduction to microprocessors and microcontrollers
EB-3152 – Decoders, Multiplexers and Adders
IV
The EB-3152 is connected to the EB-3100 via a 48 pin industrial connector.
It has a built-in microcontroller that identifies (for the EB-3100 system) the
experiment board when it is being plugged into the system, and starts a selfdiagnostic automatically.
The following figure describes the EB-3152 experiment board.
B4
B6
Decoders
ADDERS
A
Y0
C0
B
Y1
A0
B2
B1
0
1 S0
0
1 S1
DEC1
0
Y2
G
Y3
1 S2
A
1 S3
1 S4
0
1 S5
C1
C1
D1
0
B1
C2
C2
D2
Y2
A2
FA2
Y3
IN1
L2
L3
C2
C3
D3
MUX
OUT
IN2
IN0 A
L5
L6
L7
IN0
BCD to
7-Seg.
B2
B5
B3
L1
L4
DEC2
1 S6
1 S7
FA1
L0
Y1
G
0
B7
Y0
B
0
FA0
B0
A1
0
D0
E
B
EB-3152 Panel Layout
EB-3152 – Decoders, Multiplexers and Adders
A3
B3
FA3
C2
V
The experiment method:
The system uses an external switching power supply for safety reasons. The
power supply low voltage output is converted to the 5 voltages by linear
regulators for noise reduction.
Two potentiometers on the panel are used to setup the variable voltage and the
function generator amplitude.
The system cut-off the voltages in overload and displays a massage about that.
The plug-in cards are connected directly to system without any flat cable for
noise and resistance reduction.
The 10 relays are change over relays that can switch active and passive
components.
Every selecting of a relay configuration is saved in a non-volatile memory
located on the connected plug-in card.
The components are located on the board with silk screen print of the
analytical circuit and component symbols. The central part of the
experimenting board includes all the circuit block drawings and all the hands
on components, test points and banana sockets.
The protected components are located on the circuit board upper side, clearly
visible to the student and protected by a sturdy transparent cover.
On plugging the experiment board, it sends a message to the EB-3100 which
includes the board's number and which of its block are faulty. If there is a
faulty module (B1-B8), it will be displayed on the screen.
The experiment board checks itself while it is being plugged. This is why,
during the plug-in, any banana wire should not be connected on the
experiment board.
5 LEDs should turn ON on the top right.
EB-3152 – Decoders, Multiplexers and Adders
VI
The system includes 5 power supply outputs. The system checks these
voltages and turns ON the LEDs accordingly.
+12V
+5V
–5V
–12V
–
–
–
–
Red LED
Orange LED
Yellow LED
Green LED
The fifth voltage is a variable voltage (Vvar) controlled by a slider
potentiometer.
The LED of the Vvar is both green and red: when the Vvar voltage is positive
– the color is red and when it is negative – the color is green.
There are no outlets for the power supply voltages on the
The voltages are supplied only to the 48 pin connector.
TSP-3100 panel.
The experiment boards take these voltages from the 48 pin connector.
EB-3100 Screens
The system has 3 operating screens: DVM, Oscilloscope and Faults.
Moving from one screen to another is done by the Options/Graph key.
The keyboard is always at Num Lock position.
The keys can also be used as function keys. In order to do so, we have to press
once on the Num Lock key and then on the required key. The keyboard
returns automatically to Num Lock mode.
On scope screen, pressing the Num Lock key and then the Digital key will
change the screen to Digital signal screen display.
Pressing the Num Lock key and then the Analog key will change the screen to
Analog signal screen display.
EB-3152 – Decoders, Multiplexers and Adders
VII
DVM Screen
DVM
V1 [V]
0.00
V2–V1 [V]
0.00
Fout [KHz]
5.00
V2 [V]
0.00
I [mA]
0.0
Cin [Hz]
5.00
I (+5V) [mA]
I (+12V) [mA]
0
0
I (–5V) [mA]
I (–12V) [mA]
0
0
Num Lock
V1 is the voltage measured between V1 inlet and GND.
V2 is the voltage measured between V2 inlet and GND.
V2–V1 is the voltage measured between V1 and V2. It enables us to measure
floating voltage.
I is the current measured between A+ and A– inlets.
Cin displays the frequency is measured in the Cin inlet.
The EB-3100 includes a function generator.
The frequency of the function generator is displayed in the Fout field and can
be set by the arrow keys or by typing the required values.
The square wave outlet is marked with the sign
.
Near the analog signal outlet there is a sine/triangle switch marked with the
signs
/
.
EB-3152 – Decoders, Multiplexers and Adders
VIII
Scope Screen
CH1 3.0VCH2
3.0V t 50s
CH1
1.0V
Num Lock Analog Run
The scope and the display parameters (CH1 Volt/div, CH2 Volt/div, time base
Sec/div, Trigger Channel, Trigger rise/fall, Trigger Level) appear on the
bottom of the screen.
The Up and Down arrow keys highlight one of the fields below.
The required field can be selected by touching it and can be changed by the
Up and Down arrows.
The function generator amplitude is changed by the amplitude potentiometer.
The sampling and display can be stopped by pressing the Num Lock key and
then pressing the Stop (8) key.
Performing a single sampling is done by pressing the Num Lock key and then
pressing the Single (9) key.
Running again the sampling is done by pressing the Num Lock key and then
pressing the Run (7) key.
EB-3152 – Decoders, Multiplexers and Adders
IX
Digital Screen
Pressing the Num Lock key and then the Digital key on scope screen displays
the Digital screen.
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
t 50s
TRIG
Num Lock Digital Run
Check that.
The logic analyzer includes 8 digital inlets and one trigger signal inlet.
The controller waits for trigger and when it encounters a trigger pulse it
samples the 8 digital inputs.
If a trigger pulse is not found the sampling will be according to the time base.
The sampling and display can be stopped by pressing the Num Lock key and
then pressing the Stop (8) key.
Performing a single sampling is done by pressing the Num Lock key and then
pressing the Single (9) key.
Running again the sampling is done by pressing the Num Lock key and then
pressing the Run (7) key.
EB-3152 – Decoders, Multiplexers and Adders
X
Logic Probe
The EB-3100 Logic Probe includes 5 LEDs indicating the Logic Probe (LP)
input state – High, Low, Open (unconnected), Pulses and Memory (registering
single pulse).
The Logic Probe also has a TTL/CMOS switch that determines which logic
level is selected.
When the LP is connected to a point with a voltage blow 0.8V (for TTL) or
1.3V (for CMOS), the L green LED should turn ON.
When the LP is connected to a point with a voltage above 2.0V (for TTL) or
3.7V (for CMOS), the H red LED should turn ON.
The voltage between these levels turns ON the OP orange LED.
Fault Screen
The EB-3100 includes 10 relays for fault insertion or for switching external
components.
The fault screen is selected by the Options/Graph key.
FAULTS
Please choose
Fault No.: 0–9
Activated fault
Number: 0
Num Lock
Typing a fault number and pressing ENTER operates the required relay for the
required fault.
Fault No. 0 means No Fault.
Which relay creates the required fault is registered in the plug-in experiment
board controller.
EB-3152 – Decoders, Multiplexers and Adders
XI
On entering a fault number, the system addresses the experiment board
controller and asks for the relay number. After that, it executes the required
fault.
The experiment board controller saves the last registered fault number in its
memory. This memory is non-volatile.
This is why the system does not allow us to enter a fault number when no
experiment board is plugged.
When an experiment board that a certain fault (other than zero) is registered in
its memory is plugged into the system, a warning message appears on the
system's screen.
This feature enables the teacher to supply the students various experiment
boards with planted faults for troubleshooting.
Note:
It is recommended (unless it is otherwise required), to return the
experiment board fault number to zero before unplugging it.
EB-3152 – Decoders, Multiplexers and Adders
XII
EB-3152 – Decoders, Multiplexers and Adders
1
Experiment 1 – Constructing a Decoder
Objectives:
After completing this experiment explain:
 How to construct a decoder with two inputs and four outputs.
Equipment required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
In digital systems, we often need a circuit for decoding a certain binary
combination. Such a circuit is easily constructed with gates.
Example:
A circuit whose output Y goes to '0' only when the combination 0101 appears
at its four inputs (A, B, C, D).
A
B
C
Y
D
Figure 1-1 A Dedicated 0101 Decoder
The AND gate decodes the state when all its inputs are '1'. When the output of
the AND gate is '1', we know for sure that all its inputs are '1'. When its output
is '0', we cannot know what is the state of its inputs.
EB-3152 – Decoders, Multiplexers and Adders
2
The NAND gate does the same, only its output is '0' in the decoding state (all
the inputs are '1').
We use inverters to change the required combination to '1111', to be decoded
by the AND or NAND gates.
We may add an inverter at the output or use an AND gate, thus achieving a
circuit whose output Y rises to '1' when the combination 0101 appears at its
four inputs.
The OR gate decodes the state when all its inputs are '0'. When the output of
the OR gate is '0', we know for sure that all its inputs are '0'. When its output is
'1', we cannot know what is the state of its inputs.
The NOR gate does the same, only its output is '1' in the decoding state (all the
inputs are '0').
We use inverters to change the required combination to '0000', to be decoded
by the OR or NOR gates.
A
B
C
Y
D
Figure 1-2 A Dedicated 0101 Decoder
A decoder circuit is a logic circuit with n inputs and 2n outputs. For each
combination of binary numbers at the inputs, one and only one of the outputs
is operated (one output for each combination).
EB-3152 – Decoders, Multiplexers and Adders
3
We will construct a decoder with two inputs and four outputs. In accordance
with the combination at the inputs, one of the outputs is activated (rises to '1'),
and all the other outputs are at '0'.
A1
A0
Decoder
Y3
Y2
Y1
Y0
Figure 1-3 Symbol for a Decoder
For example, Y2 = 1 when the combination of the inputs is 10.
We use AND gates and inverters to implement a decoder circuit for each combination.
Because each output represents only one combination, which is one square of the Karnaugh
map, we do not need the Karnaugh map. The construction of the decoder will be as follows:
Y3
Y2
Y1
A1
Y0
A0
Figure 1-4 Decoder Construction
The truth table of this circuit will be as follows:
A1 A0 Y3 Y2 Y1 Y0
0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Check this.
EB-3152 – Decoders, Multiplexers and Adders
4
Preparation questions:
1.
What is the binary number decoded by the following decoder:
(a)
(b)
(c)
(d)
2.
011
100
101
010
What is the binary number decoded by the following decoder:
(a)
(b)
(c)
(d)
011
100
101
010
EB-3152 – Decoders, Multiplexers and Adders
5
3.
What is the binary number decoded by the following decoder:
(a)
(b)
(c)
(d)
011
100
101
010
EB-3152 – Decoders, Multiplexers and Adders
6
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Construct the circuit described in the following figure step by step.
Y3
Y2
Y1
A1
Y0
A0
Step 7:
Connect the inputs A1 and A0 to the switches S1 and S0
accordingly.
Step 8:
Connect the output Y to the LED L0.
Step 9:
Set the states of A1 and A0 as described in the following truth table
and fill in the corresponding states of Y3, Y2, Y1, Y0.
A1 A0 Y3 Y2 Y1 Y0
0 0
0 1
1 0
1 1
Step 10: Check that the states of Y3, Y2, Y1, Y0 correspond with the outputs
of the decoder as described in the discussion section.
EB-3152 – Decoders, Multiplexers and Adders
7
Step 11: Implement the following circuit:
A
B
Y
C
Step 12: Connect inputs A, B and C to switches So, S1 and S2.
Step 13: Connect the output Y to a LED.
Step 14: Change the switches and fill the following table:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C Y
0
1
0
1
0
1
0
1
Step 15: Which is the decoded state of the inputs?
EB-3152 – Decoders, Multiplexers and Adders
8
Summary questions:
1.
What is the binary number decoded by the following decoder:
(a)
(b)
(c)
(d)
2.
010
101
011
100
What is the binary number decoded by the following decoder:
(a)
(b)
(c)
(d)
100
101
010
011
EB-3152 – Decoders, Multiplexers and Adders
9
3.
What is the binary number decoded by the following decoder:
(a)
(b)
(c)
(d)
101
010
011
100
EB-3152 – Decoders, Multiplexers and Adders
10
Experiment 2 – The Decoder
Objectives:
After completing this experiment explain:
 How to connect and to use an IC (Integrated Circuit) decoder.
Equipment Required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
2.1
Integrated logic components
In the preceding chapters we treated the materialization of digital functions by
basic logic components – the AND, OR, NOT, XOR, NAND and NOR gates.
In the early days of digital systems, only this method was used for
constructing digital systems. As technology advanced, the components
manufacturers started to produce packages, which include the materializations
of several various digital functions. The manufactured new logic devices, such
as decoders, demultiplexers, multiplexers, encoders, adders, counters and so
on. In the following chapters, we shall become familiar with these devices and
learn how to use them. These devices are called "Integrated Circuits", or in
short IC's.
From the technology point of view, there is hardly any limit to the number of
units, which we may "cram" into a package. Packages with hundreds of
thousands of gates are being produced, and this capability still increases every
year. When designing a component, the most sever design constraint is the
consideration of the number of pins of the package. Standard logic packages
come in 8, 14, 16, 18 and 20 pin packages. Packages with 24, 28, 40 and more
pins are also available. These are usually sophisticated devices and belong in
the microcomputers field.
EB-3152 – Decoders, Multiplexers and Adders
11
The selection of the size of the package to be used, dictates the number of
pins' hence the number of inputs and outputs of the component. Sometimes we
discover pins marked NC (i.e., No Connection) on some packages. This
denotes a pin that has no function. It is introduced in the packages in order to
preserve the uniformity of the packages.
Devices similar in their assigned overall functions but differing in the specific
performance of one or two pins are sometimes manufactures. The reason for
this is the inability to integrate all the required pin function in one package
(due to the limitation on the number of pins).
Among the pins of a package, two pins are usually assigned for connecting the
package to the power supply. One for the positive terminal of the power
supply, called VCC or VDD and the other to the negative terminal, the ground,
called GND or VSS. The power supply to all the gates in the package branches
out of these two terminals.
2.2
Binary and BCD decoders
In digital systems, we quite often need a circuit for decoding a certain binary
combination. Such a circuit is easily materialized by gates.
Example a:
A circuit whose output Y goes to '0' only when the combination 0101 appears
at its four inputs (A,B,C,D).
A
B
Y
C
D
Figure 2-1 A dedicated 0101 decoder
We may add an inverter at the output or use an AND gate, thus achieving a circuit whose
output Y rises to '1' when the combination 0101 appears at its four inputs.
EB-3152 – Decoders, Multiplexers and Adders
12
Example b:
A circuit with two inputs and four outputs is required. For each binary
combination of the inputs (from the four possibilities), another output shall be
activated (rise to '1').
Solution:
A
B
Y0
Y1
Y2
Y3
Figure 2-2 Gated decoder
Y0 shall rise to '1' when the combination 00 appears at inputs AB.
Y1 shall rise to '1' when the combination 01 appears at inputs AB.
Y2 shall rise to '1' when the combination 10 appears at inputs AB.
Y3 shall rise to '1' when the combination 11 appears at inputs AB.
This type of circuit happens to be a rather often required circuit, hence the
component manufactures are producing this circuit as an integrated logic
component. This circuit is called "a 1 of 4 decoder", and marked as in figure
2-3.
Y0
Y1
A
B
DECODER
Y2
Y3
Figure 2-3 2-4 line decoder
In general, NAND gates are used in decoders, hence the operative output pin
goes to '0'. The pins not being acted upon – remain at '1'.
EB-3152 – Decoders, Multiplexers and Adders
13
Instead of inserting one such circuit in a package, two such identical circuits
are packaged in a 16 pin package. 6 pins are needed for each circuit (two
inputs and four outputs) and of course two more pins for the power supply,
hence 14 pins are required in all. The other two pins serve as control pins.
The control pin is meant to block all outputs, regardless of the combination
existing at the inputs. Such a pin is justly called "Enable". It is usually
operated in the "Low" ('0') mode. When it goes "Low", one of the outputs is
activated. A very popular decoder with an enable (E') pin is the 74139,
described in the following figure.
A
B
E
A
B
E
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
Figure 2-4 74139 decoder
When pin E is at '1', none of the Y0-Y3 outputs is in operation. All are in
logic '1' state (the circle marked at each output informs us that this output is
operative under '0' and its non operating status is at '1'). When pin E is at '0'
(the enable state), the output whose driving combination appears at the inputs,
is activated.
EB-3152 – Decoders, Multiplexers and Adders
14
The enable pin allows the use of varied applications of decoders. For example,
we shall convert a package of dual 1 of 4 decoders into a single 1 of 8
decoder. For such a decoder we require 3 inputs.
A
B
A
B
C
E
Y0
Y1
Y2
Y3
Y0
Y1
Y2
Y3
A
B
E
Figure 2-5 3-8 decoder
When C = 0, one of the Y1-Y3 outputs of U1 shall be operated. The outputs of
U2 shall not be activated because E of U2 shall be at '1'.
When C = 1, one of outputs of U2 shall be operated, and the outputs of U1
shall not be activated. Thus, we have constructed a single 1 of 8 decoder
which includes three inputs and eight outputs. However, this kind of a circuit
does not include an enable pin.
There is a certain amount of waste in employing this method for materializing
a 1 of 8 decoder. A better solution is to use an existing, very popular
component, the 74138.
A
B
C
E1
E2
E3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Figure 2-6 The 74138 decoder
EB-3152 – Decoders, Multiplexers and Adders
15
This is also a 16 pin component. Check and observe where the changes have
been made. This component has three enable pins. One of the Y0-Y7 outputs
is activated (rises to '0'), in accordance with the combination appearing at
input pins A, B and C provided that all the enable pins actually are at the
Enable status. Thus, E1  E2  '0' and E3 = '1'.
Any other combination of the enable pins, causes all Y0-Y7 outputs to be at
the '1', regardless of the combination existing at the ABC input pins.
Incidentally, it is customary to mark the A pin as the LSB. Hence, the C pin
shall be the MSB.
We can neutralize the operation of the enable pin by connecting (short
circuiting) it to VCC or GND, depending on the function of the pin. For
example, if we want to cancel the effect of E3, we connect it to V CC, and if we
want to cancel the effect of E 2 , we connect it to GND or we connect it to E 1
(when E 1 is at '0' – E 2 will also be at '0' and vice versa).
A decoder possessing an Enable pin is also known as "Demultiplexer". The
enable pin is considered to be a data pin. The data is transmitted to one of the
outputs according to the number at the variables of the inputs. Actually, the
data being distributed can only be a '0'.
Another common decoder is the "BCD to Decimal" decoder. This decoder
possesses 4 inputs and 10 outputs.
A
B
C
D
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Figure 2-7 BCD to decimal decoder
EB-3152 – Decoders, Multiplexers and Adders
16
Each of the 10 outputs is activated in accordance with a different BCD
combination appearing at the inputs. If the combination differs from a BCD
number, i.e., it is a binary number in the 1010-1111 range, no output is
activated. The 7442 is an example of this kind of devices.
The package has 16 pins and because all of them are in use, this component
does not have an enable pin.
2.3
1 of n decoder
We have shown in the preceding paragraph how a dual 1 of 4 decoder
combination may be converted into a 1 of 8 decoder.
Let us proceed with the development of that idea. We shall now use two
74138's 1 of 8 decoders to construct a 1 of 16 decoder. The materialization is
rather simple and we do not require any additional component in addition to
these two components.
A
B
C
A
B
C
D
E1
E2
E3
A
B
C
E1
E2
E3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Figure 2-8 4-16 line decoder
The three enable lines allow the connection of additional lines intended to be
decoded.
EB-3152 – Decoders, Multiplexers and Adders
17
A need for a decoder providing a large number of decoded outputs, say 64
outputs, may sometimes arise. 64 combinations are received from 6 inputs
which are to be decoded (26). A convenient method for materializing such a
decoding system, using 9 decoders, is presented in the following figure.
EB-3152 – Decoders, Multiplexers and Adders
18
A
A
B
B
C
C
U2
8
E
U3
8
E
U4
8
E
D
U5
8
E
E
U1
U6
F
8
E
U7
8
E
E
U8
8
E
U9
E
Figure 2-9 64 outputs decoder
EB-3152 – Decoders, Multiplexers and Adders
8
19
The decoder U1, decodes the three MSB lines (D, E, F), and its outputs
activate all the other decoders U2 to U9, in accordance with the prevailing
combinations of D, E, F. The lines A, B, C are led to each one of the decoders.
One of the outputs of a decoder which have been activated according to the D,
E, F combinations shall be activated in accordance with the combination
residing at A, B, C.
The E1 line of U1 serves as the enable line of the entire decoding system.
Decoding by U1 is referred to as Primary Decoding and the decoding by U2U9 is referred to as Secondary Decoding.
2.4
The decoder as a decoder
We may sometimes need a 1-output decoder (for decoding just a single
combination of several inputs). We may, however, still prefer to use a multi
output decoder in the circuit.
For example, a 6-inputs decoder circuit is required whose output W is
activated ('0') when the binary combination 001101 appears at its inputs F, E,
D, C, B, A respectively. The regular materialization (with gates) shall be as
depicted by figure 2-10.
A
B
C
W
D
E
F
Figure 2-10 A 6-inputs decoder
Two packages are required for this "regular' materialization. One package
includes the NAND gate and the other package includes the inverters. The
package of the inverters is not fully used, we use only three out of the six
inverters in the package.
EB-3152 – Decoders, Multiplexers and Adders
20
No "off the shelf" NAND gate with 6 inputs is available. However, an 8-inputs
NAND gate is available (the 7430), hence we connect two of its inputs to VCC.
By using the 74138 decoder, the circuit may be materialized with a single
package.
A
B
C
F
E
D
A
B
C
E1
E2
E3
Y5
W
Figure 2-11 A 6-inputs decoder (single package solution)
Observe the method used in connecting the D, E, F inputs: we have connected
them to the enable inputs, so that only their required combination (001) shall
activate the decoder. The output W is obtained from the Y5 output of the
decoder, because this output is only activated when the required combination
of C, B, and A (namely 101) is obtained.
This decoding method enables an easy change over of the decoder for
performing a different decoding than the one of original arrangement.
Consider for example that we have to change the 001 101 combination into
the 001 110 combination. The only required operation is to connect the W
output to the Y6 decoder output (instead of the Y5 previously connected).
2.5
Primary and secondary decoding
In order to decode a large number of lines, two decoders connected in series
(one after the other) are used. One of them decodes what we call "Primary
Decoding" and the other performs "Secondary Decoding".
For example, consider the requirement of a decoding circuit with 11 inputs
(A0-A10), whose output W = 0 when the following combination prevails in
the inputs.
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0
1 0 0 0 1 0 1 0 1 1
EB-3152 – Decoders, Multiplexers and Adders
21
We divide the input into two groups: A0-A4 and A5-A10. Using two 74138
units, the materialization shall be as depicted by figure 2-12.
A0
A1
A2
A3
A
B
C
E1
E2
E3
A4
A5
A6
A7
A8
A9
A10
A
B
C
E1
E2
E3
Y3
W
Y1
Figure 2-12 Series decoders
In this application of decoders, as in the preceding example, the required
combination may be changed with ease, by changing the lines connected to
the outputs of the decoders.
EB-3152 – Decoders, Multiplexers and Adders
22
2.6
BCD to decimal as a 1 of 8 decoder
Even through the BCD to decimal components does not include an enable pin,
it can be used as a 1 of 8 decoder with an enable pin. The D pin serves as the
enable pin.
A
B
A
B
C
E
C
D
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Figure 2-13 BCD to decimal as a 2-8 line decoder
When the input D is in '0', one of the Y0-Y7 output pins shall be activated,
according to the combination established at the inputs A, B, C. When the input
D goes to '1', none of the Y0-Y7 output pins shall be operating, but Y8 or Y9
shall be activated, or no output whatsoever shall be activated.
A 1 of 4 decoder is described in the following way:
Y3
A
B
DECODER
Y2
Y1
Y0
Figure 2-14
Usually we use NAND gates to materialize the decoder, which make sure that
the chosen output drops to '0' and all the others are in '1'.
Because the decoder occupies only 6 pin, we put 2 such decoders in 16 pin
package in the circuit. Two pins are for supplying voltage to the component
and the other two pins are control pin as described in the next page.
EB-3152 – Decoders, Multiplexers and Adders
23
The control pins block all the outputs regardless the combination in the inputs.
This pin is called Enable pin. Usually, the enabling exists when this pin is in
'0'. A popular component such as this is the 74139, included in the TPS-3351
trainer. The Enable pin is marked with the letter G. The circle next to it
indicates that the Enabling exists when its in '0'.
U1A
2
A
Y0
4
3
B
1
G
Y1
Y2
Y3
5
6
7
U1B
14
A
Y0
12
13
B
15
G
Y1
Y2
Y3
11
10
9
Figure 2-15
A
The Enable pin allows us to execute other applications in the component. For
example, turning it to a 1 of 8 decoder, as described in the following figure:
U1
A
B
C
2
3
1
A
Y0
4
B
Y1
Y2
Y3
5
6
7
A
Y0
12
B
Y1
Y2
Y3
11
10
9
G
U2
14
13
15
G
Figure 2-16
When C = 0, one of the Y0-Y3 outputs of U1 is activated. The U2 outputs are
not activated because the G pin of U2 is in '1'.
EB-3152 – Decoders, Multiplexers and Adders
24
When C = 1, one of the Y0-Y3 outputs of U2 is activated. The U1 outputs are
not activated because the G pin of U1 is in '1'. This 1 of 8 decoder does not
include an Enable pin.
There are other ways to materialize a 1 of 8 decoder, but the best solution is to
use the popular decoder 74138, described in the following figure:
1
A
Y0
15
2
3
B
C
Y1
Y2
Y3
Y4
14
13
12
11
G1
Y5
Y6
Y7
10
9
7
6
4
5
G2A
G2B
Figure 2-17
This decoder comes in a 16 pin package. It includes 3 choice inputs and 3
Enable pin. For one of the Y0-Y7 output to be activated, the Enable pins must
fulfill the next condition: G2A=G2B=0 and G1=1. The activated output
according to the combination at the A, B, and C inputs drops to '0' and all the
others are in '1'.
C is the MSB and A is the LSB. We can short-circuit the Enable pins
permanently to GND or VCC, to cancel their influence.
EB-3152 – Decoders, Multiplexers and Adders
25
Preparation questions:
1.
At what combination of inputs A, B and C, Y2 is '0'?
U1
(a)
(b)
(c)
(d)
2.
A
Y0
B
B
C
G
Y1
Y2
Y3
110
011
010
101
At what combination, two or more of the outputs are '0'?
(a)
(b)
(c)
(d)
3.
A
When G is '0'.
When G is '1'.
Never
111
At what combination, two or more of the outputs are '1'?
(a)
(b)
(c)
(d)
When G is '0'.
When G is '1'.
Never
111
EB-3152 – Decoders, Multiplexers and Adders
26
4.
At what combination of inputs A, B and C, Y2 (of U2) is '0'?
U1
A
A
Y0
B
B
C
G
Y1
Y2
Y3
U2
A
Y0
B
Y1
Y2
Y3
G
(a)
(b)
(c)
(d)
110
011
010
101
EB-3152 – Decoders, Multiplexers and Adders
27
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Connect the four outputs Y3,Y2,Y1,Y0 of decoder 1 to the four
LED's L3,L2,L1,L0 accordingly.
U1
A
A
Y0
B
B
C
G
Y1
Y2
Y3
Step 7:
Connect the B,A inputs of the decoder to the switches S1,S0
accordingly.
Step 8:
Connect the enable input G to the switch S3.
Step 9:
Lower switch S3 (G) to state '0'.
EB-3152 – Decoders, Multiplexers and Adders
28
Step 10: Change the states of the switches S0 and S1 and fill in the following
table.
G B A O3 O2 O1 O0
S3 S1 S0 L3 L2 L1 L0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Step 11: Raise switch S3 (G) to '1'.
Step 12: Change switches S1,S0 and continue filling in the table for the
various states of switches S0 and S1.
Step 13: The trainer includes to 1 of 4 decoders. Materialize with those two
decoders a 1 of 8 decoder as described in the following figure.
U1
A
A
Y0
B
B
C
G
Y1
Y2
Y3
U2
A
Y0
B
Y1
Y2
Y3
G
Step 14: Connect the 3 inputs C,B,A to switches S0,S1,S2.
Step 15: Use the LED L0 for checking the status of the outputs Y0-Y7 at
each state.
EB-3152 – Decoders, Multiplexers and Adders
29
Step 16: Change the switches S2,S1,S0 (C,B,A) and fill up the following
table:
C B A
DEC B
DEC A
S2 S1 S0 Y3 Y2 Y1 Y0 Y3 Y2 Y1 Y0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
EB-3152 – Decoders, Multiplexers and Adders
30
Summary questions:
1.
At what combination of inputs A, B and C, Y2 is '0'?
U1
(a)
(b)
(c)
(d)
2.
A
Y0
B
B
C
G
Y1
Y2
Y3
110
011
010
101
At what combination, two or more of the outputs are '0'?
(a)
(b)
(c)
(d)
3.
A
When G is '0'.
When G is '1'.
Never
111
At what combination, two or more of the outputs are '1'?
(a)
(b)
(c)
(d)
When G is '0'.
When G is '1'.
Never
111
EB-3152 – Decoders, Multiplexers and Adders
31
4.
At what combination of inputs A, B and C, Y2 (of U2) is '0'?
U1
A
A
Y0
B
B
C
G
Y1
Y2
Y3
U2
A
Y0
B
Y1
Y2
Y3
G
(a)
(b)
(c)
(d)
110
011
010
101
EB-3152 – Decoders, Multiplexers and Adders
32
Experiment 3 – Using a Decoder to Materialize
a Function
Objectives:
After completing this experiment explain:
 How to materialize a function using a decoder and gates.
 How to materialize a function using a decoder with the WIRE-OR method.
Equipment Required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
A decoder may serve as a tool for materializing functions, in particular in
those cases when the function cannot be simplified. For our experiment, we
will materialize the function:
Z   (0,5,6)  C BA  CBA  CBA
The Karnaugh map of this function is shown in figure 3-1.
AB
C
0
0
00 00 00 00
1 0 1 0
0 0 0 1
Figure 3-1 Z Karnaugh map
EB-3152 – Decoders, Multiplexers and Adders
33
Materializing this function with gates requires a large number of gates and
IC's. The implementation of this function using the 74138 decoder, will be
simpler.
1
A
Y0
15
2
3
B
C
Y1
Y2
Y3
Y4
14
13
12
11
Y5
Y6
Y7
10
9
7
Z
Figure 3-2 Decoder implementation of Z
Z will be '1' when one of the combinations 000(0), 101(5) or 110(6) appears at
the corresponding inputs C,B,A. For any other combination, Z shall equal '0'.
WIRE-OR:
Sometimes we may reduce the number of gates required by employing the so
called WIRE-OR method of materialization. In other words, we are talking of
an OR operation accomplished solely by suitable wiring of outputs.
Another concept associated with this method of materialization is the "open
collector" device. These concepts are explained below.
Each logic component includes an output stage. This stage activates the
component, which is connected to the output of the logic component. At logic
'1', the output stage pushes current towards the external component, and at
logic '0', the output stage draws (sinks) current from this component.
EB-3152 – Decoders, Multiplexers and Adders
34
In general, it is prohibited to connect two outputs of different logic
components together. Consider the arrangement in figure 3-3.
Figure 3-3 A prohibited connection – example
The outputs of the OR and the AND gates are both connected to the input of
the following inverter gate. The following state of affairs is forbidden: assume
that a '1' prevails at the output of one of the gates (say the OR GATE) and a '0'
appears on the other (the AND, in this example). Thus, the OR gate shall feed
current to the AND gate and the current consumption from the power supply
will be high. More important, the data at the input of the inverter will be
ambiguous.
In order to enable two such outputs to be directly connected, as well as to
allow additional applications, special logic components have been introduced.
The output stage of these components is made of a transistor with an open
collector arrangement, as in the following figure.
Output Q
Inputs
The Logic Part
Figure 3-4 Open collector logic device
Such a device cannot "push" (feed) current, only draw it. When the logic state
at the output is '0', the transistor operates as a closed switch and its output Q is
virtually short circuited to ground. When the logic state at the output is '1', the
transistor operates as an open switch and the output is actually cut-off. In
order to apply a voltage to the output for the logic '1' condition, we have to
connect a resistor between the output Q and VCC.
EB-3152 – Decoders, Multiplexers and Adders
35
Assume that we have two logic components with an open collector output
stage. The two output stages may be interconnected as follows:
VCC
R
QA
Q
Component A
QB
Component B
Figure 3-5 Connecting two open collector output stages
If QA or QB or both are at '0', the line Q will also be at '0'. The current will
flow from VCC through resistor R to the closed transistor. However, a situation
in which one logic device sends current to the other logic device can never
occur. A logic component whose output is at '1" is actually cut-off and does
not interfere with the other logic device. Only when the two outputs (QA and
QB) are both at logic '1", namely, when both transistors are cut-off, the
resistor shall pull the Q line to VCC and Q will also be at logic '1'. This is the
reason for naming this method "WIRE-OR" (two open collector outputs wired
together).
EB-3152 – Decoders, Multiplexers and Adders
36
Let us form a relation between this method and the decoding circuit. We shall
materialize the Karnaugh map depicted by figure 2-14 with the help of a
decoder whose outputs are open collector outputs. We shall use the 74145
device, which is a 1 of 10 BCD-to-decimal decoder. Let us perform a WIREOR of the combinations producing the Zero's of the map. We obtain the
materialization of figure 3-4.
VCC
A
B
C
15
14
13
12
Y0
1
Y1
Y2
Y3
Y4
2
3
4
5
Y5
Y6
Y7
Y8
Y9
6
7
9
10
11
R
Z
Figure 3-4 WIRE-OR decoder function materialization
D is grounded (always '0'), so Y8 and Y9 will always be '1'.
Z drops to '0' when Y1,Y2,Y3,Y4 and Y7 drop to '0'. For all the other
combinations of C,B,A, which are 000(0),101(5) and 110(6), Z will be '1'.
Thus we have managed to obtain the materialization of the function Z =
(0,5,6) by using only a single device.
EB-3152 – Decoders, Multiplexers and Adders
37
Preparation questions:
1.
What is the function of the following circuit?
A
B
A
B
C
G
A
B
G
(a)
(b)
(c)
(d)
2.
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Z   ( 0 , 5 ,6 )
Z   (1,5,6)
Z   (0,2,3,4,7)
Z   (5,6)
Why we use a NAND gate and not an OR gate?
(a)
(b)
(c)
(d)
Because it is cheaper.
Because we do not have an OR gate with 3 inputs.
Because the state of the decoded output Y is '0'.
Because the state of the decoded output Y is '1'.
EB-3152 – Decoders, Multiplexers and Adders
Z
38
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Materialize the circuit described in figure 3-2 with two 1 of 4
decoders (located in the trainer) as follows:
A
B
A
B
C
G
A
B
G
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Z
Step 7:
Connect the circuit C,B,A inputs to the switches S2,S1,S0
accordingly.
Step 8:
Connect the NAND gate output to the LED L0.
EB-3152 – Decoders, Multiplexers and Adders
39
Step 9:
Change the switches S2,S1,S0 and fill in the following table:
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A Z
0
1
0
1
0
1
0
1
Step 10: Check that this table suits the function Z = (1,5,6).
EB-3152 – Decoders, Multiplexers and Adders
40
Summary questions:
1.
What is the function of the following circuit?
A
B
A
B
C
G
A
B
G
(a)
(b)
(c)
(d)
2.
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Z
Z   ( 0 , 5 ,6 )
Z   (1,5,6)
Z   (0,2,3,4,7)
Z   (5,6)
What will happen to output Z if we replace the NAND gate with an OR
gate?
(a)
(b)
(c)
(d)
Output Z will always be '1'.
Output Z will always be '0'.
Z   (0,2,3,4,7)
Z  (1,5,6)
EB-3152 – Decoders, Multiplexers and Adders
41
Experiment 4 – Multiplexer Applied as a
Multiplexer
Objectives:
After completing this experiment explain:
 The multiplexer's functions and its operation.
Equipment Required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
4.1
A 1 of n mulitplexer
When we use the term multiplexer, we are referring to a device, which
receives data arriving from several channels, and outputs it through a single
channel. Consider for example the 1 of 4 multiplexer depicted by figure 4-1.
I0
I1
Z
I2
I3
S1
S0
Figure 4-1 1 of 4 multiplexer
EB-3152 – Decoders, Multiplexers and Adders
42
The component has two select pins, S0 and S1. The data from one of the input
channels, according to the number assigned by the select pins S0 and S1,
appears at the output. The following table describes the relationship between
the number on the select pins and the chosen input channel.
S1 S0 Z
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Data arriving at the inputs of the multiplexer from the outputs of various logic
circuits can be transferred through the multiplexer, to another device or to
other logic circuits.
In this manner a selected output (Z) may be operated by different logic
functions, by using the select pins (S0,S1).
Usually, an enable pin is also available in practical multiplexer components.
This pin serves to block the data from the inputs to the output Z.
The 74153 component, for example (figure 4-2) contains two 1 of 4
multiplexers with common S0,S1 inputs.
S1
S0
Ea
I1a
I1a
Za
I2a
I3a
I0b
I1b
I2b
I3b
Zb
Figure 4-2 The 74153 multiplexer
EB-3152 – Decoders, Multiplexers and Adders
Eb
43
The table of states of the 74153 multiplexer is as given by the following table:
S1 S0 E
x x 1
0 0 0
0 0 0
0 1 0
0 1 0
1 0 0
1 0 0
1 1 0
1 1 0
I0
x
0
1
x
x
x
x
x
x
I1
x
x
x
0
1
x
x
x
x
I2
x
x
x
x
x
0
1
x
x
I3
x
x
x
x
x
x
x
0
1
Z
0
0
1
0
1
0
1
0
1
From the table we learn that the state with '0' at the output is the state at which
the data arriving from the selected channel is '0', or when all the inputs are cut
off (E = '1'). For this reason it is preferable to refer first to the output and to
check whether it is operating ('1' state) or not. When the output is in operation,
it is uniquely clear that the selected input has been activated and that E = '0'.
Some multiplexers already include and inverting output, as is the case for the
74151 component (this is a 1 of 8 multiplexer).
S2
S0
S0
E
I0
I1
I2
I3
Z
I4
I5
I6
I7
Z
Figure 4-3 74151 multiplexer
Z will be at level '1' if the input, whose combination appears at the S0-S2
select pins, shall be in logic '1'. If the aforesaid input is at '0' or if E = '1', than
the output Z shall be in '0'. Z is the inverse of Z.
1 of 2 multiplexers with a common (single) select line are also commercially
available. There are four multiplexers in the package of such a device, each
one of them possessing two inputs and one output.
EB-3152 – Decoders, Multiplexers and Adders
44
It has been indicated in the previous paragraphs that outputs of logic circuits
may be connected to a multiplexer, and with the aid of the multiplexer it is
possible to transfer the data of these outputs onto a single line.
Consider for example the circuit of figure 4-4.
A
B
I0
I1
Z
I2
Z
I3
E
S1
S0
S1
S0
Figure 4-4 Multiplexer connection
The dependence of the output Z on the inputs A and B for the circuit in figure
6-4 is as given in the following table.
S1 S0
Z
0 0 Z = A.B
0 1 Z = A+B
1 0 ZAB
1 1 Z  A.B
The circuit shown is a general circuit, illustrating the principle for
implementing a multiplexer. This is not necessarily the simplest feasible
materialization for this specific problem.
EB-3152 – Decoders, Multiplexers and Adders
45
Preparation questions:
1.
What is the function of the following circuit when S1,S0 = 00?
A
I0
B
I1
I2
Z
I3
Z
E
S1
S0
S1
S0
(a)
(b)
(c)
(d)
2.
What is the function of the above circuit when Z1,Z0 = 01?
(a)
(b)
(c)
(d)
3.
B
A
AB
AB
B
A
AB
AB
What is the function of the above circuit when Z1,Z0 = 01?
(a)
(b)
(c)
(d)
B
A
AB
AB
EB-3152 – Decoders, Multiplexers and Adders
46
4.
What is the function of the above circuit when Z1,Z0 = 01?
(a)
(b)
(c)
(d)
B
A
AB
AB
EB-3152 – Decoders, Multiplexers and Adders
47
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Use the multiplexer and gates to materialize the following circuit.
A
I0
B
I1
I2
Z
I3
Z
E
S1
S0
S1
S0
Step 7:
Connect the output Z of the multiplexer to the LED L0.
Step 8:
Connect S1,S0 inputs of the multiplexer to the switches S1,S0
accordingly.
Step 9:
Connect the B,A inputs of the circuit to the switches S3,S2
accordingly.
EB-3152 – Decoders, Multiplexers and Adders
48
Step 10: Change the states of the switches and fill in the following table.
S1,S0=0,0 S1,S0=0,1 S1,S0=1,0 S1,S0=1,1
B A Z B A Z B A Z B A Z
S3 S2 L0 S3 S2 L0 S3 S2 L0 S3 S2 L0
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
Step 11: Check which function is represented by each table (write this below
each table).
EB-3152 – Decoders, Multiplexers and Adders
49
Summary questions:
1.
What is the function of the following circuit when S1,S0 = 00?
A
I0
B
I1
I2
Z
I3
Z
E
S1
S0
S1
S0
(a)
(b)
(c)
(d)
2.
What is the function of the above circuit when Z1,Z0 = 01?
(a)
(b)
(c)
(d)
3.
B
A
AB
AB
B
A
AB
AB
What is the function of the above circuit when Z1,Z0 = 01?
(a)
(b)
(c)
(d)
B
A
AB
AB
EB-3152 – Decoders, Multiplexers and Adders
50
4.
What is the function of the above circuit when Z1,Z0 = 01?
(a)
(b)
(c)
(d)
B
A
AB
AB
EB-3152 – Decoders, Multiplexers and Adders
51
Experiment 5 – Using a Multiplexer to
Materialize Functions
Objectives:
After completing this experiment explain:
 How to use a multiplexer to materialize a function.
Equipment Required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
One application of the multiplexer is its use for materializing Boolean
functions. Consider for example the function:
Z  A.B.C  A.B.C  A.B.C  A.B.C  (0,2,4,5)
EB-3152 – Decoders, Multiplexers and Adders
52
Let us materialize this function by using the 74151 multiplexer, in the manner
shown in figure 5-1.
4
D0
3
D1
2
D2
1
15
14
13
12
A
B
C
11
10
9
7
Z
Z
6
5
Z
Z
D3
D4
D5
D6
D7
A
B
C
G
Figure 5-1 Materializing the function using a multiplexer
Note that the inputs whose respective combinations of the function produce '1'
are connected to VCC and all other inputs are connected to GND. In this
manner, we obtain with ease a convenient materialization of the function.
There is no need to simplify the function by working out a Karnaugh map.
Rather, we need only to relate to the table of states. An added advantage: this
materialization system can be adapted to change its function with ease.
An n-variables function may be materialized by employing a multiplexer
having 1 of n SELECT inputs. Let us materialize the function presented in the
former example (three variables) by using a multiplexer having two Select
inputs.
EB-3152 – Decoders, Multiplexers and Adders
53
The table of states of the function is presented below:
C
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
Z
1
0
1
0
1
1
0
0
We split the table into two tables, C=0 in one and C=1 in the other.
C
0
0
0
0
B
0
0
1
1
A
0
1
0
1
Z
1
0
1
0
C
1
1
1
1
B
0
0
1
1
A
0
1
0
1
Z
1
1
0
0
Scrutinizing the tables, we discover that:
Z=1
Z=C
Z= C
Z=0
in both tables, when B,A=00
in both tables, when B,A=01
in both tables, when B,A=10
in both tables, when B,A=11
Hence, we can write the following table of states:
B
0
0
1
1
A
0
1
0
1
Z
1
C
C
0
EB-3152 – Decoders, Multiplexers and Adders
54
Figure 5-2 depicts how the materialization of this solution is affected using a
multiplexer.
C
I0
I1
Z
I2
I3
S1
S0
B
A
Figure 5-2 Materializing the resulting function using a multiplexer
In a similar manner, we can materialize a 4-variables function by employing a
three Select inputs multiplexer.
EB-3152 – Decoders, Multiplexers and Adders
55
Preparation questions:
1.
What is the function materialized by the following circuit?
I0
I1
C
Z
I2
I3
S1
S0
B
A
(a)
(b)
(c)
(d)
2.
Z   (1,3,6,7)
Z   (1,2,3,4)
Z   (0,2,4,5)
Z   (0,2,4,6)
At state B,A = 1,0, what will be the function of Z?
(a)
(b)
(c)
(d)
Z=1
Z=0
Z=C
ZC
EB-3152 – Decoders, Multiplexers and Adders
56
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Use the multiplexer and an inverter gate to materialize a function as
described in the following figure.
C
I0
I1
Z
I2
I3
S1
S0
B
A
Step 7:
Connect the output Z of the multiplexer to the LED L0.
Step 8:
Connect S1,S0 inputs of the multiplexer to the switches S1,S0
accordingly.
Step 9:
Connect the C input of the circuit to the switch S2. S2,S1,S0 will act
as the equation variables C,B,A accordingly.
EB-3152 – Decoders, Multiplexers and Adders
57
Step 10: Change the states of switches S2,S1,S0 and fill in the following
table.
C B A Z
S2 S1 S0 L0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Step 11: Check that this table suits the truth table of the function
Z = (0,2,4,5) as described in the discussion section.
EB-3152 – Decoders, Multiplexers and Adders
58
Summary questions:
1.
What is the function materialized by the following circuit?
I0
I1
C
Z
I2
I3
S1
S0
B
A
(a)
(b)
(c)
(d)
2.
Z   (1,3,6,7)
Z   (1,2,3,4)
Z   (0,2,4,5)
Z   (0,2,4,6)
At state B,A = 1,0, what will be the function of Z?
(a)
(b)
(c)
(d)
Z=1
Z=0
Z=C
ZC
EB-3152 – Decoders, Multiplexers and Adders
59
Experiment 6 – Binary Addition
Objectives:
After completing this experiment explain:
 The structure of a half adder and full adder.
 How to use a full adder for binary addition.
Equipment Required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
6.1
Binary addition
A prerequisite for addition in the decimal system is to know the addition table
of the various digits. This applies to the binary system too, only in the binary
system we have only 2 digits. The addition table for the binary system looks
as follows:
0+0=0
0+1=1
1+0=1
1 + 1 = 10
The adding together of two binary numbers is done in a similar fashion to that
of two decimal numbers, which is by adding two digits together at a time, the
outcome's digit of the same order is written down below the line and the carry
digit is written above the next order's digit.
Example:
18610 =
1011 10102
+ 5110 = + 0011 00112
23710 =
1110 11012
EB-3152 – Decoders, Multiplexers and Adders
60
A Half Adder (HA) is a logic component, which adds two binary bits. The
binary addition of two bits is performed in accordance with the following
table.
A B C Y
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
The half adder has two outputs. The Y output contains the result, and the
second output, C, indicates the carry. A carry is generated when both bits
being added are '1', producing "10" (2) as the result.
A half adder (HA) is symbolized in figure 6-1.
B
A
H
A
C
Y
Figure 6-1 The Half Adder symbol
In order to materialize the HA we have to split its table of states into two truth
tables, presented below.
B
0
0
1
1
A
0
1
0
1
Y
0
1
1
0
A
0
0
1
1
B
0
1
0
1
C
0
0
0
1
EB-3152 – Decoders, Multiplexers and Adders
61
Note that the table of states of the Y output is the state table of a XOR gate
and the table of states of the C output is the state table of an AND gate. Hence,
the materialization is implemented by the arrangement in figure 6-2.
BA
C
Y
Figure 6-2 Materialization of the Half Adder
A half adder is only serviceable for adding one pair of bits at a time. When we
are adding binary numbers, we add each pair of bits (one from each number to
be added) with the carry, which has been received from adding the former pair
of bits. The HA is unsuitable for this task. The unit that does perform this kind
of addition is called a Full Adder (FA). This device has three inputs and two
outputs. The table of its states is presented below.
C0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
A C+
0 0
1 0
0 0
1 1
0 0
1 1
0 1
1 1
Y
0
1
1
0
1
0
0
1
EB-3152 – Decoders, Multiplexers and Adders
62
Its Karnough map of Y is as follows:
AB
C-
0
0
00 01 11 10
0 1 0 1
1 0 1 0
Figure 6-3 Full Adder – Karnaugh map of Y
There are no "neighboring squares".
The function which shall be obtained is the following normal function:
Y  C  .B .A  C  .B.A  C  .B .A  C  .B.A
But this function is also equal to the following function:
Y  C  B  A
And the materialization may be accomplished in one of the two forms
depicted by figure 6-4.
CCB
A
Y
B
A
Y
Figure 6-4 Full Adder – materializations of function Y
EB-3152 – Decoders, Multiplexers and Adders
63
The Karnaugh map of function C+ is depicted by figure 6-5.
AB
C-
00 01 11 10
0
0
0
1
0
0
0
1
1
1
Figure 6-5 Full Adder – Karnough map of C+
The following normal function is obtained:
C+ = A.B+C-.A+C-.B
Which is equal to:
C+ = A.B+C-.(A+B)
And its materialization is depicted by figure 6-6.
CB
A
C+
Figure 6-6 Full Adder – materialization of function C+
EB-3152 – Decoders, Multiplexers and Adders
64
Figure 6-7 presents the symbol for a FA cell.
B
A
F
A
C+
Y
C-
Figure 6-7 The Full Adder symbol
In figure 6-8 we show how an adder for adding four bit binary numbers may
be materialized.
b3 a3
b
a
b2 a2
c-
b
FA
c+
a
c-
b
FA
c+
Y4 Y3
b1 a1
a
c-
b
FA
c+
Y2
b0 a0
a
c-
FA
c+
Y1
Y0
Figure 6-8 Materializing a 4-bit binary numbers adder
The FA at the extreme right adds the two LSB's of the two binary numbers, A0 and B0.
The following FA (second from the right) adds the two bits A1 and B1 and the
carry brought over from the preceding addition, and so on. The results shall be
obtained at the Y0,Y1,Y2 and Y3 bits. The last C+, is actually a fifth bit, the
carry bit.
EB-3152 – Decoders, Multiplexers and Adders
65
An off the shelf component which is exactly such an adding unit, is readily
available. This is the 7483 IC component described in figure 6-9.
b3 a3 b2 a2 b1 a1 b0 a0
c4
c0
y3
y2
y1
y0
Figure 6-9 The 7483 adder
C0 is actually the C- of the first FA, which adds A0 with B0, and Y0 is its
output. C4 is C+ of the last FA, which add A3 with B3, and Y3 is its output.
C0 and C4 are used when we wish to connect several such units in cascade, in
order to handle (add) large binary numbers.
Figure 6-10 describes how to assemble an adder capable of adding two 8-bit
binary numbers.
b7 a7 b6 a6 b5 a5 b4 a4
1
b3 a3 b2 a2 b1 a1 b0 a0
1
b3 a3 b2 a2 b1 a1 b0 a0
b3 a3 b2 a2 b1 a1 b0 a0
c4
c0
c4
c0
y3
y2
y1
y0
y3
y2
y1
y0
y7
y6
y5
y4
y3
y2
y1
y0
CY
Figure 6-10 An adder for two 8-bit binary numbers
EB-3152 – Decoders, Multiplexers and Adders
66
Preparation questions:
1.
What is the result of 0110 + 0110?
(a)
(b)
(c)
(d)
2.
What is the result of 1111 + 1111?
(a)
(b)
(c)
(d)
3.
1100
0100
1010
1101
01110
10000
11110
10101
What is the result of 1111 + 0001?
(a)
(b)
(c)
(d)
01110
10000
11110
10101
EB-3152 – Decoders, Multiplexers and Adders
67
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Connect the four switches S0-S3 to the A0-A3 inputs of the adder.
Step 7:
Connect the four switches S7-S4 to the B3-B0 inputs of the adder in
the trainer.
b3 a3 b2 a2 b1 a1 b0 a0
+5V
b3 a3 b2 a2 b1 a1 b0 a0
c4
c0
y3
y2
y1
y0
y3
y2
y1
y0
+C
Step 8:
Connect the C0 input to the output of a NOT gate. This will act as a
ground.
Step 9:
Connect the four outputs Y3-Y0 to the LEDs L0-L3.
Step 10: Connect the C4 output to LED L4.
EB-3152 – Decoders, Multiplexers and Adders
68
Step 11: Change the state of the input switches and check that the binary sum
of the two numbers being added is obtained at the LEDs.
Write down three examples in your notebook.
Step 12: Check the results of the preparation questions.
EB-3152 – Decoders, Multiplexers and Adders
69
Summary questions:
1.
What is the result of 0110 + 0110?
(a)
(b)
(c)
(d)
2.
What is the result of 1111 + 1111?
(a)
(b)
(c)
(d)
3.
1100
0100
1010
1101
01110
10000
11110
10101
What is the result of 1111 + 0001?
(a)
(b)
(c)
(d)
01110
10000
11110
10101
EB-3152 – Decoders, Multiplexers and Adders
70
Experiment 7 – Binary Subtraction
Objectives:
After completing this experiment explain:
 The 2's complement method.
 How to use an adder for subtracting.
Equipment Required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
Instead of performing subtraction, we can define negative numbers in the
same manner as is done in the decimal numbers system, and then perform
addition.
Study the following example:
15-6 = 15+(-6) = 9
Because signs cannot be designated, the MSB (Most Significant Bit) is used to
indicate the sign. Zero (0) indicates plus and one (1) indicates minus. The
remaining bits are the number.
One may think, that in order to convert the positive number into a negative
one, it would be sufficient to change the sign (bit) from '0' to '1'.
Let us try it. For example:
+5 = 0000 0101
–5 = 1000 0101
EB-3152 – Decoders, Multiplexers and Adders
71
Let us see what happens when the two numbers are added:
+ 0000 0101
1000 0101
1000 1010 = –10
–10 is of course a wrong answer. Hence, another method has to be developed
for performing the subtraction operation.
The 2's complement method is widely accepted. The number complementing
to two is the 1's complement value plus 1. The 2's complement is defined as a
negative number.
The 1's complement (the number complementing a given number to one) of a
binary number is the number obtained after every zero was substituted by 1
and every 1 was substituted by zero.
Example:
+29 = 0001 1101
The 1's complement of
plus 1
gives the 2's complement of
+29 = 1110 0010
+
1
–29 = 1110 0011
Now we can check if we do get zero by adding +29 and –29 (binary).
0001 1101 = +29
1110 0011 = –29
carry [1] 0000 0000
The carry is disregarded in this method of subtraction.
EB-3152 – Decoders, Multiplexers and Adders
72
Examples:
a)
15-9 = +6
0000
1111
2's comp. +9 = 1111
of
0111
[1] = 0000
0110
b)
= +15
= –9
0000
1001
1's comp. +9 = 1111
of
0110
= +9
0000
1111
1's comp. +15 = 1111
of
0000
= +15
= +6
9 –15 = –6
0000
1001
2's comp. +15 = 1111
of
0001
[0] = 1111
1010
= +9
= –15
= –6
Let us verify that the result equals (–6):
00000110 = +6
1's complement = 11111001
+
1
11111010 = –6
We have shown that binary subtraction may be performed by adding the 2's
complement of the subtrahend (the number to be subtracted) from the
minuend (the number we have to subtract from). We have also introduced the
2's complement, which is the 1's complement of that number plus 1. We shall
now perform the subtraction operation by adding the 1's complement of the
subtrahend to the number from which we have to subtract and establishing '1'
at C0. In this manner, we add the 1's complement to the minuend plus 1.
EB-3152 – Decoders, Multiplexers and Adders
73
For an example, see the following figure 7-1.
b3 a3 b2 a2 b1 a1 b0 a0
+5V
b3 a3 b2 a2 b1 a1 b0 a0
c4
c0
y3
y2
y1
y0
y3
y2
y1
y0
+C
Figure 7-1 Subtracting a 4-bit binary number
EB-3152 – Decoders, Multiplexers and Adders
74
Preparation questions:
1.
What is the result of 0110 – 0011?
(a)
(b)
(c)
(d)
2.
What is the result of 0000 – 1111?
(a)
(b)
(c)
(d)
3.
0011
0100
0001
0010
10000
10001
11110
01111
What is the 1's complement of 0110?
(a)
(b)
(c)
(d)
0101
1110
1001
1010
EB-3152 – Decoders, Multiplexers and Adders
75
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Interconnect the full adder and four inverters as described in the
following figure (you can also use NAND or NOR gates as inverter
by short circuiting their inputs).
b3 a3 b2 a2 b1 a1 b0 a0
+5V
b3 a3 b2 a2 b1 a1 b0 a0
c4
c0
y3
y2
y1
y0
y3
y2
y1
y0
+C
Connect C0 input to VCC.
Step 7:
Connect the switches S3-S0 to the A3-A0 inputs of the minuend.
Step 8:
Connect the switches S7-S4 to the B3-B0 inputs of the subtrahend.
Connect the switches to the inverter inputs.
Step 9:
Connect the full adder's four outputs Y4-Y0 and the CY output to
the LEDs.
EB-3152 – Decoders, Multiplexers and Adders
76
Step 10: Change the state of the input switches and check that the binary
difference between the two numbers is obtained at the LEDs.
Write down three examples in your notebook, including an example
where the subtrahend is larger than the minuend.
Step 11: check the results of the preparation questions.
EB-3152 – Decoders, Multiplexers and Adders
77
Summary questions:
1.
What is the result of 0110 – 0011?
(a)
(b)
(c)
(d)
2.
What is the result of 0000 – 1111?
(a)
(b)
(c)
(d)
3.
0011
0100
0001
0010
10000
10001
11110
01111
What is the 1's complement of 0110?
(a)
(b)
(c)
(d)
0101
1110
1001
1010
EB-3152 – Decoders, Multiplexers and Adders
78
Experiment 8 – Binary Comparison
Objectives:
After completing this experiment explain:
 How to materialize a binary numbers comparator circuit.
Equipment Required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
Using a XOR gate can perform an operation comparing two binary numbers.
For example, with a circuit whose output goes to '1' when its two inputs are
equal, as shown in figure 8-1.
A
B
Y
Figure 8-1 2-bit comparator circuit
The table of states of this circuit is as follows:
B
0
0
1
1
A
0
1
0
1
Y
1
0
0
1
EB-3152 – Decoders, Multiplexers and Adders
79
Two binary numbers may be compared by the circuit proposed in figure 8-2.
A0
B0
A1
B1
Y
A2
B2
A3
B3
Figure 8-2 2 binary numbers comparator circuit
Y shall equal '1' when the input bits of all pairs are identical. Once an
inequality develops in one (or more) of the pairs, Y goes to '0'.
EB-3152 – Decoders, Multiplexers and Adders
80
Preparation questions:
1.
What is the value of Y when A1,A0 = B1,B0?
A0
B0
A1
B1
Y
(a) 0
(b) 1
2.
What is the value of Y when A1,A0  B1,B0?
A0
B0
A1
B1
Y
(a) 0
(b) 1
3.
Can the following circuit be used as a comparator?
A0
A1
B0
B1
Y
(a) Yes
(b) No
EB-3152 – Decoders, Multiplexers and Adders
81
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Step 5:
Observe the display and check that the experiment board name
appear and no fault is detected.
Step 6:
Use the panel gates and implement a 2-bit comparator. Use OR and
NOT gates to implement the NOR gate.
A0
B0
A1
B1
Y
Step 7:
Connect switches S1,S0 to the circuit inputs A1,A0.
Step 8:
Connect switches S3,S2 to the circuit inputs B1,B0.
Step 9:
Connect the output of the NOR gate to the LED L0.
EB-3152 – Decoders, Multiplexers and Adders
82
Step 10: Change the state of the input switches and check that the circuit
reacts according to the state table.
B1 B0 A1 A0
S3 S2 S1 S0 Y
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
EB-3152 – Decoders, Multiplexers and Adders
83
Summary questions:
1.
What is the value of Y when A1,A0 = B1,B0?
A0
B0
A1
B1
Y
(a) 0
(b) 1
2.
What is the value of Y when A1,A0  B1,B0?
A0
B0
A1
B1
Y
(a) 0
(b) 1
3.
Can the following circuit be used as a comparator?
A0
A1
B0
B1
Y
(a) Yes
(b) No
EB-3152 – Decoders, Multiplexers and Adders
84
Experiment 9 – Troubleshooting
Objectives:
 Troubleshooting faults in an electrical circuit.
Equipment required:
 EB-3100
 EB-3152
 Banana wires
Discussion:
The EB-3100 includes 10 relays for fault insertion or for switching external
components.
The fault screen is selected by the Options/Graph key.
FAULTS
Please choose
Fault No.: 0–9
Activated fault
Number: 0
Num Lock
Typing a fault number and pressing ENTER operates the required relay for the
required fault.
Fault No. 0 means No Fault.
Which relay creates the required fault is registered in the plug-in experiment
board controller.
On entering a fault number, the system addresses the experiment board
controller and asks for the relay number. After that, it executes the required
fault.
EB-3152 – Decoders, Multiplexers and Adders
85
The experiment board controller saves the last registered fault number in its
memory. This memory is non-volatile.
This is why the system does not allow us to enter a fault number when no
experiment board is plugged.
When an experiment board that a certain fault (other than zero) is registered in
its memory is plugged into the system, a warning message appears on the
system's screen.
This feature enables the teacher to supply the students various experiment
boards with planted faults for troubleshooting.
Note:
It is recommended (unless it is otherwise required), to return the
experiment board fault number to zero before unplugging it.
EB-3152 – Decoders, Multiplexers and Adders
86
Procedure:
Step 1:
Connect the EB-3100 to the power supply.
Step 2:
Connect the power supply to the Mains.
Step 3:
Turn ON the trainer. The DVM screen should appear on the display.
Step 4:
Plug the EB-3152 into the EB-3100.
Fault No. 1:
Step 5:
Implement the following circuit.
S0
S1
S2
A
B
C
S3
Step 6:
D
E
Y
Enter fault no. 1.
What is the fault?
(a)
(b)
(c)
(d)
Input A is disconnected.
Input B is disconnected.
Input D is disconnected.
Input E is disconnected.
EB-3152 – Decoders, Multiplexers and Adders
87
Fault No. 2:
Step 7:
Implement the following circuit.
S0
S1
S2
A
B
C
S3
Step 8:
D
E
Y
Enter fault no. 2.
What is the fault?
(a)
(b)
(c)
(d)
Input A is disconnected.
Input B is disconnected.
Input D is disconnected.
Input E is disconnected.
EB-3152 – Decoders, Multiplexers and Adders
88
Fault No. 3:
Step 9:
Implement the following circuit.
S0
S1
S2
A
B
C
D
S3
E
F
Step 10: Enter fault no. 3.
What is the fault?
(a)
(b)
(c)
(d)
Input A is disconnected.
Input B is disconnected.
Input C is disconnected.
Input E is disconnected.
EB-3152 – Decoders, Multiplexers and Adders
Y
89
Fault No. 4:
Step 11: Implement the following circuit.
S0
S1
S2
A
B
C
D
S3
E
F
Step 12: Enter fault no. 4.
What is the fault?
(a)
(b)
(c)
(d)
Input A is disconnected.
Input B is disconnected.
Input C is disconnected.
Input E is disconnected.
EB-3152 – Decoders, Multiplexers and Adders
Y
90
Fault No. 5:
Step 13: Implement the following circuit.
S0
S1
S2
2
S3
S4
IN0
IN1
IN2
IN3
EN
OUT
MUX
A
L0
B
S5
S6
Step 14: Enter fault no. 5.
What is the fault?
(a)
(b)
(c)
(d)
IN0 is disconnected.
IN1 is disconnected.
IN2 is disconnected.
IN3 is disconnected.
EB-3152 – Decoders, Multiplexers and Adders
91
Fault No. 6:
Step 15: Implement the following circuit using the B1 and B6 components.
S0
A
S1
B
S2
G
Y0
DEC1
Y1
Y2
Y3
L0
L1
L2
L3
Step 16: Enter fault no. 6.
What is the fault?
(a)
(b)
(c)
(d)
A is disconnected.
B is disconnected.
G is disconnected.
Y0 is disconnected.
EB-3152 – Decoders, Multiplexers and Adders
92
Fault No. 7:
Step 17: Implement the following circuit.
S0
S1
S2
D0
C0
A0 FA0
B0
C1
L0
S0
C1
A1
B1
D1
L1
S4
FA1
Step 18: Enter fault no. 7.
What is the fault?
(a)
(b)
(c)
(d)
C0 is disconnected.
A0 is disconnected.
B0 is disconnected.
A1 is disconnected.
EB-3152 – Decoders, Multiplexers and Adders
93
Fault No. 8:
Step 19: Implement the following circuit.
S0
S1
S2
D0
C0
A0 FA0
B0
C1
L0
S0
C1
A1
B1
D1
L1
S4
FA1
Step 20: Enter fault no. 8.
What is the fault?
(a)
(b)
(c)
(d)
C0 is disconnected.
A0 is disconnected.
B0 is disconnected.
A1 is disconnected.
EB-3152 – Decoders, Multiplexers and Adders