Microcomputer System
ECE 3551
Laboratory Experiment 4
IIR Digital Filter Implementation
Preformed By:
Brandon Schmitt
Submitted:
April 25, 2007
Table of Contents
Page
Abstract………………………………………………………… 1
Introduction……………………………………………………. 1
Implementation………………………………………………… 2
Filter Stages…………………………………………….. 2
Challenges…………………………………………………….. 4
Conclusion……………………………………………………. 4
Appendix A…………………………………………………… 6
Abstract
The goal of the IIR lab is to design and develop 3 separate implementations of a digital
IIR filter in an embedded platform. Analog Devices’ Blackfin BF533 DSP is to be
utilized to implement a floating point, integer and fract16 number representation version
of the IIR filter.
Introduction
In order to develop the filter implementations Analog Devices’ BF533 DSP on the EZKit Development Board will be used. The BF533 DSP supports development through the
VisualDSP++ development environment. The code is programmed in C then compiled
and loaded onto the development board through a USB interface cable. The EZ-Kit
supports the USB interface, real-time in circuit debugging, and peripheral circuits to
interface audio.
The IIR filter like all analog signal filters is design to reduce the magnitude of frequency
components outside the desired range. Unlike analog implementations of signal filters
built with capacitors, inductors and resisters, the IIR is a digital filter. A fast digital signal
processor (DSP) such as the BF533 is used to create a model of the filter in programmed
code. The model then acts upon small sections of the analog signal sampled forty-eight
thousand times per second.
By implementing software versions of a filter it is possible to configure multiple stages
with multiple coefficients and delay lines quickly and efficiently. A change to a digital
filter can be made by altering a line of code avoiding the need to remove, reconfigure and
rebuild analog components. Some digital implementations can be reprogrammed while
the chipset is inside a working production board, as is the case with the EZ-Kit
development board. To change the filter’s structure, coefficients, and as such frequency
response, a programmer needs only to change a few lines of code and reload the program
onto the DSP’s chipset. The result is a high quality filtering system which is easy to
implement and can outperform much more complex analog filter designs.
The IIR filter works by implementing three separate stages. The first, a gain stage alters
the amplitude of the incoming signal. The second two are filter stages which can be
modeled by their general frequency response.
b0  b1 z 1  b2 z 2
H z  
1  a1 z 1  a2 z 2
(kepuska, p.3)
Each of the two remaining filter stages have associated coefficients b0, b1, b2, a1, and a2,
and frequency delays z-1 and z-2.
For the purpose of filter implementation it is easier to sample to analog waveform then
act upon the waveform in the time domain using an appropriate time-domain
configuration of the IIR filter.
d m  xm  a2 d m  2  a1d m  1
ym  b2 d m  2  b1d m  1  b0 d m
(kepuska, p.3)
where d[m – n] n = 0, 1, 2 represents a delay line of magnitude 3.
Implementation
The first step to implementing the IIR filter on Analog Devices BF533 is to initialize and
configure the appropriate registers and subsystems of the DSP. For this lab the analog to
digital converter (ADC), digital to analog converter (DAC), direct memory addressing
(DMA), serial port, leds 4 through 9 and EZ-Kit push buttons SW4 and SW5 were
necessary.
Initialization of serial port, dma, ADC and DAC did not differ from the previous audio
labs in the class. To configure the SW4 and SW5 switches FlashA PortA was set to input.
To configure leds 4 through 9, the six least significant bits of FlashA PortB were set to
output and the data was set to zero. The data update resulted in all six leds controllable
through the FlashA_PortB_Data register and set to off.
Audio input was achieved by converting the analog signal waveform to a digitally
sampled stream of 24-bit samples at a rate of forty-eight thousand times per second. The
data was converted by the AD1386 digital to analog converter on the EZ-Kit
development board, and passed to the processor via the SPORT0 serial port interface.
The sampled signal values arrive and the SPORT0 interrupt is triggered. Depending upon
the system output state which is selected by the user using the switches SW4 and SW5
the value is then bit shifted to the left eight places to adjust the range such that the sample
can be handled as a 32-bit integer and passed to either the low pass filter processor, the
high pass filter processor, or the value is not bit shifted and sent directly to the output.
Filter Stages
The IIR filter implementations are broken into 3 distinct stages. The first, a gain stage
simply applies a scaling factor to the input. The second and third stages are similar to one
another differing only in the coefficients used. The low pass and high pass filter
configurations are achieved by applying specific coefficients in each of the three stages.
Both second and third stages are implemented in a similar manner. Each requires a delay
line of three values consisting of the current sample, and the previous two samples. The
previous two samples are shifted back one location, then the current sample is scaled and
combined with scaled versions of the two delayed version and stored in the current delay
line point. The output of each stage is a combination of each delay line point multiplied
by its associated coefficient. A C code example follows.
// Stage 1 - Gain
iDataIn = Stage1->B0 * iDataIn;
// Stage 2
Stage2->Delay[2] = Stage2->Delay[1];
Stage2->Delay[1] = Stage2->Delay[0];
Stage2->Delay[0] = Stage2->A0 * (iDataIn - Stage2->A1 * Stage2>Delay[1] - Stage2->A2 * Stage2->Delay[2]);
iDataIn = (Stage2->B2 * Stage2->Delay[2] + Stage2->B1 * Stage2>Delay[1] + Stage2->B0 * Stage2->Delay[0]);
// Stage 3
Stage3->Delay[2] = Stage3->Delay[1];
Stage3->Delay[1] = Stage3->Delay[0];
Stage3->Delay[0] = Stage3->A0 * (iDataIn - Stage3->A1 * Stage3>Delay[1] - Stage3->A2 * Stage3->Delay[2]);
iDataIn = (Stage3->B2 * Stage3->Delay[2] + Stage3->B1 * Stage3>Delay[1] + Stage3->B0 * Stage3->Delay[0]);
return iDataIn;
Each stage’s output feeds the input of the following stage. The last stage’s output
becomes the output of the filter.
In order to store each stage of both high pass and low pass filter a special variable was
designed using a variable structure (struct) and called “FilterDef.”
typedef struct {
float
float
float
float
float
float
float
float
A0;
A1;
A2;
B0;
B1;
B2;
BFactor;
Delay[3];
} FilterDef;
Each stage of the low and high pass filters were then built by filling the appropriate
coefficient variables in the FilterDef struct. With this implementation the filter’s
coefficients and delay lines were available across function calls and easily declared and
configured.
The low and high pass filters were configured in an initialization function
Init_FiltersFloat() which can be found in Initialize.c.
Challenges
Many of the challenges encountered during implementation of the floating point IIR filter
stemmed from difficulties working in the development environment or working with the
number representation in the processor. Initially work began on implementing the filter
using a filter processing function included in the SDK. Work then was redirected to
implementing the filter using a custom function with new coefficients. This path lead
ultimately to an acceptable implantation.
Another challenge encountered was related to how the 24-bit signal sample is represented
within a 32-bit int value. Before bit shifting the input to the filters was applied the output
was heavily distorted. Bit shifting the input, then bit shifting the output back helped solve
part of the distortion experienced.
Due to time restrictions the floating point implementation of the IIR filter was the only
one examined. After implanting the low pass version the high pass filter was easy to
implement.
One of the most useful troubleshooting tools used was to record 1024 samples into a
buffer integer array then halt the code and examine the buffer using Visual DSP++’s plot
function. By passing an input sinusoidal waveform from Matlab, then viewing the output
plot it helped significantly when tracking down signal distortion issues in the code.
Viewing the output plot made it easy to identify the need to bit shift the input, and to
apply proper scaling in the first filter stage. The latter example was determined when the
output plot was clearly overflowing the number representation, resulting in a square
waveform in the plot section.
Conclusion
Upon completion of the IIR digital filter the results were quite good. The low pass filter
passed test frequencies below 750 Hz with no distortion and little attenuation. A test
frequency of 10 kHz however was attenuated below the threshold of hearing at the
volume the speakers were set. The inverse was true for the high pass filters. High
frequency test tones passes with little attenuation while low frequency tones were
significantly attenuated.
Digital filters such as the IIR are fairly simple to implement and in the case of the IIR
performed quite well for the frequencies examined. Using a high speed digital signal
processor like the BF533 allows filtering to be applied in real time with sampling
frequencies of 48 kHz. In general both the processor and the filter implantation
performed well under testing.
For future labs the only improvement would be to add equipment to the lab which would
allow qualitative measurements of filter signal output to be taken. An addition to the
laboratory manual regarding the Matlab code necessary to generate a pure tone sinusoid
would also have been helpful.
Appendix A: References
1. ECE 3551 MICROCOMPUTER SYSTEMS 1, Lab 4—Learn to process audio data,
Dr. Veton Kepuska.
2. ADSP–BF533 EZ-Kit Lite Evaluation Systems Manual, Analog Devices.