International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Vol. 3 Issue 8, August 2014, ISSN: 2278-909X(Online).
High Performance Dynamic Hybrid Flip-Flop For
Pipeline Stages with Methodical Implanted Logic
K.Vajida Tabasum, K.Chandra Shekhar
Abstract-In this paper we introduce a new high performance
dynamic hybrid flip-flop (DHFF) for pipeline stages and a new
implanted logic module (DHFF-ILM). These proposed designs
satisfy the low power and reduced pipeline overhead
requirements. The DHFF presents less power dissipation since the
node at the output which drives the output transistors is splits by
which the pre-charge capacitance gets reduce. The major factor
for power dissipation in flip-flops is pre-charge capacitance. So by
reducing the pre-charge capacitance power dissipation is reduced
in DHFF. The DHFF-ILM offers to incorporate Complex logic
functions. The aim of this DHFF-ILM is to reduce the pipeline
overhead in modern deep pipelined architectures. The
performance comparisons made in micro-wind tool show power
reduction of 30% compared to the XCFF.
Index Terms- Implanted Logic, flip-flops, high performance, less
power dissipation, reduced pipeline overhead.
I. INTRODUCTION
Low power consumption has become a highly important design
concern in VLSI era and will become more and more important as
we move to all pipeline architecture design. Most of the current
designs are synchronous which implies that flip-flops and latches are
involved in one way or another in the data and control paths. One of
the challenges of low power methodologies for synchronous systems is
the power consumption of these flip-flops and latches. It is important
to save power in these flip-flops and latches without compromising
state integrity or performance. So the extensive work has being done to
improve the performance of flip-flops in past few decades.
Basically the flip-flops are categorized as static flip-flop,
dynamic flip-flops and semi-static flip-flops. Dynamic flip-flops and
semi-static flip-flops are the high performance flip-flops. The dynamic
flip-flops store the logic value at the gate capacitance of transistors
instead of at the output node as in static flip-flops. The performance of
static flip-flops is superior in terms of power consumption and glitch
reduction to dynamic circuits when the fan-in is small.
Manuscript Received July, 2014;
K. Vajida Tabasum is with the Sri Sai Institute of Technology and
Science, Rayachoty-516269, India.
K. Chandra Shekhar is with the department of Electronics and
Communication Engineering, Sri Sai Institute of Technology and
Science, Rayachoty-516269, India.
The semi dynamic flip-flops are also known as hybrid
flip-flops. They contain the hybrid architecture that combines
the advantages of both static and dynamic flip-flops. The semi
dynamic flip-flops offer the reduced power, area and delay.
The semi dynamic flip-flops allow incorporating the complex
logic functions efficiently since it has only one transistor that is
driven by the data input. This will helps in reducing the
pipeline overhead in the synchronous systems. Several semi
dynamic flip-flops have been proposed in the past few decades
aiming at reduction of pipeline overhead, area and delay.
A recent paper presents a flip-flop named Cross
Charged Control Flip-flop (XCFF). XCFF works based on the
principle of split dynamic node. XCFF has more advantages
over the static and dynamic flip-flops. It occupies less area
since makes use of 21 no. of transistors. XCFF presents less
power consumption as pre-charge capacitance is reduced by
splitting the dynamic node at the output which drives the
output transistors. Although XCFF presents reduced area and
less power dissipation it has drawbacks such as unwanted
power dissipation when input data does not changes for more
than one clock cycle and large hold time requirements which
causes the increase in delay. XCFF does not allow to
incorporate logic functions although it has single transistor
driving by the input data because when the logic in implanted
in XCFF it is more susceptible to charge sharing at the
dynamic nodes.
The aim of the proposed DHFF is to overcome the
drawbacks of the XCFF such as redundant power dissipation
and charge sharing problem. DHFF-ILM presents the area,
power and speed efficient architecture to reduce the pipeline
overhead. The performances of the existing flip-flops are
compared with that of the DHFF in the micro wind tool. It
shows the 30% of reduction in power dissipation. The proposed
DHFF-ILM has power reduction of 27% compared to the
SDFF with logic module.
The rest of this paper is divided as described below:
Section II describes the existing flip-flop architectures and
describes the disadvantages of these existing flip-flops
architectures. In Section III, the proposed DHFF architecture
and its working operation is illustrated. In Section IV,
describes architecture of the DHFF-ILM and its working
operation. In Section V, we describe the performance
comparisons of proposed flip-flops with the existing flip-flop
architectures
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All Rights Reserved © 2014 IJARECE
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Vol. 3 Issue 8, August 2014, ISSN: 2278-909X(Online).
Figure 1: Power PC 603 Flip- flop
Figure 3: Semi dynamic Flip-flop
important since it affects the power dissipation. One approach
to reduce CLK load is to make the ratioed. The next static
flip-flop to be discuss is Power PC 603 flip-flop shown in fig1.
Power PC 603 flip-flop is one of the fastest classical structures.
Its main advantage is the short direct path and the low power
feedback. It has poor data to output latency since it has the
positive setup time and also it is very much affective to the
clock signal slopes and data feed through. All these drawbacks
make the Power PC 603 weak in performance. In spite of all
these drawbacks it is consider as low power solution when the
speed is not considered.
Coming to the second category of flip-flops, dynamic flipflops are the high performance flip-flops designed to overcome
the drawbacks of static designs such as area and speed. Dynamic
flip-flops store the logic value at the gate capacitance of the
transistor. They occupy less area when compared to the static
flip-flops. The speed of operation of the dynamic flip-flops is
better when compared to the static flip-flops. Even though the
Figure 2: Hybrid Latch Flip-flop
dynamic flip-flops are faster and smaller when compared to the
static flip-flops they have some drawbacks such as generally,
dynamic flip-flops operate in two phases 1. Pre-charge phase and
II. ANALYSIS OF EXISTING FLIP-FLOP ARCHITECTURES evaluation phase, during the evaluation phase changes in the input
data makes the flip-flop more susceptible to charge sharing
Many no. of flip-flops and latches have been published in the
problem. In dynamic flip-flops during some time period output
past few decades. All these flip-flops are categorized as static flip- node is connected to neither to ground nor to supply which makes
flops, dynamic flip-flops and semi static flip-flops. Static flip-flops the design affective to noise. Some of the mostly used dynamic
flip-flops are clocked CMOS (C2MOS) flip-flop, True Single
works based on the principle of charge regeneration. The logic value
2
in static flip-flops gets stored at the output node. Static flip-flops are Phase Clock (TSPC) flip-flop. C MOS shown in Fig. 4 presents
the good low power features such as clock load and low power
preferable only when the power is concerned because they occupy
feedback. Races are just not possible since the overlaps activate
more area and also the delay is more. In synchronous systems, total either the pull-up or the pull-down networks but never both
delay associated with the latches or flip-flops is concerned as D-Q simultaneously. This is not hard to meet in practical designs,
delay. D-Q delay is the sum of CLK-Q delay and setup time of the
making C 2MOS especially attractive in high speed designs where
flip-flop. Static designs are more susceptible to large D-Q delay avoiding clock overlap is hard. When we consider the two phase
clocking schemes in the Clocked CMOS flip-flop care must be
because of the positive setup time.
taken in rout6ing the clock signals ensuring the non over-lapping
Some of the high performance static flip-flop designs are of clock signals. The TSPC flip-flop proposed by Yuan and
Transmission gate based static flip-flop, Master-slave based flip-flop, Svensson uses a single clock without any inverted clock as
Power PC 603.Transmission gate based static flip-flop occupies less shown in Fig.5 . The main advantage of the TSPC is the use of
single phase clock. The disadvantage is slight increment in usage
area but the logic level at the output gets degraded. In this
of no. of transistors when compared with the C2MOS.TSPC
transmission gate static flip-flop logic level can be recovered by
offers an additional advantage: the possibility of
using the weak inverter at the output. One of the main drawbacks of
embedding logic functionality into the flip-flop.
transmission gate static flip-flop is the high capacitive load presented
to the CLK signal. CLK load is much
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All Rights Reserved © 2014 IJARECE
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Vol. 3 Issue 8, August 2014, ISSN: 2278-909X(Online).
Figure 4: Clocked CMOS Flip-flop
.
Figure 6: Conditional Data Mapping Flip-flop
Figure 5: True Single Phase Clock flip-flop
The final category of flip-flops is Semi dynamic flip-flops.
Semi-dynamic flip-flops present the advantages of both static flip-flops
and dynamic flip-flops. It compromises of dynamic frontend structure
and static output structure. The most commonly used semi-dynamic
flip-flops are SDFF (Semi Dynamic Flip-Flop) and HLFF (Hybrid
Logic Flip-Flop). SDFF is fastest classical flip-flop architecture as
shown in fig.3. Although the SDFF is fastest it consumes more power
because of the large clock load and large pre-charge capacitance. Next
is the HLFF as shown in Fig.2. HLFF is not fastest when compared to
the SDFF but it presents low power dissipation. One of most important
advantage of the SDFF is it allows to incorporate logic module within
the flip-flop which helps in reducing the pipeline overhead.
The main sources which causes the power dissipation in the
semi dynamic flip-flops is the repeated data transitions and large precharge capacitance. Many researchers have been done to decrease the
repeated data transitions. Conditional Data Mapping flip-flop (CDMFF)
is also one of the most effective among them. It will decrease the power
consumption by reducing the repeated transitions .CDMFF contains
three transistors in series at the output node, same as in HLFF makes
the design require to have large hold time. Also, the extra transistors
make the design more bulky and causes increase in power dissipation.
Figure 7: Cross Charge Control Flip-flop
The large Pre charge capacitance in the state-of-art designs
is due to the pre charge node which needs to drive both the pull-up
and pull-down transistors. This drawback considered as a main
concern in design of flip-flops. As the remedy for this problem
only XCFF was introduced. In XCFF pre charge node which drives
the output pull-up and pull-down transistors is splits as shown in
Fig.7. By splitting the dynamic node in this manner reduces the pre
charge capacitance through which the power dissipation is
reduced. Since only one transistor is being drive during each clock
cycle the total power consumption is reduced. This XCFF also
offers the low clock driving load. But, the XCFF has some
drawbacks such as unwanted power dissipation during repeated at
the input. When the data input has more no. of 0’s and 1’s
continuously the dynamic node needs to pre charge repeatedly
which causes the more power dissipation.
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All Rights Reserved © 2014 IJARECE
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Vol. 3 Issue 8, August 2014, ISSN: 2278-909X(Online).
III. PROPOSED DHFF ARCHITECTURE
The aim of the Proposed DHFF design is to overcome the
drawbacks of XCFF. DHFF also makes use of the split dynamic
node structure as that of in XCFF. This DHFF design offers the
less power dissipation when compared to the XCFF.
discharge the node Y1 is consider to be 18 ps. The overlapping
period
In this pre charge capacitance is reduced to decrease the
power consumption by using the split pre charge node same as in
the XCFF. By splitting the pre charge node the output load gets
reduced. There are some other metrics the justify the DHFF as
effective flip- flop such as small clock to output delay which is
defined as propagation delay from the input terminal to Q
terminal. The power consumption of the DHFF strongly depends
on its architecture and the input data pattern. Also, all nodes of
the architecture responsible for the increase in power
consumption as the total power consumption of the flip-flop can
be divided as internal power consumption of flip-flop, local clock
power consumption that is caused when the clock fed to the
internal stages, Local data power consumption that is consumed
by the implanted logic. So that only split dynamic pre charge
node is used in DHFF which will reduce the output load resulting
in reduced power dissipation.
Fig. 8: Proposed DHFF
The DHFF operates in two phases same as the dynamic flipflops, 1) Pre charge phase when the clock is low 2) Evaluation
phase when the clock is high. The data transition from the input to
output takes place during 1-1 overlap of CLK and CLKB. During
the pre charge i.e. , when the CLK signal is at logic 0 the node y1
gets charged to VDD through p1 transistor. During the overlapping
period of CLK and CLKB if data in i.e., in1 is high the charge
stored at the node y1 discharges through n1, n2 and n3. This
changes value at the output of inv1 to go high and output inv out to
get discharge through the transistor n5. When the CLK goes low
the circuit again enters into the pre charge phase. If the data input
i.e., in1 is low during 1-1 overlap of CLK and CLKB then charge
stored at the node y1 remains same. This makes the inv1 output
switches to logic 0. This results in output inv out to get charged to
the VDD through the p3 transistor.
Figure 9 : Semi-dynamic flip-flop implanting NAND logic
If the data is at logic0 during the overlap period, the node
Y1 remains high and Y2 is pulled low through n4 as the CLK goes
high. So the node inv out is charged high through p1 and n3 gets
off. At the end of evaluation phase, when the CLK goes low, node
Y1 remains high and Y2 stores the charge dynamically. This
design presents the negative setup time because the small
transparency period during the 1-1 overlap of CLK and CLKB
makes the input to sampled more times
The overlapping period of CLK and CLKB depends on
the setup time and hold time of the flip-flop. Setup is defined as the
minimum time period before the CLK edge, where the input
should be stable so that the proper transition is done. Hold time is
defined as the minimum time period after the CLK edge, where the
input should be stable so that the proper transition is done. The
proper setup time and hold time of DHFF flip-flop depends on the
switching threshold of the inv1 and inv2. For proper operation the
overlapping period must be greater than the time that is required to
discharge the node Y1. The optimum time period that is needed to
Figure 10: Dynamic Hybrid Flip-flop implanting NAND logic
IV. PROPOSED DHFF-ILM
The challenge has been raised to improve the flip-flop
architectures which can allow the implanted logic module
effectively because the idea of incorporating the logic module is
not new. One of the most preferable flip-flops which allow
implanting of logic module efficiently is the SDFF. Many
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All Rights Reserved © 2014 IJARECE
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Vol. 3 Issue 8, August 2014, ISSN: 2278-909X(Online).
functions such as AND, OR functions, multiplexers and complex
functions can also be implanted. In the positive edge SDFF to
implant the N input logic function N no. of NMOS transistors are
needed to be used as a result, reduced area and fast operation can
be achieved. The architecture of the SDFF-ELM is shown in
Fig.10 .One of the most important benefit of SDFF is it allow to
implant the logic easily. This implanted architecture offers a very
fast and small implementation.
The proposed DHFF-ILM presents less power
dissipation when compared to the SDFF with implanted logic
module. DHFF-ILM works same as the DHFF except that during
the evaluation period, the output get switched to the logic value
based on the inputs given to the inputs of the logic module during
the pre charge phase. DHFF-ILM offers less power dissipation. It
presents less area which helps in reducing the pipeline overhead.
Any complex functions can be implemented in DDHF-ILM. The
architecture of the DDHF-ILM is shown in Fig. 11.
Figure 13: Simulation Results of Proposed DHFF
Some of the functions that can be implanted in DHFF-ILM
are shown in Fig 12.
(a)
(b)
(c)
Figure 11: Implanted logics a) NAND b) NOR c) Multiplexer
V.SIMULATION RESULTS
To verify the performance of the existing and proposed
architectures DSCH (Digital Schematic) and Micro wind
tools are used. In DSCH tool the functionality of the design
can verified very comfortably and to verify the power
dissipation, area and delay information Micro wind tool is
the best.
Figure 12: Simulation Results of XCFF
Figure 14: Simulation results of SDFF-ELM implanting
NAND function
Fig. 16: Simulation results of DHFF-ILM implanting
NAND function
The simulation results shown in DSCH and Micro wind
shows that the power dissipation presented by the XCFF is
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All Rights Reserved © 2014 IJARECE
International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE)
Vol. 3 Issue 8, August 2014, ISSN: 2278-909X(Online).
12.27 µW. The power dissipation presented by the DHFF
is 6.133µW. These results show the difference of 40%. The
power dissipation in the SDFF with implanted logic is
18.068µW and the power dissipation in the DHFF-ILM is
1.048µ. All these results show that DHFF and DHFF-ILM
are the high performance designs when compared to the
existing designs.
VI.CONCLUSION
In this paper, a novel high performance DHFF and the
DHFF-ILM were proposed. Many existing flip-flop
architectures were discussed to get correct analysis of
drawbacks on which we are concentrating in the proposed
designs. Power dissipation in DHFF and DHFF-ILM is
reduced by reducing the pre charge capacitance at the pre
charge output node. As per the simulation results, it was
proved that the DHFF and DHFF-ILM are high
performance designs.
K. Vajida Tabasum received the B.Tech degree in
electronics and communication engineering degree from Sri Sai
Institute of Technology and Science affiliated to Jawaharlal
Nehru Technological University, Anantapur, India in 2012 and
currently per suing M.Tech degree in VLSI system design from
Sri Sai Institute of Technology and Science affiliated to
Jawaharlal Nehru Technological University, Anantapur, India.
K. Chandra Shekhar received the B.Tech degree in
electronics and communication engineering from SCDE affiliated
to Jawaharlal Nehru Technological University, Hyderabad, India
and received the M.Tech degree in DECS from AITS affiliated to
Jawaharlal Nehru Technological University, Anantapur, India.
He has been with the department of electronics and
communication engineering, Sri Sai Institute of Technology and
Science, Rayachoty, since 2005, where he is currently the Head
of Department. His current research includes image processing.
FUTURE SCOPE:
We can improve performance of the DHFF-ILM by
replacing the pull-down network by the efficient logic
network such as domino logic, CVSL, Clocked CMOS.
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