Enabling success from the center of technology™
Xilinx Embedded
Processing Solutions
2
Goals
Enabling success from the center of technology™
Learn why FPGA embedded processors are
seeing significant adoption in today’s
designs
What options are available for Xilinx
embedded solutions
Understand how the latest Xilinx
development tools simplify the embedded
design process
Copyright © 2007. Avnet, Inc. All rights reserved.
3
Agenda
Enabling success from the center of technology™
Advantages of using Xilinx embedded processors
Design flow overview
Demo 1 – Creating a design
Processor options
Understanding the development environment
Demo 2 – Running the design
Copyright © 2007. Avnet, Inc. All rights reserved.
4
Agenda
Enabling success from the center of technology™
Advantages of using Xilinx embedded processors
Design flow overview
Demo 1 – Creating a design
Processor options
Understanding the development environment
Demo 2 – Running the design
Copyright © 2007. Avnet, Inc. All rights reserved.
5
Why Embedded Processors?
Enabling success from the center of technology™
Typical embedded system
– FPGA with custom functions
– Stand-alone processor with
peripherals and memory
Opportunity
– Move processor system into
FPGA fabric
– Upgrade functions to improve
performance and optimize cost
Advantages
– Any thoughts?
Copyright © 2007. Avnet, Inc. All rights reserved.
FPGA
FIFO
Filter
FIFO
Ethernet
Processor
Processor
Mem Cntrl
PHY
SDRAM
DDR2
6
FPGA Advantage
Enabling success from the center of technology™
Customization
Risk mitigation
Lower design cost and less inventory
Hardware acceleration
Copyright © 2007. Avnet, Inc. All rights reserved.
7
Customization
Enabling success from the center of technology™
Choose between hard or
soft processors
ARB
Large menu of peripherals
to choose from and modify
FPU
EMAC
CPU
PCI
DDR2
Create user-defined
peripherals
CACHE
INTC
Create non-standard
solutions unavailable in
stand-alone packages
DMA
CUSTOM
Copyright © 2007. Avnet, Inc. All rights reserved.
UART
UART
UART
GPIO
GPIO
8
Risk Mitigation
Enabling success from the center of technology™
Allows system-level changes late in project
Processor hardware is field-upgradeable
Guarantees product lifespan
– Soft IP can easily be upgraded to use new silicon
Hard-processors continue on Virtex roadmap
Soft-processor code can be purchased
– Can freeze product to satisfy military requirements
Copyright © 2007. Avnet, Inc. All rights reserved.
Lower Design Cost and Less Inventory
9
Enabling success from the center of technology™
Design consolidation
– Sweep external components into the FPGA
– Smaller form-factor, less real-estate
– Increased reliability
Procurement consolidation
– Combine device(s) across product range
– Footprint compatibility
Reduced inventory holding
– Use the same hardware for multiple products
• FPGA content controls functionality
Copyright © 2007. Avnet, Inc. All rights reserved.
Hardware Acceleration
10
Enabling success from the center of technology™
Create custom co-processor hardware
– Connected via low latency dedicated channel
Enables optimum “system partitioning”
Performing some software tasks
in hardware can be expensive
Performing some hardware tasks
in software can be slow
Tune your system for the optimum hardware/software balance.
Off-the-shelf processors can not deliver this!
Copyright © 2007. Avnet, Inc. All rights reserved.
Tailor the System to Achieve Performance
11
Enabling success from the center of technology™
Custom Hardware Logic
MP3 decoding with custom hardware logic
– XCELL magazine #58 Third Quarter 2006
100MHz
100MHz MicroBlaze,
MicroBlaze,
pure
software
pure software
== 146
146 seconds
seconds
1X
IMDCT
100MHz
100MHz MicroBlaze
MicroBlaze
+FSL
+FSL ++ LL
LL MAC
MAC
== 99 seconds
seconds
16X
100MHz
100MHz MicroBlaze
MicroBlaze
+FSL
+
DCT
+FSL + DCT ++ IMDCT
IMDCT ++ LL
LL MAC
MAC
== 77 seconds
seconds
1x
DCT
2x
21X
8x
10x
Performance Improvement
Note: MicroBlaze v4.00 core, ML40x board, 100MHz system clock, EDK8.1
Copyright © 2007. Avnet, Inc. All rights reserved.
20x 50x 100x
LL MAC
What Do Embedded Designers Need ?
12
Enabling success from the center of technology™
Designers are saying that they…
Solution Requirement
Want to minimize inventory of off-the-shelf
(OTS) parts or inventory of different OTS parts for
each project
Inventory one type of silicon part (e.g.
FPGA) that can be used across many
projects
Want processor/sub-system that’s a fit to the
target application
A processor with a custom mix of
standard peripherals or mix of custom
peripherals
Want a solution that will not become obsolete
Want to spend less time creating and debugging
custom IP blocks
Want to use sw resources across different
projects
Maintain same processor code for
software re-use
A wide range of pre-verified intellectual
property with complete support
infrastructure
Common software development tools
Copyright © 2007. Avnet, Inc. All rights reserved.
13
Agenda
Enabling success from the center of technology™
Advantages of using Xilinx embedded processors
Design flow overview
Demo 1 – Creating a design
Processor options
Understanding the development environment
Demo 2 – Running the design
Copyright © 2007. Avnet, Inc. All rights reserved.
14
Embedded Processor Design
Enabling success from the center of technology™
FPGA
FIFO
Filter
So how are we going to
develop this embedded
processor system block ?
FIFO
Processor
Ethernet
Mem Cntrl
PHY
SDRAM
DDR2
Processor
Ethernet
Mem Cntrl
Copyright © 2007. Avnet, Inc. All rights reserved.
15
Embedded Design Flow
Enabling success from the center of technology™
Select Platform
Components
Build Hardware
Build Software
.bit File
Download
Hardware
.elf File
Download
Software
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16
Selecting Platform Components
Enabling success from the center of technology™
Select Platform
Components
Build Hardware
.bit File
Download
Hardware
Build Software
.elf File
Download
Software
Inputs
– Processor system requirement
– Board description file*
Builder wizard
– Basic selections
Outputs
– Hardware specification file
– Software specification file
– Hardware constraints file*
– Application code
* optional
Copyright © 2007. Avnet, Inc. All rights reserved.
Building the Hardware
17
Enabling success from the center of technology™
Select Platform
Components
Build Hardware
.bit File
Download
Hardware
Build Software
.elf File
Download
Software
Inputs
– Hardware specification
– Constraints
Platform generation
– Collect HDL for peripherals
Synthesis
Implementation
– Translate
– Map
– Place and route
Outputs
– Configuration file (.bit)
Copyright © 2007. Avnet, Inc. All rights reserved.
Building the Software
18
Enabling success from the center of technology™
Select Platform
Components
Build Hardware
.bit File
Download
Hardware
Build Software
.elf File
Download
Software
Inputs
– Software specification
– Hardware specification
– Application code
Generate Board Support
Package (BSP)
– Peripheral drivers
– Standard libraries
• boot code
Compile & link
Outputs
– Executable file (.elf)
Copyright © 2007. Avnet, Inc. All rights reserved.
Downloading Hardware and Software
19
Enabling success from the center of technology™
Select Platform
Components
Build Hardware
.bit File
Download
Hardware
Build Software
.elf File
Download
Software
Inputs
– Configuration file (.bit)
– Executable file (.elf)
Configure the FPGA
Initialize processor memory
Run
Outputs
– Flawless execution
– Award winning
– Best in class
Copyright © 2007. Avnet, Inc. All rights reserved.
20
Agenda
Enabling success from the center of technology™
Advantages of using Xilinx embedded processors
Design flow overview
Demo 1 – Creating a design
Processor options
Understanding the development environment
Demo 2 – Running the design
Copyright © 2007. Avnet, Inc. All rights reserved.
21
Block Diagram
Enabling success from the center of technology™
FPGA
External
Devices
Debug
Port
ILMB
Controller
MDM
ILMB
IOPB
SDRAM
Controller
GPIO
MicroBlaze
OPB
Dual-port
BRAM
JTAG
Header
GPIO
32MB
SDRAM
User LEDs
DIP
Switches
DOPB
DLMB
Controller
DLMB
GPIO
Push
Switches
UART
RS232 Port
Copyright © 2007. Avnet, Inc. All rights reserved.
22
Tool Summary
Enabling success from the center of technology™
Xilinx
Platform
Studio
(XPS)
Base System Builder (BSB) Wizard
Generate Bitstream
Build All User
Applications
.bit File
Download Bitstream
.elf File
Launch XMD
Copyright © 2007. Avnet, Inc. All rights reserved.
23
Agenda
Enabling success from the center of technology™
Advantages of using Xilinx embedded processors
Design flow overview
Demo 1 – Creating a design
Processor options
Understanding the development environment
Demo 2 – Running the design
Copyright © 2007. Avnet, Inc. All rights reserved.
Range of FPGA Embedded Processor Solutions
24
Enabling success from the center of technology™
From space efficient to high performance processors
PowerPC
Flexible integration
Scalable cost points
Features
Variable resources
MicroBlaze
PicoBlaze
Highest Performance 32-bit
General Purpose
Architecture With
Acceleration
Only Dual PowerPC core
architecture
32-bit General Purpose
Architecture Soft Core with
Acceleration
Space Efficient 8-bit Architecture
Soft Core
Performance
Extensive offering of common peripherals and IP
Copyright © 2007. Avnet, Inc. All rights reserved.
PicoBlaze for Simple Processing Solutions
25
Enabling success from the center of technology™
Free PicoBlaze 8-bit
microcontroller reference
design macro for use in
– Xilinx FPGAs
– Xilinx CPLDs
Benefits
– Predictable performance
– Minimal logic size
– Easy-to-use assembler
– Many examples
– Can be reconfigured
“On the Fly (OTF)”
Available at
– www.xilinx.com/picoblaze
Copyright © 2007. Avnet, Inc. All rights reserved.
MicroBlaze Overview
26
Enabling success from the center of technology™
MicroBlaze processor core features
• 32-bit soft processor core
• Flexible architecture - customizable, automatically optimized to the
•
•
•
•
•
•
•
•
FPGA target architecture
RISC, Harvard architecture
As small as 900 logic cells (basic CPU)
32 x 32 bit general purpose registers
Fully synchronous
Customize the processor functionality through parameters
Multiple instantiations are possible
High-speed Local Memory Bus (LMB)
On-Chip Peripheral Bus (OPB)
Supported FPGA (all architectures)
• Spartan-3
• Virtex-4
• Virtex-5
Copyright © 2007. Avnet, Inc. All rights reserved.
MicroBlaze Core
27
Enabling success from the center of technology™
IOPB
INSTRUCTION
BUFFER
INSTRUCTION
DECODE
IXCL
Cache
Bus I/F
PROGRAM
PROGRAM
COUNTER
COUNTER
SHIFT
ALU
MULTIPLIER
DIVIDER
BARREL
FPU
DLMB
FSL
Bus I/F
Cache
ILMB
REGISTER
FILE 32x32b
Instruction Fetch Bus Interface
DXCL
DOPB
Data Bus Interface
ILMB - Instruction Local Memory Bus
IOPB - Instruction On-Chip Peripheral Bus
IXCL - Instruction Xilinx Cache-Link
DLMB - Data Local Memory Bus
DOPB - Data On-Chip Peripheral Bus
DXCL - Data Xilinx Cache-Link
MFSL - Master Fast Simplex Link
SFSL - Slave Fast Simplex Link
Copyright © 2007. Avnet, Inc. All rights reserved.
FSL Advantages
28
Enabling success from the center of technology™
No need to learn new bus architectures to build a hardware
interface
Saves clock cycles – faster than a bus interface
– Eliminates bus signaling overhead
• No arbitration
• No address decode
• No acknowledge cycles
– Decoupled data clock from CPU allows for asynchronous
operation
Control bits limit need for a complex interrupt structure
FSL port standard promotes design reuse
Copyright © 2007. Avnet, Inc. All rights reserved.
29
Fast Simplex Link (FSL)
Enabling success from the center of technology™
FSL is a point-to-point unidirectional bus that can be used to
connect input/output IP cores to the MicroBlaze processor core.
MFSL0
FSL
FSLn_M_Clk
FSLn_S_Clk
FSLn_M_Write
FSLn_S_Read
FSLn_M_Data
FIFO
FSLn_M_Control
FSLn_S_Data
FSLn_S_Control
FSLn_M_Full
User
Output IP
Core
FSLn_S_Exists
FSL
SFSL0
MicroBlaze
FSLn_S_Clk
FSLn_M_Clk
FSLn_S_Read
FSLn_M_Write
FSLn_S_Data
FIFO
FSLn_S_Control
FSLn_M_Data
FSLn_M_Control
FSLn_M_Full
FSLn_S_Exists
FSL consists of a Master Bus (writes to FIFO), a Slave Bus (reads from
FIFO). The FIFO can be up to 8K deep and 8/16/32-bits wide.
Copyright © 2007. Avnet, Inc. All rights reserved.
User
Input IP
Core
PowerPC Overview
30
Enabling success from the center of technology™
PowerPC Processor Core Features
•
•
•
•
•
•
•
•
•
•
•
•
PowerPC 405 core
32-bit RISC architecture
5-stage data-path pipeline
16KB instruction and data caches
64-bit high-speed Processor Local Bus (PLB)
Device Control Register Bus (DCR)
Timers: PIT, FIT, Watchdog
Dedicated On-Chip Memory (OCM) interface for instruction and data
JTAG Debug and Instruction Trace Support
Built-in Memory Management Unit (MMU)
600 DMIPS at 400 MHz
0.9mW/MHz typical power
Supported FPGA Architectures
•
•
Virtex-II Pro
Virtex-4 FX
Copyright © 2007. Avnet, Inc. All rights reserved.
PowerPC 405 Core
31
Enabling success from the center of technology™
PLB
IOCM
MMU
I-Cache
Array
I-Cache
Controller
Instruction-Cache
Unit 16KB
Unified TLB
(64-Entry)
Cache
Units
D-Cache
Controller
PLB
Fetch and
Decode
Logic
3-Element
Fetch
Queue
Execution Unit
ALU
Data-Cache
Unit 16KB
D-Cache
Array
Instruction
Shadow-TLB
(4-Entry)
CPU
DOCM
Data
Shadow-TLB
(8-Entry)
32x32
GPR
APU
APU
Copyright © 2007. Avnet, Inc. All rights reserved.
Timers
Timers
and
Debug
Ports
MAC
Debug
Logic
JTAG
I-Trace
32
CoreConnect Bus Architecture
Enabling success from the center of technology™
DCR
DCR Interface
PPC 405
Core
PLB
Arbiter
High-speed
Peripheral
Data
Instruction
PLB Interface
Processor
LocalRegister
Bus
(PLB)
Device
On-Chip
Control
Peripheral
Bus
(OPB)
Bus
(DCR)
64-bit data
32-bit address, 32-bit
10-bit
address,
32-bit
data
Separate
readdata
and
write
CoreConnect
consists
oftransfers
three
Single-cycle
buses
for
overlapped
Directly
accessible
by /PPC
distinct
buses
Maximum
peripherals
transfers
Interface
high loadto register-based
I/O
High
performance
devices
PLB
OPB
PLB-OPB
Bridge
Memory
Controller
I/O Device
Interface
OPB
Arbiter
Memory
Controller
FPGA
High-performance
devices are connected
to the PLB
Memory and I/O devices with
lower-performance requirements
are connected to the OPB
Copyright © 2007. Avnet, Inc. All rights reserved.
Auxiliary Processor Unit (APU)
33
Enabling success from the center of technology™
Accelerate performance beyond the core
Offloads CPU intensive operations
Extends PowerPC instruction set
Provides direct interface from CPU instruction
pipeline to FPGA logic
Enables integration of coprocessor and hardware
accelerators
Flexible high bandwidth interfaces to and from
fabric
Increase performance by over 20X
Copyright © 2007. Avnet, Inc. All rights reserved.
34
Agenda
Enabling success from the center of technology™
Advantages of using Xilinx embedded processors
Design flow overview
Demo 1 – Creating a design
Processor options
Understanding the development environment
Demo 2 – Running the design
Copyright © 2007. Avnet, Inc. All rights reserved.
FPGA System Design
35
Enabling success from the center of technology™
FPGA
FIFO
Filter
FIFO
Processor
Ethernet
Mem Cntrl
Copyright © 2007. Avnet, Inc. All rights reserved.
Embedded Development Kit
36
Enabling success from the center of technology™
Xilinx Platform Studio (XPS)
– The “hardware” tool
Xilinx peripheral IP library
– Includes MicroBlaze soft core
Software Development Kit (SDK)
Embedded debug
Copyright © 2007. Avnet, Inc. All rights reserved.
Xilinx Platform Studio (XPS)
37
Enabling success from the center of technology™
Base System Builder (BSB)
– Enables the creation of a custom PowerPCTM or MicroBlaze based
computing platform with just a few mouse clicks
– All detailed connections and a default memory map are generated
automatically
Integrated Development Environment (IDE) and tool suite used to
define, configure, and generate a hardware/software design
– Programming environment for either a stand-alone or real-time
operating system
Software development tools
– GNU C/C++ Compiler (gcc)
– GNU Debugger (gdb)
– Xilinx Microprocessor Debug Engine (XMD)
• Host-based target control using command line tools for complex regression
testing
Copyright © 2007. Avnet, Inc. All rights reserved.
Growing Suite of Peripheral IP
38
Enabling success from the center of technology™
Memory Interface Cores
– External Memory Controller
(SRAM/Flash)
– SDRAM Memory Controller
– DDR SDRAM Memory Controller
– DDR2 SDRAM Memory Controller
– System ACE Interface Controller
– BRAM Interface Controller
Peripherals
– PCI Arbiter
– External Peripheral Controller
– CAN Controller
– HDLC Interface
– Chipscope Integrated Controller
– Chipscope Integrated Logic Analyzer
– Chipscope OPB Integrated Bus Analyzer
Peripherals (continued)
– Interrupt Controller
– 16450/16550 UART
– UART Lite
– IIC
– SPI
– Ethernet (EMAC)
– Ethernet Lite (EMAC Lite)
– ATMC (Trace Core)
– Timer/Counter
– Fixed Interval Timer
– Watchdog Timer
– GPIO
– Central DMA Controller
…And More!
Pre-designed, verified and validated for Xilinx Solutions
Copyright © 2007. Avnet, Inc. All rights reserved.
Customers want to spend
less time creating and debugging
custom IP blocks
Xilinx Platform Studio SDK
39
Enabling success from the center of technology™
The “software” tool
Can be launched from XPS or independently
•
•
•
•
•
•
Software application hand-off from XPS to SDK
Software platform generation
Linker script generation
Software interface document generation
Download FPGA bitstream
Flash programmer
– Improved ease-of-use
• Project setup wizard
Enhanced C/C++ editor support includes
– Code folding of functions
– Methods
– Classes, structures, and macros
Eclipse based platform version v3.1
Copyright © 2007. Avnet, Inc. All rights reserved.
40
XPS to SDK Software Development Flow
Enabling success from the center of technology™
XPS
SDK
Generate Hardware
Platform
Generate Software
Platform
Create Software
Application Project
Libra
r
and ies
Drive
rs
Generate Software
Platform
Add Sources
and Edit
Debug
And
Profile
Compile and Link
New for 9.1i
Done?
Yes
Download to Board
Copyright © 2007. Avnet, Inc. All rights reserved.
No
41
SDK Profiling
Enabling success from the center of technology™
Determine
how
Determinethe
the
how
percentage
many
a
percentage
manytimes
timesof
of
a time
time
each
specific
function
function
took
each
specific
function
function
took
was
wascalled
called
All
Allfully
fullyintegrated
integratedinto
intothe
thePlatform
PlatformStudio
StudioSDK
SDKenvironment
environment
Copyright © 2007. Avnet, Inc. All rights reserved.
42
Platform Debug
Enabling success from the center of technology™
The ability to debug and analyze both the hardware
and software platforms simultaneously
Software debug via integrated GNU debugger
– Differentiate critical versus typical accesses using
software breakpoints
Hardware debug using ChipScope Pro
– Capture unexpected system issues and exceptions
using hardware triggers
Synchronous cross triggering between the hardware
and software
Copyright © 2007. Avnet, Inc. All rights reserved.
Cross Triggering
43
Enabling success from the center of technology™
ChipScope Pro triggering
debugger example
Complex trigger condition
detects address and data value
simultaneously
Suspends software routine
within a few clock cycles
Enabling better insight into the
HW / SW code dynamics
Copyright © 2007. Avnet, Inc. All rights reserved.
44
Xilinx Compatible OS and RTOS
Enabling success from the center of technology™
Operating System
VxWorks
Linux
Vendor
PowerPC
Wind River
z
LynuxWorks
MontaVista
Wind River
z
Nucleus Plus
LynuxWorks
Petalogix
Mentor/ATI
ThreadX
μClinux
MicroBlaze
z
z
z
Express Logic
z
z
μC/OS-II
Micrium
z
OSE
ENEA
z
Integrity
Green Hills
z
Neutrino
QNX
z
Mind
z
eCos
Copyright © 2007. Avnet, Inc. All rights reserved.
To Find Out More….
45
Enabling success from the center of technology™
MicroBlaze Processing Solutions
– Visit www.xilinx.com/microblaze for more information
Xilinx Embedded Magazine
– Latest Issue – Endless Possibilities (April 2006)
On the web at Xilinx.com
– Xilinx Processor Central site
•
–
Xilinx Embedded Development Kit, Platform Studio Tools
•
–
www.xilinx.com/xds/index.htm
Xilinx and Partner Boards (Reference, Development,
Eval)
•
–
xilinx.com/XPS
Xilinx Design Services
•
–
www.xilinx.com/products/design_resources/proc_central/index.htm
www.xilinx.com/xlnx/xebiz/board_search.jsp
Xilinx Online Store
•
ww.xilinx.com/xlnx/xebiz/onlinestore.jsp?sGlobalNavPick=PURCHASE
Comprehensive Embedded Services
– Embedded Systems Development Course (2-Day
Course)
•
–
–
Effectively develop, debug, and simulate an embedded system
On-Site Xilinx Embedded Design Specialist
Award-Winning Technical Support
•
•
•
Customer Hotline Support
MySupport.xilinx.com
Embedded Processor Forum and Tech Tips
Copyright © 2007. Avnet, Inc. All rights reserved.
46
Agenda
Enabling success from the center of technology™
Advantages of using Xilinx embedded processors
Design flow overview
Demo 1 – Creating a design
Processor options
Understanding the development environment
Demo 2 – Running the design
Copyright © 2007. Avnet, Inc. All rights reserved.
47
Tool Summary
Enabling success from the center of technology™
Xilinx
Platform
Studio
(XPS)
Base System Builder (BSB) Wizard
Generate Bitstream
Build All User
Applications
.bit File
Download Bitstream
.elf File
Launch XMD
Copyright © 2007. Avnet, Inc. All rights reserved.
48
What’s Next?
Enabling success from the center of technology™
Contact your local FAE for more information
Get Xilinx tools
– ISE WebPack can be downloaded free
– EDK is often bundled with Avnet development boards
during Avnet Speedway promotion
Get a development board
Create your own embedded processor design!
– Attend Avnet Speedway workshop for a quick start
Copyright © 2007. Avnet, Inc. All rights reserved.
Appendix
49
Enabling success from the center of technology™
Copyright © 2007. Avnet, Inc. All rights reserved.
50
UltraController-II
Enabling success from the center of technology™
Easy to use HDL module
sys_clk
Interrupt
sys_rst_out
JTAG
JJ
TT
AA
GG
gpio_in
DSOCM
DSOCM
sys_rst
PowerPC 405
ISOCM
ISOCM
RR
ee
ss
ee
tt
I-Cache
D-Cache
gpio_out
Fabric
FPGAFPGA
Fabric
Code Loaded
and stored
in Cache
Simple processor/fabric interface
uses minimal FPGA resources
Up to:
– 450 MHz
– 700+ DMIPS
Only
– 0.29
mW/MHz
– 10 Logic
Cells
High Performance Small Footprint Controller
Copyright © 2007. Avnet, Inc. All rights reserved.
UltraController-II Module
51
Enabling success from the center of technology™
PowerPC 405 core and Tri-mode Ethernet MAC (XAPP 807)
Virtex-4 FX Reference Design
– Utilizes Integrated PPC
– Integrated EMAC
Advantages
– Low resource utilization
– <1% of Virtex-4 FX12
– Supports up to 90Mb/s
(non TCP/IP)
Applications
– Lightweight web server
– Monitor and/or influence the system status
– Replace legacy RS-232 serial interface
Copyright © 2007. Avnet, Inc. All rights reserved.
52
Customer Success Stories
Enabling success from the center of technology™
CPLD
Microblaze
DLMB
BRAM
ILMB
Competition: NIOS, Motorola
Needs:
– Reduce cost
– Integrate custom mix of standard peripherals
and own IP/logic
Initial Concerns:
– Performance of Xilinx SDRAM controller
– No “wake” and “sleep” features in Xilinx
solution.
Solution:
– Worked with field to find cost point- XC3S400
– Built FSL-based SDRAM controller
– XDS Dublin built “wake” and “sleep” func.
– OPB used to connect mix of standard IPs
– XC3S400
– MicroBlaze core at about 65MHz
FLASH
FLASH
Mem. Ctl
User
Logic
SDRAM
OPB
UART
2X Timers
Int. Ctl
SDRAM
Mem. Ctl
Ethernet
Lite
GPIO
MicroBlaze processor sub-system
HDLCU
BSII
CRCU
DSP MUX
LCU
XC3S400
Application: GSM/G3 Base Station
Copyright © 2007. Avnet, Inc. All rights reserved.
DSP
53
Customer Success Stories
Enabling success from the center of technology™
Application: Home/Enterprise Security Systems
Competition: Freescale
Needs:
– Replace off-the-shelf DragonBall processor (at end-of-life stage)
•
•
•
•
–
–
–
–
OTS fixed processors is an in-exact fit to the target application
OTS processors can become obsolete
Configurable soft processor, flexibility to tailor mix of IPs
RTOS
XC3S400 and XC3S1000
RTOS: uCLinux
Prototype: Q4-2005
3-platforms for 3 year production
Microblaze
DLMB
After this win, replaced perfectly good (shipping) Coldfire too!
– Moderate CPU performance
– Flexibility to integrate custom and standard IPs per project
– Re-use peripherals for other projects
– uCLinux
Initial Concerns:
– No FPGA experience
– Un-familiar with soft-processor solution
Solution:
– Deciding factor:
ILMB
•
BRAM
FLASH
User
Logic
OPB
UART
Lite
UART
16550
UART
Lite
SDRAM
10/100
Ethernet
MicroBlaze processor sub-system
Custom IP
Custom IP
XC3S400
Check out http://www.xilinx.com/prs_rls/silicon_spart/05117ge_security.htm
and Embedded Magazine for ESC April/06
Copyright © 2007. Avnet, Inc. All rights reserved.
Custom IP
GPIO
32 Bit
