Overview of Chapter 4
Developing the State Diagram
ƒ Types of Sequential Circuits
ƒ Storage Elements
ƒ A state is an abstraction of the history of the past
applied inputs to the circuit (including the “null” input
at power-up or reset).
ƒ Latches
ƒ Flip-Flops
• The interpretation of “past inputs” is tied to the synchronous
operation of the circuit. E. g., an input value is measured
only during the setup-hold time interval for an edge-triggered
flip-flop.
ƒ Sequential Circuit Analysis
ƒ State Tables
ƒ State Diagrams
ƒ Examples:
ƒ Sequential Circuit Design
ƒ
ƒ
ƒ
ƒ
• State A represents the fact that a 1 input has occurred
among the past inputs.
Specification
Assignment of State Codes
Implementation
HDL Representation
• State B represents the fact that a 0 immediately followed by
a 1 has occurred among the most recent past two inputs.
1
Developing the State Diagram(Continued)
2
Sequence Recognizer Procedure
ƒ To develop a sequence recognizer state diagram:
ƒ In specifying a circuit, we use states to remember
meaningful properties of past input sequences that
are essential to predicting future output values.
• Begin in an initial state in which NONE of the initial portion of
the sequence has occurred (typically “reset” state).
• Add a state that recognizes that the first symbol has
occurred.
• Add states that recognize each successive symbol
occurring.
• The final state represents the input sequence (possibly less
the final input value) occurence.
• Add state transition arcs which specify what happens when a
symbol not in the proper sequence has occurred.
• Add other arcs on non-sequence inputs which transition to
states that represent the input subsequence that has
occurred.
ƒ The last step is required because the circuit must recognize the
input sequence regardless of where it occurs within the overall
sequence applied since “reset.”.
ƒ A sequence recognizer is a sequential circuit that
produces a distinct output value whenever a
prescribed pattern of input symbols occur in
sequence, i.e, recognizes an input sequence
occurence.
ƒ We will develop a procedure specific to sequence
recognizers to convert a problem statement into a
state diagram.
ƒ Next, the state diagram, will be converted to a state
table from which the circuit will be designed.
3
4
Sequence Recognizer Example
Example: Recognize 1101
ƒ Example: Recognize the sequence 1101
ƒ Define states for the sequence to be recognized:
• assuming it starts with first symbol,
• continues through each symbol in the sequence to be
recognized, and
• uses output 1 to mean the full sequence has occurred,
• with output 0 otherwise.
• Note that the sequence 1111101 contains 1101 and "11" is a
proper sub-sequence of the sequence.
ƒ Thus, the sequential machine must remember that
the first two one's have occurred as it receives
another symbol.
ƒ Starting in the initial state (Arbitrarily named "A"):
ƒ Also, the sequence 1101101 contains 1101 as both
an initial subsequence and a final subsequence with
some overlap, i. e., 1101101 or 1101101.
1/0
• Add a state that
A
B
recognizes the first "1."
• State "A" is the initial state, and state "B" is the state which
represents the fact that the "first" one in the input
subsequence has occurred. The output symbol "0" means
that the full recognized sequence has not yet occurred.
ƒ And, the 1 in the middle, 1101101, is in both
subsequences.
ƒ The sequence 1101 must be recognized each time it
occurs in the input sequence.
5
6
1
Recognize 1101 (Continued)
Recognize 1101 (Continued)
ƒ After one more 1, we have:
• C is the state obtained
when the input sequence
has two "1"s.
A
1/0
A
1/0
B
1/0
B
1/0
0/0
C
D
B
1/0
0/0
C
1/1
D
ƒ Clearly the final 1 in the recognized sequence 1101 is
a sub-sequence of 1101. It follows a 0 which is not a
sub-sequence of 1101. Thus it should represent the
same state reached from the initial state after a first 1
is observed. We obtain:
C
ƒ Finally, after 110 and a 1, we have:
A
1/0
1/1
• Transition arcs are used to denote the output function (Mealy Model)
• Output 1 on the arc from D means the sequence has been
recognized
• To what state should the arc from state D go? Remember: 1101101
A
?
1/0
1/0
B
C
• Note that D is the last state but the output 1 occurs for the input
applied in D. This is the case when a Mealy model is assumed.
0/0
D
1/1
7
Recognize 1101 (Continued)
A
1/0
1/0
B
Complete the Diagram (1101)
0/0
C
8
ƒ The other arcs are added to each state for
inputs not yet listed. Which arcs are missing?
D
1/1
ƒ The state have the following abstract
meanings:
A
• A: No proper sub-sequence of the sequence has
occurred.
• B: The sub-sequence 1 has occurred.
• C: The sub-sequence 11 has occurred.
• D: The sub-sequence 110 has occurred.
• The 1/1 on the arc from D to B means that the last
1 has occurred and thus, the sequence is
recognized.
B
1/0
0/0
C
ƒ Answer:
"0" arc from A
"0" arc from B
"1" arc from C
"0" arc from D.
D
1/1
9
Add Missing Arcs
10
1101 State Table from Diagram
ƒ State transition arcs must represent the fact
that an input subsequence has occurred.
Thus we get:
0/0
A
1/0
ƒ From the State Diagram, we can fill in the State
0/0
1/0
Table.
ƒ There are 4 states, one
input, and one output.
We will choose the form
with four rows, one for
each current state.
1/0
1/0
B
1/0
0/0
C
0/0
D
1/1
ƒ From State A, the 0 and
1 input transitions have
been filled in along with
the outputs.
0/0
ƒ Note that the 1 arc from state C to state C
implies that State C means two or more 1's
have occurred.
11
A
1/0
B
1/0
0/0
C
0/0
D
1/1
0/0
Present
State
A
B
C
D
Next State
x=0 x=1
A B
Output
x=0 x=1
0
0
12
2
Complete 1101 State Table
Moore Model for 1101
ƒ For the Moore Model, outputs are associated
with states.
ƒ From the state diagram, we complete the
state table.
0/0
1/0
A
1/0
1/0
B
0/0
Present
State
A
B
C
D
Next State
x=0 x=1
A
B
A
C
D
C
A
B
Output
x=0 x=1
0
0
0
0
0
0
0
1
C
0/0
ƒ We need to add a state "E" with output value 1
for the final 1 in the recognized input sequence.
D
1/1
• This new state E, though similar to B, would generate
an output of 1 and thus be different from B.
0/0
ƒ The Moore model for a sequence recognizer
usually has more states than the Mealy model.
ƒ What would the state diagram and state table
look like for the Moore model?
13
Moore State Table for 1101
Moore Diagram for 1101 (Cont.)
1
0
ƒ We mark outputs on
0
states for Moore model
1
1
A/0
B/0
C/0
ƒ Arcs now show only
state transitions
0
1
1
ƒ Add a new state E to
0
E/1
produce the output 1
ƒ Note that the new state,
0
E produces the same behavior
in the future as state B. But it gives a different output
at the present time. Thus these states do represent a
14
D/0
ƒ The state table is shown
below
ƒ Memory aid re more
state in the Moore model:
“Moore is More.”
0
A/0
1
1
1
B/0
0
C/0
1
0
0
D/0
1
E/1
0
Present
State
A
B
C
D
E
different abstraction of the input history.
Next State
x=0 x=1
A
B
A
C
D
C
A
E
A
C
Output
y
0
0
0
0
1
15
16
Second State Diagram Example
Parallel Load Register with Synchronous Clear and
Load
ƒ A register consists of an ordered set of n flipflops plus combinational logic to determine its
next state.
ƒ If a register can be designed as a set of n
identical cells, the register cell can be
designed as a two-state sequential circuit.
ƒ Register Specification
ƒ Diagram:
CLS
LDS
CLK
ƒ Table:
Data_in (7:0)
Register(7:0)
RESET
(Async)
Data_out(7:0)
17
Operation
CLS
LDS
Result (Next State)
Hold Reg
0
0
Data_out
Load Reg
0
1
Data_in
Clear Reg
1
X
0000000
18
3
Second Example: Register Cell Design
Second Example: State Diagram Design
ƒ By definition, a register cell is a sequential
circuit that:
ƒ Initial State:
• contains one flip-flop (2 states)
• has the flip-flop output as the primary external
register output (Moore model)
LDS,Data_in
RESET
1, 1
A/0
B/1
1, 0
Data_in (i)
Reg. Cell(i)
1, 0 State/Data_out(i)
ƒ Add Load:
ƒ Cell Diagram:
CLS
LDS
A/0
RESET
ƒ Add Clear:
CLS,LDS,Data_in
RESET
FF
CLK
Data_out(i)
RESET
(Async)
0, 1, 0; 1, -, -
1, 1
State/Data_out(i)
0, 1, 1
A/0
B/1
0,1,0; 1,-,-
0,1,1
19
20
Second Example: State Diagram Design
Second Example: State Table
ƒ Make the state unchanged (Hold Reg) by
adding all unused input combinations for
each state.
ƒ From State Diagram: CLS, LDS, Data_in
CLS,LDS,Data_in
RESET
A/0
0, 1, 0; 1, -, State/Data_out(i)
0, 1,
B/1
1
0,1,0; 1,-,-;
0,0,-
Input:
State:
000
001
010
011
100
101
110
111
Output
A
A
A
A
B
A
A
A
A
0
B
B
B
A
B
A
A
A
A
1
0,1,1;
0,0,21
Sequential Circuit Implementation
Overview of Chapter 4
ƒ For the design of a sequential circuit, we need to:
ƒ Types of Sequential Circuits
ƒ Storage Elements
• Implement the Next State Function, and
• Implement the Output Function.
ƒ Latches
ƒ Flip-Flops
ƒ For the Next State Function, we need to:
• Assign binary variable values to states,
• Select a flip-flop type (or types) for binary state variable storage,
and
• Write the next state function in terms of flip-flop input excitation
equations.
ƒ Sequential Circuit Analysis
ƒ State Tables
ƒ State Diagrams
ƒ Sequential Circuit Design
ƒ
ƒ
ƒ
ƒ
22
ƒ For the Output Function, we need combinational
Boolean equation(s) from:
Specification
Assignment of State Codes
Implementation
HDL Representation
• States to Outputs (Moore) or
• States and Inputs to Outputs (Mealy).
23
24
4
State Coding – Example 1
Present Next State
State
x=0 x=1
A
A
B
B
A
B
State Coding – Example 2
Output
x=0 x=1
0
0
0
1
Present
State
A
B
C
D
ƒ How may assignments of codes with a
minimum number of bits?
Next State
x=0 x=1
A
B
A
C
D
C
A
B
Output
x=0 x=1
0
0
0
0
0
0
0
1
ƒ How may assignments of codes with a
minimum number of bits?
• Two – A = 0, B = 1 or A = 1, B = 0
ƒ Does it make a difference?
• 4 × 3 × 2 × 1 = 24
ƒ Does code assignment make a difference?
• Only in variable inversion, so small, if any.
• See Next Two Slides
25
State Coding – Example 2
State Coding – Example 2 (Cont.)
Present Next State
State x = 0 x = 1
00
00
01
01
00
10
10
11
10
11
00
01
Output
x=0x=1
0
0
0
0
0
0
0
26
Present Next State
State x = 0 x = 1
00
00
01
01
00
11
11
10
11
1
10
ƒ Code 1: A = 0 0, B = 0 1, C = 1 0, D = 1 1
• Y 1( t + 1) = Y 1 Y 2 + x Y 1 Y 2
• Y 2( t + 1) = x Y 1 Y 2 + x Y 1 Y 2 + x Y 1 Y 2
ƒ See Next Slide
00
01
Output
x=0x=1
0
0
0
0
0
0
0
1
ƒ Code 2: A = 0 0, B = 0 1, C = 1 1, D = 1 0
• Y 1( t + 1) = Y 1 Y 2 + x Y 2
• Y 2( t + 1) = x
ƒ So it does make a difference in cost!
27
Implementation
Implementation with DFF
Present Next State
State x = 0 x = 1
00
00
01
01
00
11
11
10
11
10
00
01
Output
x=0x=1
0
0
0
0
0
0
0
Present Next State
State x = 0 x = 1
00
00
01
01
00
11
11
10
11
1
10
ƒ Using code 2:
• Y 1( t + 1) = Y 1 Y 2 + x Y 2
• Y 2( t + 1) = x
•
28
00
01
DFFY1
x=0x=1
0
0
0
1
1
1
0
0
DFFY2
x=0x=1
0
1
0
1
0
1
0
1
ƒ Using D = Q(t+1):
• D Y 1 = Y1 Y 2 + x Y 2
• DY 2 = x
• y = x Y1 Y 2
y = x Y1 Y 2
29
30
5
DFF Schematic
Implementation with TFF
D
Y1
x
C
y
10
D
CLK
TFFY1
x=0x=1
0
0
0
1
0
0
Present Next State
State x = 0 x = 1
00
00
01
01
00
11
11
10
11
Y2
00
1
01
TFFY2
x=0x=1
0
1
1
0
1
0
1
0
1
ƒ From Q(t+1) = T ⊕ Q(t), we can write T = Q(t) ⊕
Q(t+1)
• TY 1 = x Y 1 Y 2 + Y 1 Y 2
• TY 2 = x Y 2 + x Y 2
• y = x Y1 Y 2
C
RESET
31
Implementation with JKFF
Implementation with JKFF (Cont.)
ƒ Rearranging gives the compact JK Excitation
Table:
ƒ Recall the J-K Flip Flop Characteristic Table:
Q(t)
0
0
0
0
1
1
1
1
J
0
0
1
1
0
1
0
1
K
0
1
0
1
1
1
0
0
Q(t+1)
0
0
1
1
0
0
1
1
Hold
Clear
Set
Toggle
Clear
Toggle
Hold
Set
32
From this table we can write:
Q( t + 1) = J( t ) Q( t ) + K ( t ) Q( t )
We can also derive a compact
characteristic table:
Q(t)
J
K
Q(t+1)
0
0
1
0
1
X
X
X
1
0
1
0
1
X
0
1
Hold or Clear
Set or Toggle
Clear or
Toggle
Hold or Set
Q(t)
Q(t+1)
J
K
Comment
0
0
1
1
0
1
0
1
0
1
X
X
X
X
1
0
Hold or Clear
Set or Toggle
Clear or Toggle
Hold or Set
ƒ This compact JK Excitation Table can be applied
to the state transition table to obtain the required
J and K inputs.
ƒ For each possible state transition pair, we map to
values of J and K from the table above.
33
Sequential Logic Design Process
Implementation with JKFF (Cont.)
Present
State
Next State
x=0x=1
JY1
x=0x=1
34
1. Word description
2. State table or State diagram
3. Reduced state table (not covered)
4. Code Assignment (State, Input, Output)
5. Choose flip-flop types
6. Derive output function(s)
7. Derive excitation functions
8. Draw the logic diagram
KY1
x=0x=1
00
00
01
0
0
X
X
01
00
11
0
1
X
X
11
10
11
X
X
0
0
10
00
01
X
X
1
1
• J Y 1 = X ×Y 2
• K Y1 = Y 2
35
36
6
Second Example – Register File Cell:
State Diagram Design
Second Example – Register File Cell:
State Table – State Assignment (A=0, B=1)
ƒ Make the state unchanged (Hold Reg) by adding all
unused input combinations for each state.
CLS,LDS,Data_in
B
State/Data_out(i)
0, 1, 0; 1, -, 0, 1, 1
A/0
RESET
Input:
State:
A
Input:
State:
0
B/1
0,1,1; 0,0,-
0,1,0; 1,-,-; 0,0,-
1
000 001 010 011 100 101 110
111
Output
A
A
A
B
A
A
A
A
0
B
B
A
B
A
A
A
A
1
111
Output
000 001 010 011 100 101 110
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
1
37
38
DFF Implementation
JKFF Implementation
ƒ Moving state table data to a K-Map and
solving:
LDS
ƒ Moving state table data to a K-Map
LDS
and solving:
0
0
1
0
0
0
0
0
0
Q
1
0
1
0
0
1
0
JQ
CLS
Q
Data_in
LDS
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
Data_in
D Q = CLS LDS Q + CLS LDS Data _ in
JQ = CLS LDS Data _ in
39
KQ
CLS
Q
X
X
X
X
X
X
X
X
1
1
1
1
0
0
1
0
CLS
Data_in
K Q = CLS + LDS Data _ in
40
Review: Excitation Tables
JK-FF Excitation Table
Q(t)
Q(t+1)
J
K
Comment
0
0
0
X
Hold or Clear
D-FF Excitation Table
Q(t)
Q(t+1)
D
0
0
0
Clear
Comment
0
1
1
X
Set or Toggle
0
1
1
Set
1
0
X
1
Clear or
Toggle
1
0
0
Clear
1
1
1
Set
1
1
X
0
Hold or Set
T-FF Excitation Table
RS-FF Excitation Table
Q(t)
Q(t+1)
T
Comment
0
0
0
Hold
X
Hold or Clear
0
1
1
Toggle
0
Set
1
0
1
Toggle
0
1
Clear
1
1
0
Hold
X
0
Hold orSet
Q(t)
Q(t+1)
S
R
0
0
0
0
1
1
1
0
1
1
Comment
41
7