8086 Internal Block diagram (Intel Corp.)
eNotes
By
Prof. S. Jagannathan,
HOD – Department of Electronics and
Communication Engineering,
R.V. College of Engineering, Bangalore
Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore
Session - III
ADVANCED MICROPROCESSORS
Contents
•
Block Diagram of 8086
•
segment registers
•
8086 flag register format
8086 Internal Block diagram (Intel Corp.)
The block diagram of 8086 is as shown. This can be subdivided into two parts, namely
the Bus Interface Unit and Execution Unit. The Bus Interface Unit consists of segment
registers, adder to generate 20 bit address and instruction prefetch queue.
Once this address is sent out of BIU, the instruction and data bytes are fetched from
memory and they fill a First In First Out 6 byte queue.
Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore
Execution Unit:
The execution unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX
and pointers like SP (Stack Pointer), BP (Base Pointer) and finally index registers such as
source index and destination index registers. The 16-bit scratch pad registers can be split
into two 8-bit registers. For example, AX can be split into AH and AL registers. The
segment registers and their default offsets are given below.
Segment Register
Default Offset
CS
IP (Instruction Pointer)
DS
SI, DI
SS
SP, BP
ES
DI
The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The
results of these operations can affect the condition flags.
Different registers and their operations are listed below:
Register
Operations
AX
Word multiply, Word divide, word I/O
AL
Byte Multiply, Byte Divide, Byte I/O, translate, Decimal Arithmetic
AH
Byte Multiply, Byte Divide
BX
Translate
CX
String Operations, Loops
CL
Variable Shift and Rotate
DX
Word Multiply, word Divide, Indirect I/O
Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore
8086/8088 MPU
IP
Instruction Pointer
CS
Code Segment Register
DS
Data Segment Register
SS
Stack Segment Register
ES
Extra Segment Register
AX
AH
AL
BX
BE
BL
CX
CE
CL
DX
DH
DL
SP
Stack Pointer Register
BP
Break Pointer Register
SI
Source Index Register
DI
Destination Index Register
SR
Status Register
MEMORY
00000016
Code Segment (64Kb)
Data Segment (64Kb)
Stack Segment (64Kb)
Extra Segment (64Kb)
Generation of 20-bit Physical Address:
Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore
FFFFF16
LOGICAL ADDRESS
SEGMENT REGISTER
0000
ADDER
20 BIT PHYSICAL MEMORY ADDRESS
Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore
8086 flag register format
BIT
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
U
U
U
U
0F
DF
IF
TF
SF
ZF
U
AF
U
PF
U
CF
U= UNDEFINED
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
: CARRY FLAG – SET BY CARRY OUT OF MSB
: PARITY FLAG – SET IF RESULT HAS EVEN PARITY
: AUXILIARY CARRY FLAG FOR BCD
: ZERO FLAG – SET IF RESULT = 0
: SIGN FLAG = MSB OF RESULT
: SINGLE STEP TRAP FLAG
: INTERRUPT ENABLE FLAG
: STRING DIRECTION FLAG
: OVERFLOW FLAG
There are three internal buses, namely A bus, B bus and C bus, which interconnect the
various blocks inside 8086.
The execution of instruction in 8086 is as follows:
The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and
fetches the first instruction of a program from the memory. Subsequent addresses are sent
Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore
out and the queue is filled upto 6 bytes. The instructions are decoded and further data (if
necessary) are fetched from memory. After the execution of the instruction, the results
may go back to memory or to the output peripheral devices as the case may be.
Prof. S. Jagannathan,HOD – Dept of E & C Engg,R.V. C. E, Bangalore