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Controllers and Interface Peripherals
A broad range of controllers and peripherals have been integrated in System-on-Chip (SoC)
circuits by CSEM. These blocks are available for reuse in future systems to reduce the cost
and time to market of future ASICs. This document lists the blocks most often used.
Controllers
Direct memory access (DMA) controllers unburden the
processor from tedious data move operations between
memories and/or peripherals. Interrupt requests which
might hinder real time processing can be avoided. The
DMA is also often used during the ROM boot sequence.
CSEM DMAs support 4 prioritized channels, autobuffering, 1D and 2D accesses, byte packing and
unpacking, and the chaining of DMA operations.
The request controller collects event signals from any
other block and forwards it to a DMA controller (request) or
to a processor (interrupt). Output requests can be masked,
prioritized and vectorized.
The joint test action group (JTAG) IEEE Std 1149.1
controller is used for test and debug purposes. It forces
values on selected internal signals and/or pushes internal
values out while in test mode. The icyflex processors use
the JTAG interface for on-chip debug and for memory built
in self test (MBIST).
Interface Peripherals
The inter-IC (I2C) bus is a multi-master 2-wire serial bus.
The CSEM I2C interface supports both master and slave
modes and can operate with external master devices
running in standard (100 kb/s) or fast (400 kb/s) modes.
The serial peripheral interface (SPI) bus is a full-duplex
point-to-point 4-wire serial bus. The CSEM SPI interface
has input and output FIFOs and supports both master and
slave mode, at a maximum baud rate of respectively 50%
and 25% of its clock frequency.
The inter-IC sound (I2S) bus is a 3-wire serial bus
designed for audio applications which require a low jitter.
The CSEM I2S interface has input and output FIFOs and
supports variable data lengths (up to 32 bits), master and
slave modes, at a maximum baud rate of respectively 50%
and 25% of its clock frequency.
The universal asynchronous receiver/transmitter (UART) is
an asynchronous serial bus interface. The CSEM UART
interface has input and output FIFOs and supports the RS232 standard with a 2-wire (RX, TX) implementation.
Figure 1 Sample block diagram of a digital SoC
Controllers and Interface Peripherals
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CSEM’s parallel peripheral interface (PPI) bus is a
synchronous or asynchronous parallel bus which supports
a customizable data width. It uses N data wires plus 2
control wires. It has input and output FIFOs and supports
master and slave modes and can run at a maximum of
100% and 25% of its clock frequency respectively in
synchronous and asynchronous (slave) mode.
CSEM’s general purpose input/output (GPIO) interface
supports a customizable amount of single bit IOs, with
debounce digital filters on the inputs. The input signals can
be mapped to interrupt signals.
CSEM’s interface for single data rate (SDR) synchronous
dynamic random access memory (SDRAM) is compatible
with industry standard SDR SDRAM chips. It supports
customizable address and data widths, as well as many
timing configurations.
Other Digital Blocks
The CSEM timer supports three modes: counting signal
edges, measuring the duration of a signal state with
respect to a reference clock, and generating a pulse width
modulation (PWM) signal. The CSEM digital watchdog
detects the absence of its re-initialization during a
programmable duration with respect to a reference clock.
The watchdog’s registers are protected by a lock
mechanism to avoid accidental re- initializations. The timer
and watchdog use 32-bit registers.
The CSEM real-time clock (RTC) block keeps track of the
current time (in second, minute, hour, day format) by using
a 32 kiHz clock from a crystal oscillator. It can generate an
event signal at a programmable time. In can also
timestamp selected event signals. The CSEM RTC is
designed for ultra-low power consumption since it is often
the only block to run when a SoC is in standby mode.
The memory built in self test (MBIST) block helps test the
RAM in a circuit in less time and at a reduced cost. The
CSEM MBIST block is based on the 11-operation March C
algorithm.
The adaptive encryption standard (AES) block performs
strong encryption and decryption using a symmetric key.
Reusable building blocks for low-power SoC design
CSEM also designs ultra-low-power processors, static
random access memories (SRAM), standard cell libraries
and analog blocks, which are described in separate
documents. All these reusable blocks compose a coherent
library of reusable IP for advanced SoC designs with ultralow power consumption.
Controllers and Interface Peripherals
© CSEM
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