Chapter 5
The Inverter
V1. April 10, 03
V1.1 April 25, 03
V2.1 Nov.12 03
Inverter
Objective of This Chapter
‰ Use
Inverter to know basic CMOS
Circuits Operations
‰ Watch for performance Index such as
ƒ Speed (Delay calculation)
ƒ Optimal Transistor Sizing for speed and
Energy
ƒ Power Consumption and Dissipation
Inverter
The CMOS Inverter: A First Glance
V DD
V in
V out
CL
Inverter
CMOS Inverter
N Well
VDD
VDD
PMOS
Contacts
PMOS
In
Out
In
NMOS
Out
Metal 1
Polysilicon
NMOS
GND
A=WxL
Inverter
Two Inverters
Share power and ground
Abut cells
VDD
Vin
Connect in Metal
Vout
Vout
Vin
Inverter
CMOS Inverter
First-Order DC Analysis
V DD
V DD
Rp
V out
V out
VOL = 0
VOH = VDD
Rn
V in = V DD
V in = 0
Inverter
Delay Definitions (circuit speed)
V in
50%
t
V out
tpHL
tpLH
90%
50%
t
10%
tf
tr
Inverter
CMOS Inverter: Transient Response
V DD
V DD
tpHL = f(Ron.CL)
Rp
= 0.69 RonCL
V out
V out
CL
ln(2)=0.69
CL
Rn
V in = 0
V in = V DD
(a) Low-to-high
(b) High-to-low
Inverter
Voltage Transfer
Characteristic
Inverter
(Vdd = 2.5V in 0.25um CMOS Process)
(Vt = 0.4V as shown in Table 3-2)
PMOS Load Lines
IDn
Vin = VDD +V GS , p
I D ,n = − I D , p
Vout = VDD +V DS , p
IDp
Vout
Vin=0
IDn
IDn
Vin=1.5
VGSp=-1
V
DS,p
Vin=0
Vin=1.5
V
DS,p
V
out
VGSp=-2.5
Vin = VDD +V GS , p
I D ,n = − I D , p
Vout = VDD +V DS , p
Inverter
CMOS Inverter Load Characteristics
IDn
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
Vin = 1.5
Vin = 1.5
Vin = 2
Vin = 2.5
NMOS
Vin = 1
Vin = 1.5
Vin = 1
Vin = 0.5
Vin = 0
Vout
Inverter
CMOS Inverter VTC
NMOS off
PMOS res
2.5
Vout
2
NMOS s at
PMOS res
VM: Vin = Vout
Switching Threshold
Voltage
1
1.5
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0.5
1
1.5
2
NMOS res
PMOS off
2.5
V in
Inverter
Switching Threshold as a Function of
Transistor Ratio
NMOS and PMOS are in Saturation Modes
VM ≈
rVDD
( when
1+ r
VDD >> VDSAT , VTn , VTp )
For r = 1, and saturated velocity NMOS = 2 PMOS, Wp = 2Wn
Inverter
Switching Threshold as a Function of
Transistor Ratio
1.8
1.7
1.6
1.5
M
V (V)
1.4
1.3
1.2
1.1
1
2
0.9
0.8
10
3 4
0
10
W /W
p
1
n
Inverter
Simulated VTC
2 .5
2
V
out
(V )
1 .5
1
0 .5
0
0
0 .5
1
1 .5
V
in
2
2 .5
(V )
Inverter
Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
Good definition: Smaller oxide thickness, smaller L, higher W, smaller VT
Inverter
Propagation Delay
Inverter
CMOS Inverters
VDD
PMOS
1.2µm
=2λ
In
Out
Metal1
Polysilicon
NMOS
GND
Inverter
CMOS Inverter Propagation Delay
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
CL
Ron
ln(0.5)
Vout
1
VDD
0.5
0.36
Vin = V DD
RonCL
t
Inverter
The Transistor as a Switch
VG S ≥ V T
S
Ron
D
ID
V GS = VD D
Rmid
R0
V DS
VDD/2
VDD
Inverter
The Transistor as a Switch
7
x 10
5
6
4
eq
(O h m )
5
R
3
2
1
0
0 .5
1
1 .5
V
DD
2
2 .5
(V )
Inverter
The Transistor as a Switch
Inverter
Transient Response
3
?
2 .5
2
(V )
out
V
tp = 0.69 CL (Reqn+Reqp)/2
1 .5
1
tpHL
tpLH
0 .5
0
-0 . 5
0
0 .5
1
1 .5
t (s e c )
2
2 .5
x 10
-10
Inverter
Delay (speed degrade) as a function of VDD
5 .5
5
4 .5
p
t (n o rm a liz e d )
4
when VDD >> VTn + VDSATn / 2
3 .5
3
t pHL ≈ 0.52
2 .5
CL
(W / L)k n' VDSATn
2
1 .5
1
0 .8
1
1 .2
1 .4
1 .6
V
DD
1 .8
2
2 .2
2 .4
Similar to Rn curve!
Sharp change at 2Vt
(V )
Inverter
Design for Speed Performance
‰ Keep
loading capacitances (CL) small
‰ Increase transistor ratio (W/L) (adding
CMOS gain)
ƒ Watch out for self-loading (for the previous
stage)!
‰ Increase
Vdd! Æ Trade power/energy
dissipation for performance!
Inverter
Propagation delay v.s. Transistor size
‰
NMOS-to-PMOS Ratio:
ƒ Symmetrical tpHL and tpLH Æ PMOS is 2.5~3.5
wider than NMOS in width under same L
ƒ Is there better propagation delay (tp), or a better
N-to-P ratio for overall tp can be found?
‰
Consider two identical cascaded CMOS inverters.
The approximated load cap of the 1st gate is
C L = (Cdp1 + Cdn1 ) + (C gp 2 + C gn 2 ) + CW
Cdp1 , Cdn1 Is drain capacitance of PMOS and NMOS of 1st stage
C gp 2 , C gn 2 Is gate capacitance of PMOS and NMOS of 2nd stage
Inverter
Propagation delay v.s. Transistor size
‰
When the PMOS device is made β times larger than the
(W / L)
=
β
NMOS
(W / L)
Cdp1 ≈ βCdn1 and C gp 2 ≈ βC gn 2
Then
‰
CL becomes CL = (1 + β )(Cdn1 + C gn 2 ) + CW
‰
From (5.20), we have
‰
p
n
tp =
Reqp
0.69
(1 + β )(Cdn1 + C gn 2 ) + CW ( Reqn +
)
β
2
[
]
[
]
= 0.345 (1 + β )(Cdn1 + C gn 2 ) + CW Reqn (1 +
where γ =
Reqp
Reqn
γ
)
β
is the resistance ratio of equal-size NMOS
and PMOS
Inverter
NMOS/PMOS ratio
5
x 10
-11
β = Wp/Wn
tpHL
tpLH
From Table 3.3
β= 31Κ/13Κ = 2.4
4 .5
4
p
t (s e c )
tp
β opt = γ (1 + (
3 .5
3
1.9
1
1 .5
2
CW
)
Cdn1 + C gn 2
when Cdn1 + C gn 2 >> CW
2 .5
3
3 .5
4
4 .5
5
β opt = γ
β
Fig. 5-18
Inverter
Inverter Sizing
Inverter
Inverter Chain
In
Out
1
f1
f2
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
Inverter
Notation Definition
•Unit-size NMOS Transistor: the NMOS with minimum
Lmin and Wmin that meets the layout design rule
(assume L is fixed, and W is varied)
• Cunit : Intrinsic Cap. of unit-size NMOS transistor
• Runit : Channel resistance of unit-size NMOS transistor
• C g : Gate cap of unit-size NMOS transistor
• RW : Channel resistance of W-sized NMOS transistor
• Cint : Self-loading or intrinsic cap of the inverter
(diffusion cap and gate-drain overlap (Miller) cap)
Inverter
Inverter Delay
• Minimum length devices, L=0.25µm
• Assume RP = 2RN and WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
2W
W
• Analyze as an RC network
tpLH = (ln 2) RPCL
Delay (D): tpHL = (ln 2) RNCL
 Wunit
RP = (2 Runit )
 WP
 Wunit

 ≈ Runit 

 WN
Load for the next stage:

 = RN = RW (R of unit size NMOS)

C gin
W
=3
Cunit
Wunit
Inverter
Inverter with Load
Delay
RP
RW
2W
W
CL
Load (CL)
tp = k RWCL
•k is a constant, equal to 0.69
•Assumptions: no load Æ zero delay
tpHL = (ln 2) RNCL
tpLH = (ln 2) RPCL
Inverter
Inverter with Load and Para. Cap.
CP = 2Cunit
Delay
2W
W
Cint
CL
CN = Cunit
Load
Delay = kRW (Cint + CL) = kRWCint + kRWCL
= Delay (Internal) + Delay (Load)
= kRW Cint(1+ CL /Cint)
Inverter
Delay Formula
Delay ~ RW (C int + C L )
t p = kR W C int (1 + C L / C int ) = t p 0 (1 + f / γ
)
Cint = γCg,in with γ ≈ 1
f = CL/Cg,in: Effective fanout
RW = Runit / W ; Cint =WCunit
tp0 = 0.69RunitCunit
(Intrinsic or unloaded delay)
Not function of transistor size!!
Inverter
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C gin , j +1 

t pj ~ Runit Cunit 1 +

 γC
gin
j
,


N
N 
C gin , j +1 
, C gin , N +1 = C L
t p = ∑ t p , j = t p 0 ∑ 1 +
 γC

j =1
i =1 
gin , j 
Inverter
Optimal Tapering for Given N
Delay equation has (N-1) unknowns, Cgin,2 ~ Cgin,N
Minimize the delay, find (N – 1) partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin , j = C gin , j −1C gin , j +1
- Each stage has the same effective fanout (Cout/Cin)
- Each stage has the same delay
Inverter
Optimum Delay and Number of Stages
When each stage is sized by f and has same effective
fanout f
f
N
= F = C L / C gin ,1
Effective fanout of each stage:
f =NF
Minimum path delay
(
t p = Nt p 0 1 + N F / γ
)
Inverter
Example
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f =38 =2
Inverter
Optimum Number of Stages
Given load, CL and given input capacitance Cin
Find optimal sizing f
C L = F ⋅ Cin = f Cin
N
t p = Nt p 0
(
ln F
with N =
ln f
)
t p 0 ln F  f
γ

F / γ +1 =
+
γ  ln f ln f
∂t p
t p 0 ln F ln f − 1 − γ f
=
⋅
=0
2
∂f
ln f
γ



f = exp(1 + γ f )
For γ = 0, f = e, N = lnF
Inverter
Optimum Effective Fanout f
f = exp(1 + γ f ) Æ fopt = 3.6 for γ=1, fopt = 2.718 for γ=0
Inverter
Normalized delay function of F
(
t p = Nt p 0 1 + N F / γ
)
Inverter
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
22.6
Without considering the internal capacitance
Inverter
Power Dissipation
Inverter
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Inverter
Dynamic Power Consumption
∞
EVDD
∞
∞
dv
2
= ∫ iVDD (t )VDD dt =VDD ∫ C L out dt =VDD C L ∫ dvout =C LVDD
dt
0
0
0
Inverter
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.
∞
∞
2
dvout
C LVDD
EC = ∫ iVDD (t )vout dt = ∫ C L
vout dt =
2
dt
0
0
Energy in CL
Inverter
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E
N
= C • V 2 • n (N )
L
dd
EN : the energy consumed for N clock cycles
n(N): the number of 0->1 transition in N clock cycles
EN
2
(N ) C
 lim n
P
= lim -------- • f
-----------V
=
•
•
• f clk
avg N
clk
dd


N
N
N→∞
L
→∞
α0
P
→1
=
n( N )
lim -----------N→∞ N
= α
C •V 2•f
•
avg
0→1
dd
clk
L
2
2
PAVG = (α 0→1 ⋅ C L ) ⋅ VDD
⋅ f CLK = C Eff ⋅ VDD
⋅ f CLK
(C Eff : Effective Capacitance)
Inverter
Switching Activity (Example 5.12)
α 0→1 = 2 / 8 = 0.25
Inverter
Transistor Sizing for Minimum Energy
‰
Goal: Minimize Energy of whole circuit while maintaining
the speed speed performance
ƒ Design parameters: f and VDD
ƒ tp ≤ tp,ref of referenced circuit with f=1 and Vdd =Vref
In
Out
Cg1
1
f
Cext

f 
F 
 
t p = t p 0  1 +  + 1 +
( F = Cext / C g1 )
fγ  
 γ  
VDD
t p0 ∝
(VTE = VT + VDSAT / 2)
VDD − VTE
Inverter
Transistor Sizing (2)
‰
Performance Constraint (γ=1) Æ Vdd(f)
tp
t pref
‰
=
t p0
t p 0 ref

F
 2 + f + 
f  VDD Vref − VTE

=
(3 + F )
Vref VDD − VTE

F
 2 + f + 
f 

=1
(3 + F )
Energy for single transition
2
2
E = VDD
C g1 [1 + γ + f + fγ + F ] = VDD
C g1[(1 + γ )(1 + f ) + F ]
‰
Energy ratio of the design and reference circuit
2
 VDD ( f )   2 + 2 f + F 
E
 
=



Eref  Vref   4 + F 
Inverter
Transistor Sizing (4)
VDD=f(f)
Required Supply Voltage
E/Eref=f(f)
Energy v.s. Sizing factor
Inverter
Sizing factor for Speed and Energy
‰
Device sizing, combined with supply voltage
reduction, is a very effective way in reducing energy
consumption of a logic network.
ƒ The gain can be up to 10 for large fanout.
‰
‰
Oversizing beyond the optimal value comes at a hefty
price in energy.
Optimal size for energy is smaller than the optimal
sizing for performance.
ƒ For example, f(energy) = 3.53, f(performance) = 4.47= 20 ,
for F=20
Inverter
Short Circuit Currents (during switching)
Vd d
Vin
Vout
CL
I V D D (m A)
0.15
0.10
0.05
0.0
1.0
2. 0
3.0
V in (V)
4.0
5 .0
Inverter
Minimizing Short-Circuit Power
Inverter
Neil Weste
Textbook
Inverter
Leakage Current
Sub-threshold current is one of most compelling issues
in low-energy circuit design!!
Pstat = I statVDD
Inverter
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS × A
JS = 10-100 pA/µm2 at 25 deg C for 0.25µm CMOS
JS doubles for every 9 deg C!
Inverter
Subthreshold Leakage Component
Inverter
Subthreshold Leakage Component (2)
Inverter
Putting All Together
Ptotal = Pdyna + Pdp + Pstat
2
= (C LVDD
+ VDD I peak t s ) f 0→1 + VDD I leak
•In a typical CMOS circuits, the capacitive
dissipation is by far the dominant factor.
•Leakage is ignorable at present, but will be
major issue in deep-submicron CMOS circuits.
Inverter
Principles for Power Reduction
‰
Prime choice: Reduce voltage!
ƒ Recent years have seen an acceleration in supply
voltage reduction
ƒ Design at very low voltages still open question
(0.6, … , 0.9 V by 2010!)
‰
Reduce switching activity (at different levels)
‰
Reduce physical capacitance
ƒ Device Sizing: for example, for F = 20
fopt(energy)=3.53, fopt(performance)=4.47.
Inverter
Power-Delay Product (PDP)
‰
PDP = Pav t p
‰ f max = 1 /( 2t p )
PDP = C V
2
L DD
‰
2
C LVDD
f max t p =
2
PDP stands for the average energy
consumed per switching event (0Æ 1, 1Æ 0)
Inverter
Energy-Delay Product (EDP)
‰
Measure of both Performance and Energy
2
C LVDD
‰ EDP = PDP × t p = P t =
tp
2
αC LVDD
‰
2
av p
tp ≈
VDD − VTE
‰ EDP =
‰
, VTE = VT + VDSAT / 2
3
αC L2VDD
2(VDD − VTE )
, VDD ,opt
3
= VTE
2
(5.21)
(5.59)
The value of supply voltage that simultaneously
optimizes performance and energy. For Vt=0.5V, the
VDD is around 1V.
Inverter
Energy-Delay Product (EDP)
VTn = 0.42V , VDsat ,n = 0.63V , VTE ,n = 0.74V
VTp = −0.4V , VDsat , p = −1V , VTE , p = −0.9V
VTE = (VTE ,n + VTE , p ) / 2 = 0.8V ⇒ VDD ,opt = (3 / 2) × 0.8V = 1.2V
Note:
Vdd for minimum EDP
May not be the
Optimal Vdd for a
given design problem
(speed contraint)
Inverter
Summary
Inverter Speed (delay), sizing, and power are
discussed.
‰ The concept can be extended to complex
gates in next chapter and future discussions
‰ Very important for the 1st-order
guess/approximation for designers in
considering power/area/speed of the target
CMOS circuits
‰
Inverter