EE247
Lecture 12
• Data Converters
– Data converter testing (continued)
• Measuring DNL & INL (continued)
– Servo-loop
– Code density testing (histogram testing)
• Dynamic tests
– Spectral testingÆ Reveals ADC errors associated with
dynamic behavior i.e. ADC performance as a function of
frequency
• Direct Discrete Fourier Transform (DFT) based
measurements utilizing sinusoidal signals
• DFT measurements including windowing
• Relationship between: DNL & SNR, INL & SFDR
• Effective number of bits (ENOB)
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 1
Histogram Testing
• Code boundary measurements are slow
(covered last lecture)
– Long testing time
• Histogram testing
– Apply input with known pdf (e.g. ramp or sinusoid)
& quantize
– Measure output pdf
– Derive INL and DNL from deviation of measured
pdf from expected result
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 2
Code Boundary Servo
Input
Digital
Code
i1
A
Good DVM
C1
VREF fS
A<B
Digital
Comp.
B
R2
ADC
A≥B
C2
i2
ADC
Output
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 3
Histogram Test Setup
VREF
fS
Ramp VREF
ADC
0
PC
Time
• Slow (wrt conversion time) linear ramp applied to ADC
• DNL derived directly from total number of occurrences of each
code @ the output of the ADC
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 4
A/D Histogram Test Using Ramp Signal
Digital Output
Example:
ADC
Input/Output
ADC sampling rate:
fs =100kHz Æ Ts=10μsec
1LSB =10mV
For 0.01LSB measurement
resolution:
Æn =100 samples/code
Analog
input
Æ Ramp duration per code:
=100x10μsec=1msec
n.Ts
Ramp
Æ Ramp slope: 10mV/msec
Time
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 5
Example:
Ramp slope: 10mV/msec
1LSB =10mV
Each ADC codeÆ1msec
Digital Output
A/D Histogram Test Using Ramp Signal
Analog
input
fs =100kHz Æ Ts=10μsec
n/fs
# of
Samples
Per code Time
Æn =100 samples/code
EECS 247 Lecture 12:
ADC
Input/Output
Data Converters- Testing
Ramp
Digital
Output
© 2009 H. K. Page 6
Ramp Histogram
Example: Ideal 3-Bit ADC
7
200
ADC characteristics
ideal converter
180
160
Code Count
Digital Output Code
6
5
4
3
140
120
100
80
2
60
1
40
0
20
0
1
2
3
4
5
6
ADC Input Voltage [Δ]
EECS 247 Lecture 12:
7
0
8
0
1
2
3
4
5
6
7
ADC output code
Data Converters- Testing
© 2009 H. K. Page 7
Ramp Histogram
Example: Real 3-Bit ADC Including Non-Idealities
7
180
160
6
-0.4 LSB DNL
140
5
Code Count
Digital Output Code
200
ADC characteristics
ideal converter
120
4
100
3
+0.4 LSB INL
2
80
60
1
40
+0.4 LSB DNL
20
0
0
1
2
3
4
5
6
ADC Input Voltage [Δ]
EECS 247 Lecture 12:
7
8
0
Data Converters- Testing
0
1
2
3
4
5
6
7
ADC output code
© 2009 H. K. Page 8
Example: 3 Bit ADC
1- Remove “Over-range bins”
(0 and full-scale)
2- Compute average count/bin
(600/6=100 in this case)
Code Count, End bins removed
DNL Extracted from Histogram
140
120
100
80
60
40
20
0
0
1
2
3
4
5
6
7
ADC output code
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 9
Example: 3 Bit ADC
Process of Extracting from Histogram
3- Normalize:
Divide histogram by
average count/bin
Æ ideal bins have exactly the
average count, which, after
normalization, would be 1
Æ Non-ideal bins would have
a normalized value greater of
smaller than 1
Normalized Code Count
-
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
ADC output code
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 10
4- Subtract 1 from the
normalized code count
5- Result Æ DNL (+-0.4LSB
in this case)
DNL = Counts / Mean(Counts) -1
Example: 3 Bit ADC
DNL Extracted from Histogram
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
0
1
2
3
4
5
6
7
ADC output code
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 11
Example: 3-Bit ADC
Static Characteristics Extracted from Histogram
• Width of all codes derived from
measured DNL (Code=DNL +
1LSB)
• INLÆ(deviation from a straight
line through the end points)- is
found
7
6
Digital Output
• DNL histogram Æ used to
reconstruct the exact converter
characteristic (having measured
only the histogram)
Reconstructed ADC
Transfer Characteristic
5
4
3
2
1
0
0
1
2
3
4
5
6
7
ADC Input Voltage
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 12
Example: 3 Bit ADC
DNL & INL Extracted from Histogram
ADC characteristics
Ideal converter
DNL [LSB]
1
0.5
6
-0.4 LSB DNL
0
-0.5
5
-1
4
3
+0.4 LSB INL
1
2
3
4
5
6
3
4
5
6
1
INL [LSB]
Digital Output Code
7
0.5
2
1
+0.4 LSB DNL
0
-0.5
0
0
1
2
3
4
5
6
ADC Input Voltage [Δ]
EECS 247 Lecture 12:
7
-1
1
2
Digital Output Code
Data Converters- Testing
© 2009 H. K. Page 13
Measuring DNL
• Ramp speed is adjusted to provide large number of
output/code - e.g. an average of 100 outputs of each
ADC code (for 1/100 LSB resolution)
• Ramp test can be quite slow for high resolution ADCs
• Example:
16bit ADC & 100conversions/code @100kHz
sampling rate
(216or 65,536 codes)(100 conversions/code)
100,000 conversions/sec
EECS 247 Lecture 12:
Data Converters- Testing
= 65.6 sec
© 2009 H. K. Page 14
ADC Histogram Testing
Sinusoidal Inputs
ADC Output- Raw Histogram
Code Count
• Ramp signal generators linear
to only 8 to10bits & thus only
good for testing ADCs <10bit
res.
Æ Need to find input signal
with better purity for testing
higher res. ADCs
1000
500
• Solution:
ÆUse sinusoidal test signal
(may need to filter out
harmonics)
• Problem: Ideal ADC histogram
not flat but has “bath-tub shape”
EECS 247 Lecture 12:
Data Converters- Testing
0
1000
2000
3000
4000
ADC output code
© 2009 H. K. Page 15
At sinusoid midpoint crossings:
dv/dt Æ max.
Æ least # of samples
Digital Output
ADC Histogram Test Using Sinusoidal Signals
Analog
input
# of
Samples
Per code Time
At sinusoid amplitude peaks:
dv/dt Æ min.
Æ highest # of samples
EECS 247 Lecture 12:
ADC
Input/Output
Data Converters- Testing
Sinusoid
Digital
Output
© 2009 H. K. Page 16
Histogram Testing
Correction for Sinusoidal PDF
• References:
– [1] M. V. Bossche, J. Schoukens, and J. Renneboog,
“Dynamic Testing and Diagnostics of A/D Converters,” IEEE
Transactions on Circuits and Systems, vol. CAS-33, no. 8,
Aug. 1986.
– [2] IEEE Standard 1057
• Is it necessary to know the exact amplitude and offset
of sinusoidal input? No!
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 17
DNL/INL Extraction Matlab Program
function [dnl,inl] = dnl_inl_sin(y);
%DNL_INL_SIN
% dnl and inl ADC output
% input y contains the ADC output
% vector obtained from quantizing a
% sinusoid
% Boris Murmann, Aug 2002
% Bernhard Boser, Sept 2002
% histogram boundaries
minbin=min(y);
maxbin=max(y);
% histogram
h = hist(y, minbin:maxbin);
% cumulative histogram
ch = cumsum(h);
EECS 247 Lecture 12:
% transition levels found by:
T = -cos(pi*ch/sum(h));
% linearized histogram
hlin = T(2:end) - T(1:end-1);
% truncate at least first and last
% bin, more if input did not clip ADC
trunc=2;
hlin_trunc = hlin(1+trunc:end-trunc);
% calculate lsb size and dnl
lsb= sum(hlin_trunc) / (length(hlin_trunc));
dnl= [0 hlin_trunc/lsb-1];
misscodes = length(find(dnl<-0.99));
% calculate inl
inl= cumsum(dnl);
Data Converters- Testing
© 2009 H. K. Page 18
Example: Test Results for DNL & INL
Using Sinusoidal Histogram
DNL [LSB]
DNL = +1.3 / -1 LSB, missing code if (DNL<-0.99)
1
0
-1
0
500
1000
1500
2500
3000
3500
4000
3000
3500
4000
INL = +1.7 / -0.69 LSB
2
INL [LSB]
2000
code
1
0
-1
0
500
EECS 247 Lecture 12:
1000
1500
2000
code
2500
Data Converters- Testing
© 2009 H. K. Page 19
Example: Matlab ADC Model
DNL/INL Code Test
hist(y, min(y):max(y));
0.5
0
-0.5
-1
fs = 1e6;
fx = 494e3 + pi;
% try fs/10!
C = round(100 * 2^B / (fs / fx));
-30
-10
0
10
20
30
20
30
INL = +0.7 LSB
0.4
0
-30
-20
-10
0
10
Digital Output
dnl_inl_sin(y);
EECS 247 Lecture 12:
-20
0.8
INL [LSB]
t = 0:1/fs:C/fx;
x = (range+1) * sin(2*pi*fx.*t);
y = adc(x, th) - 2^(B-1);
DNL = +0.7 / -0.7 LSB
1
DNL [LSB]
% converter model
B = 6;
% bits
range = 2^(B-1) - 1;
% thresholds (ideal converter)
th = -range:range; % ideal thresholds
th(20) = th(20)+0.7; % error
Data Converters- Testing
© 2009 H. K. Page 20
Histogram Testing Limitations
• The histogram (as any ADC test, of course) characterizes one
particular converter. Test many devices to get valid statistics.
• Histogram testing assumes monotonicity
E.g. “code flips” will not be detected.
• Dynamic sparkle codes produce only minor DNL/INL errors
E.g. 123, 123, …, 123, 0, 124, 124, … Æ look at ADC output to
detect
• Noise not detected & averaged out
E.g. 9, 9, 9, 10, 9, 9, 9, 10, 9, 10, 10, 10, …
Ref: B. Ginetti and P. Jespers, “Reliability of Code Density Test for High Resolution
ADCs,” Electron. Lett., vol. 27, pp. 2231-3, Nov. 1991.
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 21
Example: Hiding Problems in the Noise
• INL Æ 5
missing codes
• DNL "smeared
out" by noise!
• Always look at
both DNL/INL
• INL usually
does not lie...
EECS 247 Lecture 12:
[Source: David Robertson, Analog Devices]
Data Converters- Testing
© 2009 H. K. Page 22
Why Additional Tests/Metrics?
• Static testing does not tell the full story
– E.g. no info about "noise“ or high frequency effects
• Frequency dependence (fs and fin) ?
– In principle we can vary fs and fin when performing
histogram tests
– Result of such sweeps is usually not very useful
– Hard to separate error sources, ambiguity
– Typically we use fs=fsNOM and fin << fs/2 for
histogram tests
• For additional info regarding higher frequency
operation Æ Spectral testing
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 23
DAC Spectural Test or Simulation
Digital
Sinusoid
Signal
Generator
Device Under Test
(DUT)
DAC
Vout
Spectrum
Analyzer
Clock
Generator
• Input sinusoid Æ Need to have significantly better purity compared to DAC
linearity
• Spectrum analyzer need to have better linearity than DUT
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 24
Filtering Input to Spectrum Analyzer
Prevent Signal Distortion Incurred by Spec. Analyzer
1.Measure
fundamental
signal level
DAC
2.Notch out
Output Signal
fundamental
Amplitude
signal so that
Spec. Analyzer
input signal
0
becomes small
enough not to
Spectrum
drive S.A. input
Analyzer
into non-linear
Input
region
Signal
3.Measure the
Amplitude
harmonic content
0
of the DAC output
EECS 247 Lecture 12:
Notch (Band Reject) Filter
...
2fin
fin
3fin
4fin ...
f
...
fin
2fin
3fin
Data Converters- Testing
4fin
...
f
© 2009 H. K. Page 25
Direct ADC Spectral Test via DAC
Device Under Test (DUT)
Vin
Signal
Generator
ADC
DAC
Vout
Spectrum
Analyzer
Clock
Generator
• Need DAC with much better performance compared to ADC
under test
• Beware of DAC output sinx/x frequency shaping
• Good way to "get started"...
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 26
Direct ADC-DAC Test
Device Under Test (DUT)
Bandpass
V in
or
Lowpass
Signal
Generator
ADC
DAC
Notch
Filter
Filter
Clock
Generator
Spectrum
Analyzer
• Issues to beware of:
– Linearity of the signal generator output has to be much better than ADC linearity
– Spectrum analyzer nonlinearities
Æ May need to build/purchase filters to address one or both above
problems
– Clock generator signal jitter
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 27
Filtering ADC Input Signal
Bandpass Filter
Signal Generator
Output Signal
Amplitude
0
...
fin
3fin
2fin
4fin
ADC
Input
Signal
Amplitude
0
EECS 247 Lecture 12:
...
f
...
fin
2fin
3fin
Data Converters- Testing
4fin
...
f
© 2009 H. K. Page 28
ADC Spectral Test via
Data Acquisition Sytem
Device Under Test
(DUT)
Vin
Signal
Generator
Data
Acquisition
System
ADC
PC
Clock
Generator
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 29
Analyzing ADC Outputs via
Discrete Fourier Transform (DFT)
x(t)
⇒
x(k)
• Sinusoidal waveform has all its power at one single frequency
• An ideal, infinite resolution ADC would preserve ideal, single tone
spectrum
• DFT used as a vehicle to reveal ADC deviations from ideality
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 30
Discrete Fourier Transform (DFT)
Properties
• DFT of N samples spaced Ts=1/fs seconds:
– N frequency bins from DC to fs
– Num of bins Æ N & each bin has width= fs /N
– Bin # m represents frequencies at m * fs /N [Hz]
• DFT frequency resolution:
– Proportional to fs /N in [Hz/bin]
• DFT with N = 2k ( k is an integer) can be found using a
computationally more efficient algorithm named:
– FFT Æ Fast Fourier Transform
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 31
DFT Magnitude Plots
•
Because magnitudes of DFT bins (Am) are symmetric around fS /2, it is
redundant to plot ⏐Am⏐’s for m >N/2
0
•
fs/2
fs
Usually magnitudes are plotted on a log scale normalized so that a
full scale sinusoidal waveform with rms value aFS yields a peak bin of
0dBFS:
⏐Am⏐ [dBFS] = 20 log10
EECS 247 Lecture 12:
Data Converters- Testing
⏐Am⏐
aFS .N/2
© 2009 H. K. Page 32
Matlab Example
Normalized DFT
1e6;
50e3;
1;
100;
1
time vector
= linspace(0, (N-1)/fs, N);
input signal
= Afs * cos(2*pi*fx*t);
spectrum
= 20 * log10(abs(dft(y)/N/Afs*2));
drop redundant half
= s(1:N/2);
frequency vector (normalized to fs)
= (0:length(s)-1) / N;
Note: Where does the -300dBFS noise
floor come from?
EECS 247 Lecture 12:
Amplitude
%
t
%
y
%
s
%
s
%
f
=
=
=
=
0.5
0
-0.5
-1
Magnitude [ dBFS ]
fs
fx
Afs
N
0
0.2
0.4
0.6
0.8
0.3
0.4
Time
1
-4
x 10
0
-100
-200
-300
0
fx/fs
0.1
Data Converters- Testing
0.2
0.5
Frequency [ f / fs]
© 2009 H. K. Page 33
“Another” Example …
Signal Amplitude
1
0
-1
0
1
2
3
4
Amplitude [ dBFS ]
Time
5
x 10-5
-10
-20
-30
-40
-50
0
0.1
0.2
0.3
0.4
0.5
Even though the
input signal is a
pure sinusoidal
waveform note that
the DFT results
does not look like
the spectrum of a
sinusoid …
Seems that the
signal is distributed
among several bins
Frequency [ f / fs ]
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 34
DFT Periodicity
Signal Amplitude
• The DFT implicitly assumes that time
sample blocks repeat every N
samples
• With a non-integer number of signal
periods within the observation
window, the input yields significant
amplitude/phase discontinuity at the
block boundary
0.5
0
-0.5
-1
Signal Amplitude
• This energy spreads into other
frequency bins as “spectral leakage”
• Spectral leakage can be eliminated
by either
1. Choice of integer number of
sinusoids in each block
2. Windowing
EECS 247 Lecture 12:
Actual Signal
1
0.4
0
0.8
Time
1.2
-4
x 10
DFT Perceived Signal
1
0.5
0
-0.5
-1
0.4
0
0.8
Time
Data Converters- Testing
1.2
-4
x 10
© 2009 H. K. Page 35
Frequency Spectrum
Integer # of Cycles versus Non-Integer # of Cycles
Integer number of cycles
Non-integer number of cycles
1
Signal Amplitude
Signal Amplitude
1
0.5
0
-0.5
-1
0
0.2
0.4
0.6
0.8
1
1.2
Time
0.5
0
-0.5
-1
0
1.4
-4
0.4
0.6
Time
0.8
1
1.2
1.4
-4
x 10
-10
Amplitude [ dBFS ]
Amplitude [ dBFS ]
0
-100
-200
-300
-400
0
0.2
x 10
0.1
0.2
0.3
0.4
0.5
-20
-30
-40
-50
-60
0
Frequency [ f / fs]
EECS 247 Lecture 12:
0.1
0.2
0.3
0.4
0.5
Frequency [ f / fs]
Data Converters- Testing
© 2009 H. K. Page 36
Choice of Number of Cycles & Number of
Samples
Signal Amplitude
To overcome frequency
spectrum leakage problem:
– Number of Cycles
Æ integer
N/cycles = fs / fx=6 Æ integer
1
0.5
0
-0.5
-1
– N/cycles = fs / fx
Æ non-integer (choose
prime # of cycles)
otherwise quant. noise Æ
periodic and non-random
Signal Amplitude
Time
– Preferable to have N: Æ
power of 2 (FFT instead of
DFT)
1
N/cycles = fs / fx=5.55 Æ non-intege
0.5
0
-0.5
-1
Time
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 37
Example: Integer Number of Cycles
fs = 1e6;
% Number of cycles in test
cycles = 67;
%N=power of 2 speeds up
analysis
Magnitude [ dBFS ]
%Make N/cycles noninteger!
accomplished by choosing
cyclesÆ prime #
0
-50
-100
-150
-200
-250
-300
N = 2^10;
-350
%signal frequency
fx = fs*cycles/N
y = Afs * cos(2*pi*fx*t);
s = 20 * log10(abs(fft(y)/N/Afs*2));
EECS 247 Lecture 12:
0
0.1
0.2
0.3
0.4
Frequency [ f / fs ]
Notice: Range of test signals limited to
[( cycles)x fs/N]
Data Converters- Testing
© 2009 H. K. Page 38
0.5
Example: Integer Number of Cycles
• Fundamental falls into a single
DFT bin
0
• Noise (this example numerical
quantization noise) occupies all
other bins
• “integer number of cycles”
constrains signal frequency fx
Amplitude [ dB ]
-50
• Alternative: windowing Æ
EECS 247 Lecture 12:
-100
-150
-200
-250
-300
-350
0
0.1
0.2
0.3
]
s
0.4
0.5
Frequency [ f / fs]
Data Converters- Testing
© 2009 H. K. Page 39
Windowing
• Spectral leakage can be attenuated by “windowing”
time samples prior to the DFT
– Windows taper smoothly down to zero at the beginning and
the end of the observation window
– Time samples are multiplied by window coefficients on a
sample-by-sample basis
Æ Convolution in frequency domain
• Large number choices of various windows
– Tradeoff: attenuation versus fundamental signal spreading to
number of adjacent bins
• Window examples: Nuttall versus Hann
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 40
Example: Nuttall Window
Time domain
Frequency domain
20
1
0
Magnitude (dB)
Amplitude
0.8
0.6
0.4
-20
-40
-60
0.2
0
-80
20
40
Samples
-100
0
0.2
0.4
0.6
0.8
Normalized Frequency (×π rad/sample)
60
• Time samples are multiplied by window coefficients on a sample-by-sample basis
• Multiplication in the time domain Æ convolution in the frequency domain
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 41
• Time samples are
multiplied by window
coefficients on a sampleby-sample basis
• Signal after windowing
– Windowing removes
the discontinuity at
block boundaries
EECS 247 Lecture 12:
Windowed
Signal Amplitude
• Signal before windowing
Signal Amplitude
Windowed Data
1
0
-1
0
0.2
-2
0
0.2
0.4
0.6
0.8
Time [msec]
1
2
0
Data Converters- Testing
0.4
0.6
Time [msec]
0.8
1
© 2009 H. K. Page 42
Nuttall Window DFT
• Only first 20 bins shown
• Response attenuated by -120dB
for bins > 5
• Lots of windows to choose from
(go by name of inventorBlackman, Harris, Nutall…)
• Various window trade-off
attenuation versus width
(smearing of sinusoids)
Normalized Amplitude [dB]
0
-20
-40
-60
-80
-100
-120
2
EECS 247 Lecture 12:
4
6
8
10 12 14 16 18 20
DFT Bin
Data Converters- Testing
© 2009 H. K. Page 43
• Signal energy
“smeared” over
several
(approximately 10)
bins
Windowed Spectrum
[ dBFS ]
• Windowing results
in ~ 100dB
attenuation of
sidelobes
Spectrum not Windowed
[ dBFS ]
DFT of Windowed Signal
Spectrum Before/After Windowing
0
Before windowing
-20
-40
-60
0
0.1
0.2
0.3
0.4
Frequency [ fx / fs]
0.5
0
After windowing
-40
-80
-120
0
0.1
0.2
0.3
0.4
0.5
Frequency [ fx / fs]
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 44
Window
Nuttall versus Hann
Time domain
Frequency domain
Magnitude (dB)
Amplitude
1
0.8
0.6
0.4
0.2
0
20
40
Samples
60
0
Nuttall
Hann
-50
-100
0
0.2
0.4
Normalized Frequency (×π rad/samp
Matlab code:
N=64;
wvtool(nuttallwin(N),hann(N));
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 45
Integer Cycles versus Windowing
• Integer number of cycles
–
–
–
–
Signal energy for a single sinusoid falls into single DFT bin
Requires careful choice of fx
Ideal for simulations
Measurements Æ need to lock fx to fs (PLL)- not always possible
• Windowing
– No restrictions on fx Æ no need to have the signal locked to fs
Æ Good for measurements w/o having the capability to lock fx to fs or
cases where input is not periodic
– Signal energy and its harmonics distributed over several DFT bins –
handle smeared-out harmonics with care!
– Requires more samples for a given accuracy
– Note that no windowing is equal to windowing with a rectangular
window!
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 46
Example: ADC Spectral Testing
• ADC with B bits
• Full scale input =2
B = 10;
delta = 2/2^B;
y = cos(2*pi*fx/fs*[0:N-1]);
y=round(y/delta)*delta;
s = abs(fft(y)/N*2);
f = (0:length(s)-1) / N;
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 47
ADC Output Spectrum
0
• Input signal bin:
• What is the SNR?
-20
Ampliutde [dbFS]
– Bx @ bin # (N * fx /fs + 1)
(Matlab arrays start at 1)
– Asignal = 0dBFS
N=2048
-40
-60
-80
-100
-120
0
0.1
0.2
0.3
0.4
0.5
f /fs
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 48
Simulated ADC Output Spectrum
0
• Noise bins: all except signal bin
bx = N*fx/fs + 1;
As = 20*log10(s(bx))
%set signal bin to 0
s(bx) = 0;
An = 10*log10(sum(s.^2))
SNR = As - An
Amplitude [dbFS]
N=2048
-20
-40
-60
-80
• MatlabÆSNR = 62dB (10 bits)
• Computed SQNR =
6.02xN+1.76dB=61.96dB
-100
-120
0
f /fs
0.1
0.2
0.3
0.4
0.5
Note: In a real circuit including thermal/flicker noise Æ the measured
total noise is the sum of quantization & noise associated with the circuit
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 49
Why is Noise Floor Not @ -62dB ?
• DFT bins act like an analog
spectrum analyzer with
bandwidth per bin of fs /N
ÆThe DFT noise floor wrt total
noise:
-10log10(N/2) [dB]
below the actual noise floor
• For N=2048:
-10log10(N/2) =-30 [dB]
EECS 247 Lecture 12:
N=2048
-20
Amplitude [dbFS]
• Assuming noise is uniformly
distributed, noise per bin:
(Total noise)/N/2
0
-40
-60
30dB
-80
-100
-120
0
Data Converters- Testing
0.1
0.2
0.3
0.4
0.5
f /fs
© 2009 H. K. Page 50
DFT Plot Annotation
• Need to annotate DFT plot such that actual
noise floor can be readily computed by one of
these 3 ways:
1. Specify how many DFT points (N) are used
2. Shift DFT noise floor by 10log10(N/2) [dB]
3. Normalize to "noise power in 1Hz bandwidth“
then noise is in the form of power spectral
density
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 51
Example 10Bit ADC FFT
• The quantization noise is
not a major error:
SDR = 74dB
• SNR = 56.1dB
This corresponds to
Gaussian thermal noise
with variance Δ/2 at the
converter input … a
reasonable design choice
EECS 247 Lecture 12:
0
N = 4096
SNR = 56.1dB
SDR = 73.9dB
SNDR = 55.0dB
SFDR = 77.5dB
-20
Amplitude [ dBFS ]
• After re-design and re-fab.
Same test performed:
(fx = fs / 16)
-40
-60
-80
-100
-120
-140
0
Data Converters- Testing
0.1
0.2
0.3
0.4
Frequency [ f / fs]
0.5
© 2009 H. K. Page 52
Example:10Bit ADC FFT
0
• For a real 10bit ADC
spectral test results:
3rd
• A
harmonic is barely
visible
Amplitude [ dBFS ]
• SNR=55.9dB
N = 4096
SNR = 55.9dB
SDR = 76.4dB
SNDR = 55.1dB
SFDR = 77.3dB
-20
-40
-60
-80
-100
• Is better view of distortion
component possible?
-120
-140
0
0.1
0.2
0.3
0.4
0.5
Frequency [ f / fs]
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 53
Example:10Bit ADC FFT
• Larger # of bins Æ less
noise power per bin (total
noise stays constant)
• Note the 3rd harmonic is
clearly visible when N is
increased
EECS 247 Lecture 12:
0
Amplitude [ dBFS ]
• Increasing N, the number of
samples (and hence the
measurement or simulation
time) distributes the noise
over larger # of bins
N = 65536
SNR = 55.9dB SDR = 77.9dB
SNDR = 55.2dB SFDR = 78.5dB
-50
-100
-150
0
Data Converters- Testing
0.1
0.2
0.3
0.4
Frequency [ f / fs]
0.5
© 2009 H. K. Page 54
Spectral Performance Metrics
ADC Including Non-Idealities
•
•
•
•
Signal S
DC
Distortion D
Noise N
• Ideal ADC adds:
– Quantization noise
• Real ADC typically adds:
– Thermal and flicker noise
– Harmonic distortion
associated with circuit
nonlinearities
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 55
ADC Spectral Performance Metrics
SNR
•
•
•
•
Signal S
DC
Distortion D
Noise N
• Signal-to-noise ratio
SNR = 10log[(Signal Power) /
(Noise Power)]
• In Matlab: Noise power includes
power associated with all bins
except:
– DC
– Signal
– Signal harmonics
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 56
ADC Spectral Performance Metrics
SDR & SNDR & SFDR
• SDRÆ Signal-to-distortion ratio
= 10log[(Signal Power) /
(Total Distortion Power)]
• SNDRÆ Signal-to(noise+distortion)
= 10log[S / (N+D)]
• SFDRÆ Spurious-free dynamic
range
= 10log[(Signal )/
(Largest Harmonic)]
Æ Typically SFDR > SDR
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 57
Harmonic Components
• At multiples of fx
• Aliasing:
– fsignal = fx = 0.18 fs
– f2 = 2 f0 = 0.36 fs
– f3 = 3 f0 = 0.54 fs
Æ 0.46 fs
– f4 = 4 f0 = 0.72 fs
Æ 0.28 fs
– f5 = 5 f0 = 0.90 fs
Æ 0.10 fs
– f6 = 6 f0 = 1.08 fs
Æ 0.08 fs
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 58
Relationship INL & SFDR/SNDR
ADC Transfer Curve
Output
Output
Real
INL
Input
Quadratic shaped transfer function:
Æ Gives rise to even order harmonics
EECS 247 Lecture 12:
INL
Input
Cubic shaped transfer function:
Æ Gives rise to odd order harmonics
Data Converters- Testing
© 2009 H. K. Page 59
DNL [LSB]
Frequency Spectrum versus INL & DNL
0
-0.03
Good DNL and poor INL
suggests distortion
INL [LSB]
2
1
0
-1
-2
EECS 247 Lecture 12:
Data Converters- Testing
INLÆNot fully symmetric
100 200 300 400 500 600 700 800 900 1000
bin #
© 2009 H. K. Page 60
Relationship INL & SFDR/SNDR
• Nature of harmonics depend on "shape" of
INL curve
• Rule of Thumb: SFDR ≅ 20log(2B/INL)
– E.g. 1LSB INL, 10bÆ SFDR≅60dB
• Beware, this is of course only true under the
same conditions at which the INL was taken,
i.e. typically low input signal frequency
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 61
SNR Degradation due to DNL
[Source: Ion Opris]
• Uniform quantization error pdf was assumed for ideal quantizer
over the range of: +/- Δ/2
• Let's now add uniform DNL over +/- Δ/2 and repeat math...
– Joint pdf for two uniform pdfs Æ Triangular shape
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 62
SNR Degradation due to DNL
• To find total noise Æ Integrate triangular pdf:
+Δ
e2 = 2 ∫ (1 − e)
0
Δ2
e2
de =
Δ
6
⇒ SNR = 6.02 ⋅ N − 1.25 [dB]
3dB
• Compare to ideal quantizer:
e2 =
+ Δ / 2 e2
∫
−Δ / 2 Δ
de =
⇒ SNR = 6.02 ⋅ N + 1.76 [dB]
Δ2
12
ÆError associated with DNL reduces overall SNR
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 63
SNR Degradation due to DNL
• More general case:
–
–
–
–
Uniform quantization error ±0.5Δ
Uniform DNL error ± DNL [LSB]
Convolution yields trapezoid shaped joint pdf
SQNR becomes:
SQNR =
EECS 247 Lecture 12:
1 ⎛⎜ 2 N Δ ⎞⎟
2 ⎜⎝ 2 ⎟⎠
2
Δ2 DNL2
+
12
3
Data Converters- Testing
© 2009 H. K. Page 64
SNR Degradation due to DNL
• Degradation in dB:
⎤
⎡
1
⎢
⎥
8
⎥
SQNR _ deg = 1.76 − 10 log ⎢
2
⎢ 1 DNL ⎥
⎢⎣ 12 + 3 ⎥⎦
Valid only for cases where with
no missing codes
8
6
SNR
Degradation
4
[dB]
2
0
0
EECS 247 Lecture 12:
0.2
0.4
0.6
|DNL| [LSB]
Data Converters- Testing
0.8
1
© 2009 H. K. Page 65
Summary
INL & SFDR -
DNL & SNR
INL & SFDR
• Type of distortion depends on
"shape" of INL
Assumptions:
• DNL pdf Æuniform
• No missing codes
• Rule of Thumb:
SFDR ≅ 20 log(2B/INL)
– E.g. 1LSB INL, 10b
Æ SFDR≅60dB
EECS 247 Lecture 12:
DNL & SNR
Data Converters- Testing
1 ⎛⎜ 2 N Δ ⎞⎟
2 ⎜⎝ 2 ⎟⎠
2
SQNR = 2
Δ DNL2
+
12
3
© 2009 H. K. Page 66
Uniform DNL?
# of occurrences
250
200
150
100
50
0
-0.5 -0.4 -0.3 -0.2 -0.1 0
0.1 0.2 0.3 0.4 0.5
DNL
• DNL distribution of 12-bit ADC test chip
• Not quite uniform...
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 67
Effective Number of Bits (ENOB)
• Is a 12-Bit converter with 68dB SNDR really a 12-Bit
converter?
• Effective Number of Bits (ENOB)Æ # of bit of an ideal
ADC with the same SQNR as the SNDR of the nonideal ADC
SNDR − 1.76dB
ENOB =
6.02dB
68 − 1.76
= 11.0Bits
6.02
• Æ Above ADC is a 12bit ADC with ENOB=11bits
=
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 68
ENOB
• At best, we get "ideal" ENOB only for
negligible thermal noise, DNL, INL
• Low noise design is costly Æ 4x penalty in
power per (ENOB-) bit or 6dB extra SNDR
• Rule of thumb for good performance /power
tradeoff: ENOB < N-1
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 69
ENOB Survey
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. on
Selected Areas in Communications, pp. 539-50, April 1999
EECS 247 Lecture 12:
Data Converters- Testing
© 2009 H. K. Page 70