Digitizing the Analog World:
Challenges and Opportunities
April 5, 2010
Boris Murmann
murmann@stanford.edu
Murmann
Mixed-Signal Group
Murmann Mixed-Signal Group
2
Research Overview
Biomolecule
detection
MEMS
Sensor
interfaces
Signal
Conditioning
Spin-Valve
Neural
prosthetics
Transducers,
Antennas,
Cables, ...
Digital enhancement
algorithms
A/D
Signal
Processing
Signal
Conditioning
D/A
High-performance and lowpower A/D and D/A
converters
Medical ultrasound
3
Research Examples

High-performance A/D converters

Neural prosthetics

MEMS accelerometers

Large area electronics
4
Digitally Assisted A/D Converters
Additional digital processing for
performance enhancement
Signal
Conditioning
Analog Media
and
Transducers
A/D
Signal
Processing
CLK
Signal
Conditioning
Analog
D/A
Digital
5
ADC for a “Digital” Serial Link


No analog error accumulation and better scalability
Need efficient high-speed ADC, typically > 10GS/s
6
Time-Interleaving

Popular way to increase ADC throuhgput
1
text
ADC1
2
ADC2
X(t)
Y[n]
N
ADCN
7
Imperfections

Mismatches result in signal distortion



Gain
Offset
Timing Skew
Voff_1
1
text
ADC1
G1
Voff_2
2
ADC2
G2
X(t)
Y[n]
Voff_N
GN
N
ADCN
8
Our Focus: Timing Skew
(2-channel example)
1
2

9
Skew Calibration Using Extra ADC

Statistics-based skew measurement in digital backend

Correction through analog adjustments
1
ADC1
2
ADC2
X(t)
Y[n]
1 2
N
ADCN
Cal
ADCCal
Digital Backend
Clock
Digitally
adjustable
delay cells
10
Timing of Auxiliary ADC Phase
1
2
N
Cal
1
ADC
1
1
2
ADC
2
2
X(t)
Y[n]
1 2
N
N
ADC
N
N
Digital Backend
Clock
Cal
ADC
Cal
Cal
11
Calibration Scheme

For each channel, adjust delay cells until correlation between
calibration ADC output and each slice are maximized

ADCCal can be 1-bit and “slow”
R()
1

ADC1
2
ADC2
X(t)
Y[n]
1 2
N
ADCN
Max
Clock
Cal
ADCCal
12

Removed pre-publication slides on experimental
results…
13
MEMS Accelerometer
CMOS

Capacitance change ~10 fF/g

Desired resolution ~10 mg for airbags and ESP


Must resolve capacitance changes of ~100 aF
Problem: Drift in parasitic bondwire capacitance
14
Sigma-Delta Interface
Mechanical
aIN
m
Fmech
1
ms 2  bs  k
x C
C
x
AC V
V
S/H
Lead
Compensator
VOut
Decimator
VDig
ForceBalancing
M. Lemkin and B. E. Boser, “A three-axis micromachined accelerometer with a CMOS
position-sense interface and digital offset-trim electronics,“ IEEE J. Solid-State Circuits,
vol. 34, pp. 456-468, April 1999.
15
Offset
Offset due to bond
wire deformation
COffset
aIN
m
Fmech
1
ms 2  bs  k
x
C
x
C
AC V
V
S/H
Lead
Compensator
ForceBalancing
16
Linear Feedback System with Two Inputs
x2
x1
y
+_
a
+
b
f
1
1
y  x1   x2 
f
af
17
Spring Constant Modulation

The output due to Coff can be modulated to higher
frequencies by modulating the spring constant k
VOut  Fmech 
1
k k
 COff 
C
FB
FB 
x
COffset
aIN
m
Fmech
1
ms 2  bs  k
x
C
x
C
AC V
V
S/H
Lead
Compensator
ForceBalancing
18
Spring softening effect
Acceleration
Spring

Acceleration
Spring
Electrostatic
_
+
_
_
+
_
_
+
_
_
+
_
Can be used to modulate spring constant (k)
19
Modulation through Multiplexed Feedback
aIN
m
Fmech
1
ms 2  bs  k
km  x
x C
C
x
PULSE
Time-Multiplexed
AC V
V
S/H
Int
Com
Decimator
fk
Electrostatic
Force
MOD Force-Balancing MOD Force-Balancing
T
T
20
VOut
Output Spectrum with 1-Tone Modulation
0
Power/frequency (dB/Hz)
-20
-32 dB
-46 dB
-40
DC
Offset
Acceleration Capacitance
-60
-80
9.1 m/s^2
9.1 m/s^2
9.1 m/s^2
-89 dB
-100
0 fF
10 fF
50 fF
-120
-140
-160 -6
10
-5
10
-4
10
-3
10
Frequency (MHz)
-2
10
-1
10
21
Pseudo-Random Modulation
Modulating spring-constant with a pseudo-random sequence
-20
Output Spectrum [dB]
-40
-60
-80
-100
-120
-140 0
10
2
4
10
10
6
10
Frequency [Hz]
22
Parameter Convergence
Closed-loop system - Feeding back capacitance
Feedback signal [x10 -15]
1.2
1
0.8
Coff=0fF
Coff=0.01fF
Coff=0.1fF
Coff=1fF
0.6
0.4
0.2
0
-0.2
0
0.5
1
1.5
2
Time [Sec]
23
Chip Design in Progress
DOut
FPGA
Correlator
Decimator
Compensator
Quantizer
MEMS
CMOS
C to V
Integrator
StateMachine
VOut
Clk
Electrostatic
Feedback
k-modulation
VRef Gnd
Scan In/Out
24
Neural Prosthetics

Cortical motor prosthetics

Neurons in the motor cortical areas of the brain encode
information about intended movement
Courtesy K.V. Shenoy
Courtesy L.R. Hochberg
Nature Magazine June ‘06
25
Neural Signal Acquisition

Electrode signals consist of multiple sources



DC Offset, about 15mV from electrode/tissue interface
Local field potential (LFP), ≤3mV peak, 10Hz to 100Hz
Spikes from nearby neurons, 35μV – 1mV peak, 500Hz to 5kHz
Courtesy M. Sahani
Courtesy C.L. Klaver
26
Specs

Separate the fast and slow signal acquisition for DR

Custom front end design for each path
Spikes
Local Field Potential
600 V/V
200 V/V
Lower Cutoff
300Hz
1Hz
Upper Cutoff
10kHz
1kHz
Gain
Input Referred Noise 2.0µVrms
(total from sampling node)
Total Power (96x Array)
3mW
1.0µVrms in 10-100Hz
100µW
27
Spike Path Front-End
SAR ADC
Input Cap
Input Stage
Output
Buffers
SC
Bandpass
Filter
28
Sampling Phase

Integrate signal current on
CB and sample


High-pass for DC block
using Cac and Rbig (offresistance)
A1 contains a pole that
helps minimize noise
folding
29
A1 Implementation Details
ITAIL
M1a
I<< ITAIL
Voutp
Voutm
M1b
VB2
VB1
Flicker noise
reduction
Anti-alias for
thermal noise
from M1a,b
30
Static Power
31
Two-Channel Interface Pixel
SAR ADC
Frontend
32
Die Photo (96 channels, 5mm x 5mm)
33
The Future?
34
Organic Semiconductors

Mechanically flexible

Suitable for solution processing


Cover large areas at low cost
Make disposable devices
35
Jellyfish Autonomous Node
http://muri.mse.vt.edu/
36
Jellyfish Bell Prototype (Virginia Tech)
A bio-inspired shape memory alloy composite (BISMAC) actuator
A .A .Villanueva, et al., 2010 Smart Mater. Struct. 19 025013 (17pp)
37
Want to Make Plastic ADCs !
38
6-bit A/D Converter Prototype
Substrate
Glass
Interconnect
Ti/Au evaporation, litho, wet etch
Gate electrodes
Al evaporation, shadow masking
Source/Drain
Au Evaporation, shadow masking
Dielectric
5.7nm AlOx/SAM
PFET
DNTT, ~0.5 cm2/Vs
NFET
F16CuPc, ~0.02 cm2/Vs
Area
28mm x 22mm
Component count
74
W. Xiong, U. Zschieschang, H. Klauk, and B.
Murmann, “A 3V, 6b Successive Approximation ADC
using Complementary Organic Thin-Film Transistors
on Glass,” ISSCC 2010.
39
ADC Schematic
Output
Calibration enables 6-bit
precision despite poorly
matched capacitors
SAR Logic
(off-chip)
To DAC
Calibration DAC
VREFN
C-2C structure
possible due
small stray
caps (glass)
VMID
VREFP
DAC with
Sampler
Comparator
C/32
Bit 0
C
C
VREFN VREFP
Input
C/32
...
Bit 1
2C
VREFN
Bit 2, 3, 4
Bit 5
2C
C
VREFP
C/32
VREFN
C
VREFP
VREFN
VMID
...
Main DAC
40
Comparator
Auto-zeroing
cancels threshold
voltage drift
CS1
+
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CLK
CF1
CS2
CF2
CS3
CF3
CS4
CF4
-
Input
Output
Wp = 500um
Wn = 500um
PFET/NFET Lp = Ln = 20um
CS1 = 1.1nF
Anti-parallel
layout minimizes variations
if CF due to misalignmentA0 = -7.8
 = 3.0ms
Wp = 400um
Wn = 400um
Lp = Ln = 20um
CS2 = 1.1nF
A0 = -9.8
 = 4.0ms
C
Wp = 400um
Wn = 400um
gdpLp = Ln = 20um
CS3 = 1.1nF
A0 = -9.8
 = 4.0ms
Wp = 100um
Wn = 300um
Lp = gdn
Ln = 20um
CS4 = 1.1nF
C
A0 = -19.6
 = 16.4ms
Transmission Gates:
Wp = Wn = 100um
Lp = Ln = 20um
41
Measured DNL/INL
Before calibration, 100 Hz clock rate
DNL (LSB)
4
2
0
-2
-4
0
8
16
24
32
Code
40
48
56
63
0
8
16
24
32
Code
40
48
56
63
INL (LSB)
4
2
0
-2
-4
42
Measured DNL/INL
After calibration, 100 Hz clock rate
DNL (LSB)
1
0.5
0
-0.5
-1
0
8
16
24
32
Code
40
48
56
63
0
8
16
24
32
Code
40
48
56
63
INL (LSB)
1
0.5
0
-0.5
-1
43
Organic ADC Summary
Process
3 metal complementary
organic thin-film
Minimum feature size
20 mm
Chip area
28 mm x 22 mm
Resolution
6 bits
Full-scale range
2V
Max DNL / INL
-0.6 LSB / 0.6 LSB
Clock rate / Update rate
100 Hz / 16.7 Hz
Power consumption
3.6 mW @ 3 V
44
Conclusions

Mixed-signal IC design remains a vibrant area of
research

Changing boundary conditions




Ever-increasing need for higher performance, lower power
New applications
New device technologies
A recurring theme in our research

Looking for new ways to overcome analog imperfections
using DSP and calibration
45