Aox Incorporated - Proprietary and Confidential
99-1-22 7:28 AM
SE401 ASIC Specification
Aox Incorporated
Se401.doc
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Aox Incorporated - Proprietary and Confidential
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AOX - SE401 ASIC CONTROLLER........................................................................................................... 4
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
1.10
1.11
2
OPERATING MODE REGISTER ADDRESS C0A0H.................................................................................. 15
CONTROL REGISTER ADDRESS C0A2H ............................................................................................. 16
PACKET SIZE REGISTER ADDRESS C0A4H ......................................................................................... 16
CLOCK DIVIDE REGISTER ADDRESS C0A6H ....................................................................................... 17
UPPER WINDOW HEIGHT REGISTER ADDRESS C0A8H ......................................................................... 17
LOWER WINDOW HEIGHT REGISTER ADDRESS C0AAH ....................................................................... 17
PACKET COUNT A REGISTER ADDRESS C0ACH READ ONLY ................................................................ 17
PACKET COUNT B REGISTER ADDRESS C0AEH READ ONLY ................................................................ 17
COMPRESSION ENGINE DATA ................................................................................................................. 18
PROGRAMMABLE TIMERS................................................................................................................... 19
6.1
6.2
6.3
7
COMPRESSION ENGINE CONTROL REGISTER ADDRESS C0B0H ............................................................ 14
TEST REGISTER ADDRESS C0B2H.................................................................................................... 14
COMPRESSION ENGINE INTERFACE. ................................................................................................ 15
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6
UART CONTROL REGISTER (READ/WRITE) ADDRESS C0E0H ............................................................ 12
UART STATUS REGISTER (READ ONLY) ADDRESS C0E2H ................................................................. 13
UART TRANSMIT DATA REGISTER (WRITE ONLY) ADDRESS C0E4H ................................................... 13
UART RECEIVE DATA REGISTER (READ ONLY) ADDRESS C0E4H ....................................................... 13
COMPRESSION ENGINE CONTROLLER............................................................................................. 14
4.1
4.2
5
POWER DOWN CONTROL REGISTER ADDRESS C00AH ............................................................................ 8
SPEED CONTROL REGISTER ADDRESS C008H ........................................................................................ 9
VERSION ADDRESS REGISTER (READ ONLY) (SEE ROM BIOS)................................................................ 9
CONFIG REGISTER ADDRESS C006H................................................................................................... 10
BREAKPOINT REGISTER ADDRESS C014H ........................................................................................... 11
UART INTERFACE................................................................................................................................... 12
3.1
3.2
3.3
3.4
4
FEATURES OF THE SE401 ASIC CONTROLLER .......................................................................................... 5
16 BIT PROCESSOR .................................................................................................................................. 6
INTERNAL RAM BUFFER ........................................................................................................................... 6
PLL CLOCK GENERATOR ......................................................................................................................... 6
USB INTERFACE ...................................................................................................................................... 6
VIDEO INTERFACE & COMPRESSION ENGINE ............................................................................................ 6
SPORT INTERFACE ................................................................................................................................... 6
UART INTERFACE ................................................................................................................................... 6
GENERAL PURPOSE I/O ............................................................................................................................ 7
SERIAL EEPROM SUPPORT ..................................................................................................................... 7
EXTERNAL SRAM/ROM INTERFACE........................................................................................................ 7
PROCESSOR CONTROL REGISTERS..................................................................................................... 8
2.1
2.2
2.3
2.4
2.5
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TIMER 0 COUNT REGISTER ADDRESS C010H ...................................................................................... 19
TIMER 1 COUNT REGISTER ADDRESS C012H ...................................................................................... 19
WATCHDOG TIMER COUNT & CONTROL REGISTER ADDRESS C00CH..................................................... 20
GENERAL PURPOSE I/O......................................................................................................................... 21
7.1
7.2
7.3
7.4
7.5
I/O CONTROL REGISTER 0 ADDRESS C022H ...................................................................................... 21
I/O CONTROL REGISTER 1 ADDRESS C028H ...................................................................................... 21
I/O CONTROL REGISTER 2 ADDRESS C034H ...................................................................................... 21
I/O OUTPUT DATA REGISTER 0 ADDRESS C01EH ............................................................................... 21
I/O OUTPUT DATA REGISTER 1 ADDRESS C024H ............................................................................... 22
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7.6
7.7
7.8
7.9
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I/O OUTPUT DATA REGISTER 2 ADDRESS C030H................................................................................ 22
I/O INPUT DATA REGISTER 0 ADDRESS C020H ................................................................................... 22
I/O INPUT DATA REGISTER 1 ADDRESS C026H ................................................................................... 22
I/O INPUT DATA REGISTER 2 ADDRESS C032H ................................................................................... 22
INTERRUPTS ............................................................................................................................................ 24
8.1
8.2
9
INTERRUPT ENABLE REGISTER ADDRESS C00EH................................................................................. 25
GPIO INTERRUPT CONTROL REGISTER ADDRESS C01CH ..................................................................... 25
MEMORY INTERFACE ........................................................................................................................... 26
9.1
9.2
10
MEMORY CONTROL REGISTER. ADDRESS C03EH ............................................................................... 27
EXTENDED MEMORY CONTROL REGISTER. ADDRESS C03AH ............................................................... 27
SPORT SYNCHRONOUS SERIAL PORT ........................................................................................... 28
10.1
10.2
10.3
10.4
10.5
11
TX DMA ADDRESS REGISTER ADDRESS 0144H.................................................................................. 28
TX DMA COUNT REGISTER ADDRESS 0146H ..................................................................................... 28
RX DMA ADDRESS REGISTER ADDRESS 0140H.................................................................................. 28
RX DMA COUNT REGISTER ADDRESS 0142H ..................................................................................... 28
SPORT CONTROL REGISTER ADDRESS C070H.................................................................................... 29
USB UNIVERSAL SERIAL BUS........................................................................................................... 30
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
11.14
11.15
11.16
12
CONTROL AND STATUS REGISTER ADDRESS C080H ............................................................................. 30
FRAME NUMBER REGISTER ADDRESS C082H ...................................................................................... 31
USB ADDRESS REGISTER ADDRESS C084H......................................................................................... 31
COMMAND DONE REGISTER (WRITE ONLY) ADDRESS C086H ............................................................... 31
ENDPOINT 0 CONTROL AND STATUS REGISTER ADDRESS C090H............................................................ 32
ENDPOINT 1 CONTROL AND STATUS REGISTER ADDRESS C092H............................................................ 32
ENDPOINT 2 CONTROL AND STATUS REGISTER ADDRESS C094H............................................................ 32
ENDPOINT 3 CONTROL AND STATUS REGISTER ADDRESS C096H............................................................ 32
ENDPOINT 0 ADDRESS REGISTER ADDRESS 0120H ............................................................................... 34
ENDPOINT 1 ADDRESS REGISTER ADDRESS 0124H............................................................................ 34
ENDPOINT 2 ADDRESS REGISTER ADDRESS 0128H............................................................................ 34
ENDPOINT 3 ADDRESS REGISTER ADDRESS 012CH........................................................................... 34
ENDPOINT 0 COUNT REGISTER ADDRESS 0122H............................................................................... 34
ENDPOINT 1 COUNT REGISTER ADDRESS 0126H............................................................................... 34
ENDPOINT 2 COUNT REGISTER ADDRESS 012AH .............................................................................. 34
ENDPOINT 3 COUNT REGISTER ADDRESS 012EH............................................................................... 34
PHYSICAL SECTION ........................................................................................................................... 35
12.1
PINOUT FOR 100 LQFP PACKAGE ........................................................................................................... 35
13 ........................................................................................................................................................................ 39
14
TESTING MODES ................................................................................................................................. 39
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Introduction
1
Aox - SE401 ASIC Controller
The SE401 ASIC Controller is a single chip that provides the capability to
interface to a force feedback device and the Universal Serial Bus (USB). The SE401
ASIC Controller consists of a central 16-bit processor, mask ROM, RAM buffer, clock
generator, and a series of interfaces. The interfaces, shown in the block diagram
below, provide control and data access, and USB data reception and transmission.
Compression
Engine
Timer 0
Timer 1
Watchdog
Timer
16 Bit Processor
Add/
Data
Serial
Interface
(GPIO)
Mask ROM
Txd
4
INT1-0
IRQ
(GPIO)
DIO
RAM
UART
(GPIO)
Rxd
CK
Serial Interface
Engine
External
Memory
Interface
(GPIO)
PLL &
Clock
Generator
A15-0
D15-0
Ctrl.
X1
X2
USB Interface
Data -
Data +
SE401 Controller Block Diagram
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1.1
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Features of the SE401 ASIC Controller
•
Built in 16 Bit processor with special purpose instructions for USB transaction
processing and control data processing.
•
Complete USB interface with built in transceivers and SIE (Serial Interface
Engine).
•
Internal Clock Generation circuitry which requires only low cost external
crystal circuitry.
•
1.5K X 16 Internal RAM buffer.
•
1K X 8 Internal Line Buffer
•
6K X 16 Internal ROM buffer.
•
Hyundai Video Interface & Compression Engine.
•
SPORT
•
Built in UART
•
Watchdog Timer
•
0.35 micron ASIC technology
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1.2
16 Bit Processor
The SE401 ASIC Controller has a built-in 16-bit processor along with a 10K x 16
masked ROM. The processor operates with a specialized instruction set that is
designed for highly efficient coding of processing algorithms and USB transaction
processing. The code for the 16-bit processor resides in a masked ROM.
The 16-bit processor has access to the Ram Buffer, external memory interface,
and all the control and status registers.
1.3
Internal Ram Buffer
The SE401 ASIC Controller contains a 3 K byte internal buffer memory,
organized as 1.5K X 16. The memory is used to buffer data and USB packets and is
accessed by the 16 Bit processor and the SIE (Serial Interface Engine).
USB transactions are automatically routed to the memory buffer. The 16-bit
processor has the ability to set up pointers and block sizes in buffer memory for USB
transactions. Data is read from the interface and is processed and packetized by the 16bit I/O processor.
1.4
PLL Clock Generator
A 12 MHz external crystal may be used with the SE401 ASIC Controller. Two
pins, X1 and CLK, are provided to connect a lower cost crystal circuit to the device. PLL
circuitry is provided to generate the internal 48 MHz clock requirements of the device. If
an external 12 MHz clock is available in the application, it may be used in lieu of the
crystal circuit by connecting directly to the CLK input pin.
1.5
USB Interface
The SE401 ASIC Controller has a built in transceiver that meets the Universal
Serial Bus (USB) specification v1.1. The transceiver is capable of transmitting and
receiving serial data at the USB full speed, 12 Mbits/sec, data rate. The driver portion
of the transceiver is differential, while the receive section is comprised of a differential
receiver and two single ended receivers. Internally, the transceiver interfaces to the SIE
(Serial Interface Engine) logic. Externally, the transceiver connects to the physical layer
of the USB.
1.6
Video Interface & Compression Engine
1.7
Sport Interface
The SE401 Sport Interface is a sixteen bit, full-duplex, synchronous serial
port.
1.8
UART Interface
Supports 7200 to 115.2K baud.
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1.9
General Purpose I/O
Up to 38 general purpose I/O signals are available. However, most GPIO may
be configured for special purpose functions such as UART, Serial EEPROM interface,
Digital Input. Etc.
1.10 Serial EEPROM Support
The SE401 ASIC Controller serial interface is used to provide access to external
EEPROM's. The interface is implemented using General Purpose I/O signals and can
support a variety of serial EEPROM formats.
1.11 External SRAM/ROM Interface
An external address port and 16-bit data port exists to interface to an external
RAM or ROM. The port provides RD and WR control signals for data access to the
memory.
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2
Processor Control Registers
The SE401 ASIC Controller has two special purpose registers that allow
operation of the device at different clock frequencies, and a special power saving mode
used for USB Suspend operation. The two registers allow selections to be made to
match a particular application.
2.1
Power Down Control Register
D7 D6
0
0
D5
D4
USB
IRQ
Address C00AH
D3
D2
D1
D0
PUD1 PUD0 SUSPEND HALT
During Powerdown mode, the peripherals are put in a “pause” state. Counters and
timers stop incrementing and the PWM stops. There are 2 ways to enter powerdown
mode: Suspend or Halt.
D5
USB
Enable restart on USB transition. Will
result in device power up.
D4
IRQ
Enable restart on IRQ transition. Will
result in device power up. Uses edges defined I
in Interrupt Control Register.
D3, D2
PUD1,0
Power up delay selection. Four delays are
provided and selected using these select bits.
This is time from power up until processor
starts executing. This allows clock to settle.
PUD1
PUD0
0
0
0
1
0 msec
1 msec
1
0
8 msec
1
1
64 msec
D1
SUSPEND
D0
HALT
Se401.doc
Power up delay
Suspend mode stops ALL clocks in the SE401
ASIC to save power.. This mode ends with a
transition on either USB or the GPIO Interrupt if they
are enabled above. It is followed by a delay set in the
Power Up Delay bit fields.
Halt mode stops JUST the Processor Clock.
Halt mode ends with any interrupt.
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2.2
Speed Control Register
Address C008H
The Speed Control Register allows the operation of the SE401 ASIC processor
at a number of speed selections.
A four bit divider (SPD3-0 + 1) selects the
speed as shown below:
D7 D6 D5 D4
0
D3-0
0
0
0
D3
D2
D1
D0
SPD3 SPD2 SPD1 SPD0
SPD3,0
SPD3-0
SE401 ASIC
SPEED
0000
0001
48 MHz.
24 MHz.
0010
0011
16 MHz.
12 MHz.
0100
9.6 MHz.
0101
0110
8 MHz.
6.86 MHz.
0111
6 MHz.
1000
1001
5.33 MHz.
4.80 MHz.
1010
1011
4.36 MHz.
4.00 MHz.
1100
3.69 MHz.
1101
1110
3.42 MHz.
3.20 MHz.
1111
3.00 MHz.
On power up, lowest speed is selected for lower power operation.
2.3
Version Address Register (read only)
Se401.doc
(See ROM BIOS)
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2.4
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Config Register
Address C006H
The Config Register is used to configure the SE401 into the appropriate mode.
D15 D14 D13 D12 D11 D10
0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
C1
C0
CD
0
D2
C1 Clock Configuration bit 1. Enables Internal PLL.
Default = ‘ 0’ .
D1
C0 Clock Configuration bit 0 . Selects frequency of JGCLK.
(Compression Module Clock) Default = ‘ 0’ .
C1
C0
JGCLK
RCLK
0
0
0
1
X1
2/3*X1
X1
X1
1
0
4*X1
4*X1
1
1
8/3*X1
4*X1
Note: 1) When using the PLL, the X1 input pin clock should be 12 MHz.
2) Default C1 C0 = ‘ 00’ .
D0
Se401.doc
CD
If Config Disable bit = ‘ 1’ , the Configuration register can
no longer be modified through SW writes. It is a “sticky bit”
used to lock the configuration through a write to this bit in
the boot prom code. Default = ‘ 0’ .
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2.5
Breakpoint Register
Address C014H
The Breakpoint Register holds the breakpoint address. When an access to this
address is done an INT127 occurs.
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A15 A14 A13 A12 A11 A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15-0
Se401.doc
A15-0
Breakpoint address.
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3
UART Interface.
The SE401 ASIC Controller UART port supports a range of baud rates from 7200
Baud up to 115.2 KBaud. Baud Rate selection is made in the Control Register. Buffer
status can be monitored in the Status Register. Transmit and receive data is written or
read from the UART data register. The UART timers are independent of the general
purpose timers.
The UART will cause “edge trigger” type interrupts on receiver buffer transitioning to
FULL or transmit transitioning to buffer EMPTY.
3.1
UART Control Register (Read/Write)
D15 D14 D13 D12 D11 D10
0
0
0
0
0
D8
0
0
D7 D6
0
0
D5
D4
D3 D2 D1 D0
WDC DIV8 B2
B1
B0
E
D5
WDC
Test bit . When set to ‘ 1’ Watchdog timer clock
runs at 1 mhz . Defaults to ‘ 0’ .
D4
DIV8
Acts as a pre-scaler if set to ‘ 1’ .
Divides the clock by 8 before generating
the UART clock.
D3-1
B2-0
D0
Se401.doc
0
D9
Address C0E0H
E
BAUD
RATE
SELECTOR
BITS.
WITH /8
PRESCALER
000
115.2 KBaud
14.4 KBaud
001
010
57.6 KBaud
38.4 KBaud
7.2 KBaud
4.8 KBaud
011
28.8 KBaud
3.6 KBaud
100
101
19.2 KBaud
14.4 KBaud
2.4 KBaud
1.8 KBaud
110
111
9.6 KBaud
7.2 KBaud
1.2 KBaud
0.9 KBaud
Enable UART when set = '1'.
When '0', UART pins are GPIO.
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3.2
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UART Status Register (Read Only)
Address C0E2H
D7 D6 D5 D4 D3 D2
0
D1
0
0
0
0
D1
0
D0
RxF TxF
Receive Buffer Full Flag. Sets to ‘ 1’ when Rx
Buffer is Full.
D0
TxF
Transmit Buffer Full Flag. Sets to ‘ 1’ when Tx
Buffer is Full.
Note: 1) No error detection for receive is supported.
3.3
RxF
UART Transmit Data Register (Write Only)
D7
D6
D5
D4
D3
D2
Address C0E4H
D1
D0
TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
D7-D0
3.4
TR7-0
UART Transmit Data
UART Receive Data Register
D7
D6
D5
(Read Only)
D4
D3
D2
Address C0E4H
D1
D0
RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
D7-D0
Se401.doc
RD7-0
UART Receive Data.
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4
Compression Engine Controller.
The SE401 Compression Engine is enabled through the compression engine
Control register.
4.1
Compression Engine Control Register
Address C0B0H
D15 D14 D13 D12 D11 D10
0
0
0
0
0
0
D3
TST
D2
CLKEN
D1
CRST
D0
COE
D9
0
D8 D7
0
D6
D5
D4
D3
0
0
0
TST
0
D2
D1
D0
CLKEN CRST COE
When set to ‘ 1’ , enables Test Register.
Defaults to ‘ 0’ .
When set to ‘ 1’ , enables Compression Engine clock.
Defaults to ‘ 0’ .
When set to ‘ 1’ , takes the Compression Engine out
of reset. Defaults to ‘ 0’ .
When set to ‘ 1’ , enables the Se401 I/O. (see note1)
Defaults to ‘ 0’ .
Note 1) When COE is asserted, control of XD and XA I/O are turned over to
the Compression engine. They can’ t be used by the QT engine.
4.2
TEST Register
Address C0B2H
D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 CD7 CD6 C 5 CD4 CD3 CD2 CD1 CD0
D15-8
D7-0
CD7-0
CD7-0
Data from compression module.
Data from compression module.
When bit3 in the Control Register is set to ‘ 1’ , a read of this register will
return a byte of video data from the Compression module. This one byte
is return on CD[15:8] and CD[7:0].
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Compression Engine Interface.
5.1
Operating Mode Register
D15 D14 D13 D12 D11 D10
0
0
0
0
0
0
Address C0A0H
D9
D8
0
0
D7
D6
D5
D4
D3
D2
LV2 LV1 LV0
SB
MEG4
KJV
D1
OM1 OM0
D[7:5]
LV[2:0]
Lossy Value.(typical compression ratio)
0 0 0 reserved
0 0 1 highest quality, lowest compression (2.55)
……. .
1 0 0 middle quality, middle compression (3.62)
……
1 1 1 lowest quality, highest compression (4.43)
D4
SB
This bit is only used when MEG4 is set.
When set to ‘ 1’ , frame buffer supports 1 logical
frame buffer. Defaults to ‘ 0’ . (2 logical frame buffers)
D3
MEG4
When set to ‘ 1’ , SE401 will support a 4 meg dram.
Defaults to ‘ 0’ . (16 meg dram)
D2
KJV
KJV mode.
D[1:0]
OM[1:0]
Operating mode
OM[1] OM[0]
X
1
0
0
1
0
Se401.doc
D0
Raw data mode
1/4 Sub-Sampled & Compression
1/16 Sub-Sampled & Compression
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5.2
Address C0A2H
Control Register
D15 D14 D13 D12 D11 D10 D9
0
0
0
0
0
0
D6
D5
D4
BOF
FSTAT1
FSTAT0
D3
D2
D1
D0
INTB
INTA
RDB
RDA
0
D8
D7
0
0
D6
D5
D4
D3
D2
D1
D0
BOF FSTAT1 FSTAT0 INTB INTA RDB RDA
Indicates an overflow of the 2 Mbit limit.
Indicates the start of a new frame
Indicates if the current frame is fed into the
frame buffer. (see note 1)
Interrupt B (0: full, 1: empty), default 1 (RO)
Interrupt A (0: full, 1: empty), default 1 (RO)
ReaddoneB. (1: QT set, 0: CE clear), default 0
ReaddoneA. (1: QT set, 0: CE clear), default 0
Note 1) Bits D[6:4] are set by the compression engine and cleared by the QT
Engine. When a write access is made to this register, it is clear independent
of the data bus.
5.3
Packet Size Register
Address C0A4H
D15 D14 D13 D12 D11 D10 D9
0
0
0
D[2:0]
Se401.doc
0
0
0
PS[2:0]
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
PS2
PS1
PS0
Packetsize[2:0]
1 1 1 -1024 bytes
1 1 0 -896 bytes
1 0 1 -768 bytes
1 0 0 -640 bytes
0 1 1 -512 bytes
0 1 0 -384 bytes
0 0 1 -256 bytes
0 0 0 -128 bytes
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5.4
Address C0A6H
Clock Divide Register
D15 D14 D13 D12 D11 D10
0
0
0
0
0
D9
D8
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
0
D[1:0]
CLKD[1:0]
D1
D0
CLKD1 CLKD0
Clock Divide[1:0].
1 1 : divide by 8
1 0 : divide by 4
0 1 : divide by 2
00:1
Set clock divide register of the image sensor to 1:1.
5.5
Upper Window Height Register
D15 D14 D13 D12 D11 D10
0
0
0
0
0
D[1:0]
5.6
Address C0A8H
D9
D8
D7
D6
D5
D4
D3
D2
0
0
0
0
0
0
0
0
0
WH[9:8]
0
0
0
0
0
D7-0
5.7
D8
0
0
WH[7:0]
D7
D6
0
0
0
0
D11
0
0
D[11:0]
Se401.doc
0
D2
D1
D0
Address C0ACH Read Only
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Packet Count for Frame Memory A.
Packet Count B Register
0
D3
Lower bits of window height.
PA[11:0]
D15 D14 D13 D12
D4
PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
D[11:0]
5.8
D10
D5
WH7 WH6 WH5 WH4 WH3 WH2 WH1 WH0
Packet Count A Register
D15 D14 D13 D12
WH9 WH8
Address C0AAH
D9
0
D0
Upper bits of window height.
Lower Window Height Register
D15 D14 D13 D12 D11 D10
D1
D11
D10
Address C0AEH Read Only
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PB[11:0]
Packet Count for Frame Memory B.
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5.9
Compression Engine Data
Video data from the Compression Engine is transfered to the Se401s SIE by
setting the DMA address, of the chosen endpoint, in the range of 8000h-9fffh.
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6
Programmable Timers.
The SE401 ASIC Controller has two built in programmable timers that can
provide an interrupt to the SE401 ASIC Engine. The two timers decrement on every
microsecond Clock tick. Interrupt occurs when the timer reaches zero.
A separate Watchdog timer is also provided. The Watchdog timer can also
interrupt the SE401 ASIC processor.
6.1
Timer 0 Count Register
Address C010H
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
D15-0 T15-0 Timer Count value.
6.2
Timer 1 Count Register
Address C012H
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
D15-0 T15-0 Timer Count value
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Watchdog Timer Count & Control Register
D15
0
D14 D13 D12 D11 D10 D9 D8 D7 D6
0
0
0
0
0
D5
D4-3
WT
TO1-0
D2
EP
D1
D0
ENB
RC
0
0
0
0
Address C00CH
D5
D4
D3
D2
WT TO1 TO0 EP
D1
D0
ENB RC
Watchdog Time-out occurred.
Time-out Count:
00
1 msec
01
4 msec
10
16 msec
11
64 msec
Enable Permanent WD timer. If set ='1'
WD timer is always enabled. Cleared only on
Reset.
Enable WD Timer operation when ='1'.
Reset Count. When set = '1'.
Note:
1) Must send a Reset Count (RC), before time-out occurs to avoid Watchdog
going off.
2) The Watchdog Timer overflow causes an internal processor reset. The
Processor can read the WT bit after exiting reset to determine if the WT bit is set.
If it is set, a watch dog timeout occurred.
3) The WT value will be cleared on the next external reset.
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7
General Purpose I/O.
A number of General Purpose Digital I/O (GPIO) pins are supported by the
SE401. Some of these pins can be assigned to special functions. However, when not
configured as special functions, the pins can be used as GPIO
The following registers are used for all pins configured as GPIO. The outputs are
enabled in the I/0 Control registers. Note that the output Data can be read back in the
Output Data Register even though the outputs are not enabled. (see diagram below).
7.1
I/O Control Register 0
Address C022H
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
E15
E14
D15-0
7.2
E13
E12
E11
E15-0
E10 E9
E7
E6
E5
I/O Control Register 1
E31
E30
E29
D15-0
7.3
E28
E27
D9
E31-16
0
D5-0
0
0
D8
D7
D6
D5
D13
D12
E0
D4
D3
D2
D1
D0
Address C034H
0
E37-32
D14
E1
Enable individual outputs, GPIO 31-16
Logic '1' enables.
D9
D8
D7
D6
0
0
0
0
D5
D4
D3
D2
D1
D0
E37 E36 E35 E34 E33 E32
Enable individual outputs, GPIO 37-32
Logic '1' enables.
I/O Output Data Register 0
D15
E2
E26 E25 E24 E23 E22 E21 E20 E19 E18 E17 E16
D15 D14 D13 D12 D11 D10
0
E3
Address C028H
I/O Control Register 2
0
E4
Enable individual outputs, GPIO 15-0.
Logic '1' enables.
D15 D14 D13 D12 D11 D10
7.4
E8
D11
D10
Address C01EH
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 O0
D15-0
Se401.doc
O15-0
Output Pin Data
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7.5
D15
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I/O Output Data Register 1
D14
D13
D12
D11
D10
Address C024H
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
O31 O30 O29 O28 O27 O26 O25 O24 O23 O22 O21 O20 O19 O18 O17 O16
D31-16
7.6
O31-16
Output Pin Data
I/O Output Data Register 2
Address C030H
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
0
0
0
0
0
0
0
0
0
0
D5-0
7.7
O37-32
D5
D4
D3
D2
D1
D0
O37 O36 O35 O34 O33 O32
Output Pin Data
I/O Input Data Register
0
Address C020H
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I15
I14
I13
D15-0
7.8
I11
I15-0
I10
I9
I8
I7
I6
I5
I4
I3
I2
I1
I0
Input Pin data.
I/O Input Data Register
1
Address C026H
D15 D14 D13 D12 D11 D10
D9
I31
I25 I24 I23 I22 I21 I20 I19 I18 I17 I16
I30
I29
D31-16
7.9
I12
I28
I27
I31-16
I26
D5-0
Se401.doc
0
0
I37-32
D6
D5
2
D15 D14 D13 D12 D11 D10
0
D7
D4
D3
D2
D1
D0
Input Pin data.
I/O Input Data Register
0
D8
0
0
Address C032H
D9
D8
D7
D6
0
0
0
0
D5
D4
D3
D2
D1
D0
I37 I36 I35 I34 I33 I32
Input Pin data.
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ENB
(from I/O Control
Register
I/O Pin
Output Data (from
Output data Reg)
Readback of
Output Data reg.
Input Data (To
Input Data Reg)
Internal I/O Register Data Path
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Interrupts
INTERRUPT
NUMBER
VECTOR
ADDRESS
INTERRUPT TYPE
0
0000H
Timer0
1
2
0002H
0004H
Timer1
GP IRQ0
3
4
0006H
0008H
GP IRQ1
UART TX
5
000AH
UART RX
6
7
000CH
000EH
AD Convert
USB Reset
8
0010H
USB SOF
9
10
0012H
0014H
USB Endpoint0 No Error
USB Endpoint0 Error
11
12
0016H
0018H
USB Endpoint1 No Error
USB Endpoint1 Error
13
001AH
USB Endpoint2 No Error
14
15
001CH
001EH
USB Endpoint2 Error
USB Endpoint3 No Error
16
0020H
USB Endpoint3 Error
17
18
0022H
0024H
SPORT TX
SPORT RX
19
20
0026H
0028H
VID COMPRESSION CHA
VID COMPRESSION CHb
Note: 1) The SOF interrupt is generated when there is an SOF incoming on the USB.
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Interrupt Enable Register
Address C00EH
D15 D14 D13 D12 D11 D10 D9 D8
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
JG
SPRT
USB
0
D7
D6
D5
D4
JG
SPRT
USB
0
D3
D2
UART GP
D1 D0
T1
T0
JANGU Interrupt enable
SPORT Interrupt enable
USB Interrupt enable.
Not used.
UART Interrupt enable.
General Purpose I/O pins Interrupt enables.
Timer1 Interrupt Enable.
Timer0 Interrupt Enable.
UART
GP
T1
T0
Note: User must initialize this register.
8.2
GPIO Interrupt Control Register
D15 D14 D13 D12 D11 D10
0
0
D3
D2
D1
D0
0
0
P1
E1
P0
E0
0
0
Address C01CH
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
P1
E1
P0
E0
IRQ1 polarity is rising edge if “1”, falling edge if “0”.
Enable IRQ1 if set to “1”.
IRQ0 polarity is rising edge if “1”, falling edge if “0”.
Enable IRQ0 if set to “1”.
Note: The interrupts can be enabled for “Suspend mode” by the Power Down Register
or enabled for interrupts by the Interrupt Enable Register.
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9
Memory Interface
The SE401 ASIC Controller provides a 16 bit Memory interface that can support
a wide variety of external RAM and ROM.
The SE401 ASIC Controller memory space is byte addressable and is divided as
follows:
FUNCTION
ADDRESS
Internal Ram
0000 - 0BFFH
External Ram
0C00 - 7FFFh
JANGU DMA
8000 - 9FFFh
Memory Mapped Registers
C000 - C0FFh
External ROM
C100 – CFFFh
Shared INT/EXTROM
D000 - DFFFh
Internal ROM
E000 - FFFFh
Each External memory space can be 8 or 16 bits wide, and can be programmed to have
up to 7 wait states.
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9.1
Memory Control Register.
D15 D14 D13 D12
0
0
0
Address C03EH
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
RA
RO
DB
0
D2
D1
D0
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RA
RO
DB
1 Wait state for internal RAM if set to ‘ 1’ . Default: ‘ 0’
1 Wait state for internal ROM if set to ‘ 1’ . Default: ‘ 1’
DEBUG mode is enabled if set to ‘ 1’ . Internal
address bus is echoed to external address pins.
Default: ‘ 1’
Extended Memory Control Register.
D15 D14 D13 D12
SRM 2CS
D15
CR
0
D11
D10
D9
D8
0
0
0
0
Address C03AH
D7
D6
D5
D4
D3
D2
D1
D0
ROW RO2 RO1 RO0 RAW RA2 RA1 RA0
Selectable ROM. If set to ‘ 1’ , address space
D000h – DFFFh is mapped to the external
Rom. Defaults to ‘ 0’ .
D14
2CS
For using 2 external 8 bit RAMS if set to ‘ 1’
Tie nBHE pin to high SRAM CS. And nXRAMSEL
To low SRAM CS. Defaults to ‘ 1’ .
D13
CR
Clean Read. When set to ‘ 1’ , read data from
external memory is latched. Defaults to ‘ 0’ .
D12-8
0’ s
Unused
D7
ROW
External ROM Width ('0' = 16, '1' = 8). Defaults to ‘ 0’ .
D6-4
RO2-0
External ROM wait states (0 - 7)
D3
RAW
External RAM Width ('0' = 16, '1' = 8). Defaults to ‘ 0’ .
D2-0
RA2-0
External RAM Wait States (0 - 7)
Note: 1) The default wait state setting on power up or reset is 7 wait states for all.
Se401.doc
SRM
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10 SPORT Synchronous Serial Port
Syncronous port for communication with Telecom chips or A/D controllers.
10.1 TX DMA Address Register
Address 0144H
Pointer to memory buffer location for SPORT TX data to be taken from.
10.2 TX DMA Count Register
Indicates the size in words for the DMA.
Address 0146H
10.3 RX DMA Address Register
Address 0140H
Pointer to memory buffer location for SPORT Receive data to be placed.
10.4 RX DMA Count Register
Indicates the size in words for the DMA.
Se401.doc
Address 0142H
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10.5 SPORT Control Register
Address C070H
D15 D14 D13 D12 D11 D10 D9 D8 D7
0
0
0
0
0
D6
RXE
D5
TXE
D4-D2
FS2-0
D1
IFS
D0
0
0
0
0
D6
D5
D4
D3
D2
D1
D0
RXE TXE FS2 FS1 FS0 IFS ENB
RX enable = ‘ 1’ . Set this when ready to RX data
Clears to ‘ 0’ when a DMA set is RX’ ed.
TX enable = ‘ 1’ . Set this when ready to TX data
Clears to ‘ 0’ when a DMA set is TX’ ed.
Frame Size. Used only if bit1 = ‘ 1’
FS2
0
FS1
0
FS0
0
Frame Size in words
1
0
0
1
2
0
0
1
1
0
1
4
8
1
1
0
0
0
1
16
32
1
1
0
64
1
1
1
128
Internal Frame SYNC if = ‘ 1’ . External Frame
SYNC pin is used if =’ 0’
ENB
SPORT Enable = ‘ 1’ .
Notes:
1) Sport interrupts are generated when corresponding DMA’ s are done.
2) The external FS pin (GPIO16) should be pulled down if internal FS is used.
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11 USB Universal Serial Bus
The USB controller contains a number of registers that provide overall control
and status functions for USB transactions. The first set of registers are for overall
control and status functions, while the second group is dedicated to specific endpoint
functions.
Communication and data flow on the USB is implemented using endpoints.
These uniquely identifiable entities are the terminals of communication flow between a
USB host and USB devices. Each USB device is composed of a collection of
independently operating endpoints. Each endpoint has a unique identifier: the endpoint
number. See USB specification v1.1. Sec 5.3.1.
The SE401 ASIC Controller supports four endpoints, numbered 0 - 3. Endpoint 0
is the default pipe, and is used to initialize and manipulate the device. It also provides
access to the device's configuration information, and supports control transfers.
Endpoint 1, 2, and Endpoint 3 support interrupt transfers, bulk transfers, or isochronous
transfers.
11.1 Control and Status Register
D7 D6 D5
0
D0
D1
D2
D3
D4
D5
Address C080H
D4 D3 D2
D1
D0
0 URL WK UA US URA UE
UE
USB Enable = '1', Overall USB enable/disable bit.
URA USB Reset = '1', USB received Reset command currently active.
US
USB SOF = '1', USB received SOF command.
Cleared when Frame Number Register read.
UA
USB Activity = '1', Activity Seen. Set to ‘ 1’ to clear.
WK Send USB remote wakeup command while = '1'.
URL USB Reset Latch = '1', USB received Reset command. Set to ‘ 1’ to
clear.
Note: 1) Per USB spec, suspend state should be entered if after 3mS there is no
activity (UA).
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Frame Number Register
Address C082H
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
S10 S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
The Frame Number Register contains the 11 bit ID Number of last SOF received by the
device from the USB Host.
D15-D11
set to all zeros.
D10-D0
S10-S0.
SOF ID Number of last SOF Received.
11.3 USB Address Register
Address C084H
D7 D6 D5 D4 D3 D2 D1 D0
0
A6
A5
A4
A3
A2
A1
A0
Address Register holds the USB address of the device assigned by the Host.
Initialized to address 0H on Power up.
D7
set to logic '0''s always.
D6-D0
USB Address of device after assignment by Host.
11.4 Command Done Register (write only)
Address C086H
D7 D6 D5 D4 D3 D2 D1 D0
0
D0
D1
D7-D2
Se401.doc
0
0
M0
M1
0
0
0
M1 M0
Command done Mode bit 1
Command done Mode bit 1
M1
0
M0
0
0
1
1
0
1
1
function
Sets command done for In
or Out status phase.
Sets command done for
Out status phase only.
Sets command done for In
status phase only.
undefined
Not assigned
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11.5 Endpoint 0 Control and Status Register
Address C090H
11.6 Endpoint 1 Control and Status Register
Address C092H
11.7 Endpoint 2 Control and Status Register
Address C094H
11.8 Endpoint 3 Control and Status Register
Address C096H
The Endpoint N Control and Status Register when written has the following functions
assigned:
BIT
POSITION
BIT NAME
0
Arm
1
Enable
2
Dir
3
ISO
Stall
4
FUNCTION
Allows enabled transfers when set = '1'.
Cleared to '0' when transfer is complete.
When set = '1' allows transfers to this endpoint. When set ='0' USB
transactions are ignored. If enable = '1' and Arm = '0'
endpoint will return NAK's to USB transmissions.
When set = '1' transmit to Host (IN). When '0' receive from Host (OUT).
When set = '1' allows isochronous mode for this endpoint.
When set = '1' sends Stall in response to next request on this endpoint.
5
Zero Length When set = '1' sends a zero length packet.
6
Not Defined
Not Defined
7
Note: 1) For Endpoint 0, ISO is not needed, and has a different function, which allows
independent stall’ s on only IN or OUT transactions. If ISO is ‘ 1’ , then stall=’ 0’ will stall
only IN’ s and stall=’ 1’ will stall only OUT’ s.
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Reading the Endpoint N Control and Status Register provides Status information
relative to the packet which has been received or transmitted. The register is defined as
follows:
BIT
POSITION
BIT
NAME
0
Arm
1
FUNCTION
If set = '1' indicates the endpoint is armed.
Enable If set = '1' indicates the endpoint is enabled.
2
Dir
Direction bit. If = '1' set to transmit to Host (IN). '0' = set receive from Host (OUT).
3
ISO
4
Stall
If set = '1' isochronous mode selected for this endpoint.
If set = '1' endpoint will send stall on USB when requested.
5
Zero When set = '1' sends a zero length packet.
Length
6
Not used
7
Not used
8
Not used
9
Not used
10
Not used
11
Not used
12
Not used
13
Setup
14
Error
15
Done
If set = '1' indicates a Setup packet received.
If set = '1', indicates an error condition occurred on last transaction for this
endpoint.
If set = '1', Done indicates transaction completed. Arm Bit is cleared to '0' when
Done sets.
Endpoint 0 is set up as a control endpoint. The DIR bit is read-only, and indicates the
direction of the last completed transaction. If the direction is incorrect, it is the
firmware’ s responsibility to handle the error. On other endpoints, DIR is written, and if
the direction of the transfer does not match DIR, then the transaction is ignored (as if
not enabled).
At the end of any transfer to an armed and enabled endpoint (with the correct DIR bit),
an interrupt occurs, and vectors to a different location depending upon whether an error
occurred or not. At the end of this transfer, the corresponding endpoint is disarmed,
and the toggle bit is advanced if no error occurred. If a packet is received with an
incorrect toggle state, it is ignored (so that if the host misses an ACK and resends data,
we only see the data once).
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11.9 Endpoint 0 Address Register
Address 0120H
Pointer to memory buffer location for USB reads and writes to Endpoint N.
11.10 Endpoint 1 Address Register
Address 0124H
Pointer to memory buffer location for USB reads and writes to Endpoint N.
11.11 Endpoint 2 Address Register
Address 0128H
Pointer to memory buffer location for USB reads and writes to Endpoint N.
11.12 Endpoint 3 Address Register
Address 012CH
Pointer to memory buffer location for USB reads and writes to Endpoint N.
11.13 Endpoint 0 Count Register
Address 0122H
Indicates the maximum packet size for the Endpoint.
11.14 Endpoint 1 Count Register
Address 0126H
Indicates the maximum packet size for the Endpoint.
11.15 Endpoint 2 Count Register
Address 012AH
Indicates the maximum packet size for the Endpoint.
11.16 Endpoint 3 Count Register
Address 012EH
Indicates the maximum packet size for the Endpoint.
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12 Physical Section
12.1 Pinout for 100 LQFP Package
Pin Number
Direction
Dedicated
Mode
1
IN
ICVDD
2
IN/OUT
GPIO35
GPIO35
3
IN/OUT
GPIO36
GPIO36
4
IN/OUT
GPIO32
GPIO32
5
OUT
Dram Ras
GPIO31
6
IN/OUT
GPIO30
GPIO30
7
OUT
CAS
Dram Cas
GPIO29
8
OUT
DR_WR
Dram Write
GPIO28
9
OUT
DR_OE
Dram Output Enable
GPIO27
10
IN/OUT
GPIO26
GPIO26
11
IN/OUT
GPIO25
GPIO25
12
IN/OUT
GPIO37
GPIO37
13
IN
GND
Gnd
14
IN
VD0
Video Data 0
GPIO0
15
IN
VD1
Video Data 1
GPIO1
16
IN
VD2
Video Data 2
GPIO2
17
IN
VD3
Video Data 3
GPIO3
18
IN
VD4
Video Data 4
GPIO4
19
IN
VD5
Video Data 5
GPIO5
20
IN
VD6
Video Data 6
GPIO6
21
IN
VD7
Video Data 7
GPIO7
22
OUT
UTXD
23
IN/OUT
GPIO33
24
IN/OUT
GPIO34
25
IN/OUT
VP
USB + Pin
26
IN/OUT
VM
USB - Pin
27
IN
UGND
USB Gnd
28
IN
UVDD
USB VDD
29
IN/OUT
VP2
USB + Pin
30
IN/OUT
VM2
USB - Pin
31
IN
VDD
VDD
32
OUT
RCLK
Processor Clock
33
OUT
JGCLK
Jangu Clock
Se401.doc
RAS
Description
Programmable IO Mode (If Dedicated
is not selected.)
VDD
Uart Txd
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Description
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Pin Number
Direction
Dedicated
Mode
Programmable IO Mode (If Dedicated
is not selected.)
34
IN
RXD
35
IN
HSYNC
Horizonal Sync
GPIO8
36
IN
VSYNC
Vertical Sync
GPIO9
37
IN
IRQ0
Edge sens. Interrupt
GPIO10
38
IN
IRQ1
Edge sens. Interrupt
GPIO11
39
OUT
MCLK
Video Clock
GPIO12
40
IN/OUT
GPIO13
GPIO13
41
IN/OUT
GPIO14
GPIO14
42
IN/OUT
GPIO15
GPIO15
43
IN/OUT
BIOS I2C SDA
GPIO16
44
IN/OUT
GPIO
BIOS I2C SCL
GPIO17
45
IN/OUT
GPIO
BIOS USB PULLUP
GPIO18
46
IN
OGND
Gnd
47
IN
CLK
48
OUT
X2
12MHz Crystal Output
49
IN
A15
A15
50
IN
OVDD
VDD
51
IN
ICVDD
VDD
52
OUT
A14
A14
53
OUT
A0
A0
54
OUT
nXBHE
55
IN
IGND
UART RXD
Clock input
External Byte High Enable (active LO)
Gnd
56
OUT
57
IN/OUT
58
IN
SPRT_CLK
59
IN
SPRT_RXD Sports Receive Data
GPIO21
60
OUT
SPRT_TXD Sports Transmit Data
GPIO22
61
IN
SPRT_TSC Sports Time Slot
GPIO23
62
IN/OUT
SPRT_FS
63
OUT
nXRD
External Memory Read (active LO)
64
OUT
nXWR
External Memory Write (active LO)
Se401.doc
nXRAMSEL External RAM CS (active LO)
GPIO19
GPIO19
Sports clock
GPIO20
Sports Frame Sync
GPIO24
36
Aox Incorporated - Proprietary and Confidential
Pin Number
Direction
65
OUT
66
IN
nRESET
67
IN
nTST
Test Pin, Disconnect for Normal
Operation.
68
IN
OGND
Gnd
69
OUT
XA_1
External Address Pins
70
OUT
XA_2
External Address Pins
71
OUT
XA_3
External Address Pins
72
OUT
XA_4
External Address Pins
73
OUT
XA_5
External Address Pins
74
OUT
XA_6
External Address Pins
75
OUT
XA_7
External Address Pins
76
OUT
XA_8
External Address Pins
77
OUT
XA_9
External Address Pins
78
OUT
XA_10
External Address Pins
Se401.doc
Dedicated
Mode
Description
99-1-22 7:28 AM
Programmable IO Mode (If Dedicated
is not selected.)
nXROMSEL External ROM CS (active LO)
Reset Pin
37
Aox Incorporated - Proprietary and Confidential
Se401.doc
99-1-22 7:28 AM
Pin Number
Direction
Dedicated
Mode
Description
79
OUT
XA_11
External Address Pins
80
OUT
XA_12
External Address Pins
81
OUT
XA_13
External Address Pins
82
IN
CGND
Gnd
83
IN/OUT
XD_0
External Data Pins
84
IN/OUT
XD_1
External Data Pins
85
IN/OUT
XD_2
External Data Pins
86
IN/OUT
XD_3
External Data Pins
87
IN/OUT
XD_4
External Data Pins
88
IN/OUT
XD_5
External Data Pins
89
IN/OUT
XD_6
External Data Pins
90
IN/OUT
XD_7
External Data Pins
91
IN/OUT
XD_8
External Data Pins
92
IN/OUT
XD_9
External Data Pins
93
IN/OUT
XD_10
External Data Pins
94
IN/OUT
XD_11
External Data Pins
95
IN/OUT
XD_12
External Data Pins
96
IN/OUT
XD_13
External Data Pins
97
IN
OGND
GND
98
OUT
XD_14
External Data Pins
99
OUT
XD_15
External Data Pins
100
IN
OVDD
Vdd
38
Aox Incorporated - Proprietary and Confidential
99-1-22 7:28 AM
13
14 Testing Modes
This document describes the various test modes of the SE401
device for use by KLSI during manufacturing test.
1. All test modes are activated by setting n_test low.
2. Nand-tree: Set n_test=0 . This pin is not in the nand-tree.
xa[13] is nand tree out.
3. USB: Set n_test=0 and io[31:29] NE "100" ( or set io[31:29] = "111".
xa[1] is USB (instance txcv1) output.
xd[1] and xd[0] determine which USB output appears on xa pin:
xd[1] xd[0]
Function
----- -----------0
0
Select rxdp
0
1
Select rxdm
1
0
Select rxd
1
1
-Unusedxd[2] is USB stbyd input for USB block. Setting xd(2) high puts diff amp in
standby.
xd[3] is USB stbys input for USB block. Setting xd(3) low puts single ended
amps in standby.
4. ARAM1024X8C16
assert n_tst and io[31:29] = "010"
address is input on io[9:0].
data in is input on io[19:12].
data out is output on xd[7:0].
csn is rxd.
rwn is io[28].
5. ARAM1536X8C16 (2)
assert n_tst and io[31:29] = "100"
address is input on io[10:0].
data in is input on io[27:12].
data out is output on xd[15:0].
csn is rxd.
rwn is io[28].
Se401.doc
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Aox Incorporated - Proprietary and Confidential
99-1-22 7:28 AM
6. ROM test
assert n_tst and io[31:29] = "101"
test address is input on io[11:0].
tclk is io[14]
TCSN is io[15].
rom data out is xd[15:0].
7. PLL test
assert n_tst and io[34:32] = "101"
test1 is io[36]
test2 is io[37].
dly_line out is xa[2]
connect_108 out is xa[3].
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40