Data Sheet No. PD60162-N
IR2106(4) (S)
HIGH AND LOW SIDE DRIVER
Features
• Floating channel designed for bootstrap operation
•
•
•
•
•
•
•
Product Summary
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
Gate drive supply range from 10 to 20V (IR2106(4))
Undervoltage lockout for both channels
3.3V, 5V and 15V input logic compatible
Matched propagation delay for both channels
Logic and power ground +/- 5V offset.
Lower di/dt gate driver for better noise immunity
Outputs in phase with inputs (IR2106)
VOFFSET
600V max.
IO+/120 mA / 250 mA
VOUT
10 - 20V
7 - 20V
(IR2106(4))
ton/off (typ.)
Delay matching
(IR2186)
180 ns
50 ns
Description
The IR2106(4)(S) are high voltage, high speed power
MOSFET and IGBT drivers with independent high and
low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction. The logic input is
compatible with standard CMOS or LSTTL output,
down to 3.3V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used
to drive an N-channel power MOSFET or IGBT in the
high side configuration which operates up to 600 volts.
Packages
8 Lead SOIC
14 Lead SOIC
8 Lead PDIP
14 Lead PDIP
Typical Connection
up to 600V
VCC
VCC
VB
HIN
HIN
HO
LIN
LIN
VS
COM
LO
IR2106
(Refer to Lead Assignments for correct pin
configuration). This/These diagram(s) show
electrical connections only. Please refer to our
Application Notes and DesignTips for proper
circuit board layout.
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TO
LOAD
up to 600V
HO
VCC
V CC
VB
HIN
HIN
VS
LIN
LIN
V SS
V SS
TO
LOAD
COM
LO
IR21064
1
IR2106(4) (S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol
High side floating absolute voltage
VS
Min.
Max.
-0.3
625
Units
High side floating supply offset voltage
VB - 25
VB + 0.3
VHO
High side floating output voltage
VS - 0.3
VB + 0.3
VCC
Low side and logic fixed supply voltage
-0.3
25
VLO
Low side output voltage
-0.3
VCC + 0.3
VIN
Logic input voltage
VSS - 0.3
VCC + 0.3
VSS
Logic ground (IR21064 only)
VCC - 25
VCC + 0.3
dVS/dt
PD
RthJA
2
Definition
VB
Allowable offset supply voltage transient
Package power dissipation @ TA ≤ +25°C
Thermal resistance, junction to ambient
—
50
—
1.0
(8 lead SOIC)
—
0.625
(14 lead PDIP)
—
1.6
(8 lead PDIP)
(14 lead SOIC)
—
1.0
(8 lead PDIP)
—
125
(8 lead SOIC)
—
200
(14 lead PDIP)
—
75
(14 lead SOIC)
—
120
TJ
Junction temperature
—
150
TS
Storage temperature
-50
150
TL
Lead temperature (soldering, 10 seconds)
—
300
V
V/ns
W
°C/W
°C
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IR2106(4) (S)
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential.
Symbol
Definition
VB
High side floating supply absolute voltage IR2106(4)
VS
High side floating supply offset voltage
Min.
Max.
VS + 10
VS + 20
Note 1
600
VHO
High side floating output voltage
VS
VB
VCC
Low side and logic fixed supply voltage IR2106(4)
10
20
VLO
Low side output voltage
0
VCC
VIN
Logic input voltage
VSS
VCC
VSS
Logic ground (IR21064 only)
-5
5
Ambient temperature
-40
125
TA
Units
V
°C
Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip
DT97-3 for more details).
Dynamic Electrical Characteristics
VBIAS (V CC, VBS) = 15V, VSS = COM, C L = 1000 pF, TA = 25°C.
Symbol
Definition
Min.
Typ.
—
220
300
VS = 0V
Turn-off propagation delay
—
200
280
VS = 0V or 600V
Delay matching, HS & LS turn-on/off
—
0
30
tr
Turn-on rise time
—
150
220
VS = 0V
tf
Turn-off fall time
—
50
80
VS = 0V
ton
Turn-on propagation delay
toff
MT
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Max. Units Test Conditions
nsec
3
IR2106(4) (S)
Static Electrical Characteristics
VBIAS (VCC , VBS) = 15V, VSS = COM and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are
referenced to VSS/COM and are applicable to the respective input leads. The VO, IO and Ron parameters are referenced to
COM and are applicable to the respective output leads: HO and LO.
Symbol
Definition
VIH
Logic “1” input voltage (IR2106(4))
VIL
Min. Typ. Max. Units Test Conditions
2.9
—
—
VCC = 10V to 20V
VCC = 10V to 20V
Logic “0” input voltage (IR2106(4))
—
—
0.8
VOH
High level output voltage, VBIAS - VO
—
0.8
1.4
VOL
Low level output voltage, VO
—
0.3
0.6
IO = 20 mA
V
IO = 20 mA
ILK
Offset supply leakage current
—
—
50
VB = VS = 600V
IQBS
Quiescent VBS supply current
20
60
150
VIN = 0V or 5V
IQCC
Quiescent VCC supply current
50
120
240
IIN+
Logic “1” input bias current
VIN = 5V (IR2106(4))
IIN-
VBSUV+
VCCUV-
—
5
20
Logic “0” input bias current
VIN = 0V (IR2106(4))
VCCUV+
VIN = 0V or 5V
µA
VCC and VBS supply undervoltage positive going
—
1
2
8.0
8.9
9.8
7.4
8.2
9.0
threshold
VCC and VBS supply undervoltage negative going
VBSUV-
threshold
VCCUVH
Hysteresis
0.3
0.7
—
Output high short circuit pulsed current
120
200
—
V
VBSUVH
IO+
mA
IO-
4
Output low short circuit pulsed current
250
350
—
VO = 0V,
PW ≤ 10 µs
VO = 15V,
PW ≤ 10 µs
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IR2106(4) (S)
Functional Block Diagrams
VB
UV
DETECT
IR2106
HO
R
HIN
VSS/COM
LEVEL
SHIFT
HV
LEVEL
SHIFTER
R
PULSE
FILTER
Q
S
VS
PULSE
GENERATOR
VCC
UV
DETECT
LIN
VSS/COM
LEVEL
SHIFT
LO
DELAY
COM
VB
UV
DETECT
IR21064
HO
R
HIN
VSS/COM
LEVEL
SHIFT
HV
LEVEL
SHIFTER
R
PULSE
FILTER
Q
S
VS
PULSE
GENERATOR
VCC
UV
DETECT
LIN
VSS/COM
LEVEL
SHIFT
DELAY
LO
COM
VSS
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5
IR2106(4) (S)
Lead Definitions
Symbol Description
HIN
Logic input for high side gate driver output (HO), in phase
LIN
Logic input for low side gate driver output (LO), in phase
VSS
Logic Ground (IR21064 only)
VB
High side floating supply
HO
High side gate drive output
VS
High side floating supply return
VCC
Low side and logic fixed supply
LO
Low side gate drive output
COM
Low side return
Lead Assignments
VB
8
1
HIN
HO
7
2
3
LIN
VS
6
4
COM
LO
5
1
VCC
2
1
4
8
HIN
HO
7
LIN
VS
6
COM
LO
5
8 Lead PDIP
8 Lead SOIC
IR2106
IR2106S
VCC
14
1
14
VCC
2
HIN
VB
13
2
HIN
VB
13
3
LIN
HO
12
3
LIN
HO
12
VS
11
4
VS
11
4
6
3
VB
VCC
5
VSS
10
5
VSS
10
6
COM
9
6
COM
9
7
LO
8
7
LO
8
14 Lead PDIP
14 Lead SOIC
IR21064
IR21064S
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IR2106(4) (S)
Case Outlines
01-6014
01-3003 01 (MS-001AB)
8 Lead PDIP
D
DIM
B
5
A
F OOT PRINT
6
8
7
6
5
H
E
0.25 [.010]
1
2
3
A
4
6.46 [.255]
MIN
.0532
.0688
1.35
1.75
A1 .0040
3X 1.27 [.050]
8X 1.78 [.070]
e1
MAX
.0098
0.10
0.25
b
.013
.020
0.33
0.51
c
.0075
.0098
0.19
0.25
D
.189
.1968
4.80
5.00
E
.1497
.1574
3.80
4.00
e
.050 BAS IC
1.27 BAS IC
.025 BAS IC
0.635 BAS IC
e1
6X e
MILLIMETERS
MAX
A
8X 0.72 [.028]
INCHES
MIN
H
.2284
.2440
5.80
6.20
K
.0099
.0196
0.25
0.50
L
.016
.050
0.40
1.27
y
0°
8°
0°
8°
K x 45°
A
C
y
0.10 [.004]
8X b
0.25 [.010]
A1
8X L
C A B
NOT ES:
1. DIMENS IONING & T OLERANCING PE R ASME Y14.5M-1994.
2. CONT ROLLING DIMENSION: MILLIMET ER
3. DIMENS IONS ARE SHOWN IN MILLIME TE RS [INCHES].
4. OUT LINE CONF ORMS T O JEDEC OUTLINE MS-012AA.
8 Lead SOIC
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8X c
7
5 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROT RUS IONS NOT TO EXCEED 0.15 [.006].
6 DIMENS ION DOES NOT INCLUDE MOLD PROT RUSIONS .
MOLD PROT RUS IONS NOT TO EXCEED 0.25 [.010].
7 DIMENS ION IS T HE LENGT H OF LEAD FOR SOLDERING T O
A SUBST RATE.
01-6027
01-0021 11 (MS-012AA)
7
IR2106(4) (S)
14 Lead PDIP
14 Lead SOIC (narrow body)
8
01-6010
01-3002 03 (MS-001AC)
01-6019
01-3063 00 (MS-012AB)
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IR2106(4) (S)
HIN
LIN
50%
50%
HIN
LIN
ton
toff
tr
90%
HO
LO
HO
LO
Figure 1. Input/Output Timing Diagram
HIN
LIN
10%
tf
90%
10%
Figure 2. Switching Time Waveform Definitions
50%
50%
LO
HO
10%
MT
MT
90%
LO
HO
Figure 3. Delay Matching Waveform Definitions
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 5/12/2001
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9