Lab 5
Model of elevator controller with direction detection
The purpose of this lab is to learn to simulate designs written in different languages.
During this lab you are going to simulate design of elevator controller (specification from
lab 4), where design of controller is written in Verilog and testbench is written in VHDL.
ModelSim simulator allows you to do that without using any intermediate language for
connecting design parts. If you want to instantiate Verilog into VHDL the following rules
must be applied:
 Verilog module is used as entity aspect in VHDL, therefore you need just to
specify module name instead of an entity name;
 All the ports in Verilog must be named;
 Default port types are:
o std_logic
o std_logic_vector
optionally, you can choose:
o bit and bit_vector
o vl_logic and vl_logic_vector;
 The VHDL identifiers for the component name, port names and generic names
are the same as Verilog identifiers for the module name, port names and
parameter names;
 A generic clause is generated if the module has parameters. The generic type is
determined by the parameter’s initial value as following:
Parameter value
Generic type
integer
Integer
real
Real
string literal
String
Examples
Verilog parameter
parameter p1=1-3;
parameter p2=3.0;
parameter p3=”Hello”;
VHDL generic
p1: integer:=-2;
p2: real:=3.000000;
p3: string:=”Hello”;
 A port clause is generated if the module has ports. A corresponding VHDL port
is defined for each Verilog port. You can set the VHDL port type to bit,
std_logic, vl_logic. If the Verilog port has a range, then the VHDL port type is
bit_vector, std_logic_vector or vl_logic_vector. If the range does not depend on
parameters, then the vector type will be constrained accordingly otherwise it will
be unconstrained.
Examples
Verilog port
VHDL port
input p1;
p1: in std_logic;
output [7:0] p2;
p2: out std_logic_vector(7 downto 0);
output [4:7] p3;
p3: out std_logic_vector(4 to 7);
inout [width-1:0] p4;
p4: inout std_logic_vector;
 To put time units of Verilog code correctly use either:
o `timescale {the smallest unit of time you use}/{resolution} in your
Verilog code before the module declaration
Example: `timescale 1 s/10 ms
o or during loading the simulation specify option –t to fix the smallest time
unit of your design.
Example: vsim –t 1 sec work.t_elevator
General block scheme of whole design is the given bellow:
Testbench: t_elevator.vhd
DOORS_OPENED
BUTTONS_IN
DIR_UP
BUTTONS_OUT_UP
Elevator controller
elevator.v
DIR_DN
MOTOR
BUTTONS_OUT_DN
FLOOR_NUM
For this task you need ready-made model of elevator controller written in Verilog
(supposed the lab 4 is done) – design elevator.v. To test your design correctness you need
to use testbench written in VHDL, take the testbench from lab 3 t_elevator_fnc.vhd and
modify it in order to control new design with more functionality. You need to add
additional output to procedure CALL_ELEVATOR to distinguish between
BUTTONS_OUT_UP and BUTTONS_OUT_DN and control logic to the procedure,
where you check either “out call” is lower than “in call” then you assign your “out call”
to BUTTONS_OUT_UP, otherwise to BUTTONS_OUT_DN. Simulate all the design
and make sure that you Verilog elevator controller model is correct with the help of
VHDL testbench.
Task:



instantiate Verilog model of elevator controller (ready-made design from lab 4)
into given VHDL testbench t_elevator_fnc.vhd;
modify the testbench t_elevator_fnc.vhd so that it would be possible to control
functionality of more advanced design;
simulate your mixed design in order to get correct behaviour of elevator.
Requirements:


Code of testbench with comments added to the report;
Waveform picture added to the report;