Supplemental Documentation
Critical Path Delay
OutALU0
O0
OutALU12
O12
CLK
A0 input before register
A0 input after register
OutALU15
O15
Cout
The input transition is A<0> = 0 to 1, A<1:15>=0, B<0:15> = 1 for this simulation. This produces the
worst case delay in the ALU. At the second rising clock, A0 gets registered and takes a long time to rise due to
the huge capacitance that it has to drive. The capacitances are contributed by all the operations in out ALU
except for the multiplier, which was disabled. Due to this slow rise in A0, the output of the ALU takes a long to
recognize the input change. With all these factors, the delay from the second rising clock edge to OutALU15 is
18.33949 ns.
Power Simulation
A9
B9
ALUout9
Out9
Out8
A8
ALUout8
B8
Out7
A7
ALUout7
B7
Out6
A6
ALUout6
B6
CarryOut
i(“VDALU:P”)
vdd_alu
power
clk
The first figure displays the requested inputs and outputs to be graphed. The first column represents Ain
bits from 9 to 6. The second column represents Bin bits from 9 to 6. The third column represents the ALUOut
bits from 9 to 6, and the fourth column represents the output bits from 9 to 6, with the carry out being
represented as the very last graph. Due to the scaling of the image, it may be hard to see the scaling of the axes.
All of the y-axes go from –1V to 6V, while the x-axes go from 0 to 800ns.
The second figure details the power consumption of the ALU block when simulated with the specified
values. The first section of the graph shows the current consumed by the ALU during the simulation. From this,
you see that the current going through is a negative current, thus it is current being consumed by the ALU. The
second section of this graph plots the value of the ALU's voltage source. This source remains at +5V throughout.
The third portion of the graph shows the clock that is driving this circuit. The last section of the graph shows the
power being consumed by the ALU. This is shown by multiplying the voltage through the ALU by the current
being consumed by the ALU. The Energy is 1.248221e-8 J, and the power we have calculated is the average
value of this graph, which we have calculated to be .0156 W.
. Arbitrary Function Simulation
CLK
A6
A7
O12
O15
The inputs A and B to for the multiplier were 11000000 => 192. The result should change only the 15th
bit and the 12th bit from 0 to 1. The rest of the outputs should remain 0s. The delay was calculated from the
rising edge of the clock to the rising edge of the 15th bit and was measured to be around 0.492ns.
List of Subcircuits
// Subcircuits for use in the AMI06 technology
simulator lang=spectre
//------------------------LAST MODIFIED 4/26/10---------------------------//
/*
1) our wiki things
-2:1MUX = ece3663MUX2to1
-4:1MUX = ece3663MUX4to1
-TGATE = ece3663tgate
-TGATE MUX = ece3663tGateMux
2) class wiki things
-Inverter = ece3663Inverter
-2 input NAND = ece3663NAND2
-2 input NOR = ece3663NOR2
-2 input AND = ece3663AND2
-2 input OR = ece3663OR2
-2 input XOR = ece3663XOR2
-2 input XNOR = ece3663XNOR2
-3 input NAND = ece3663NAND3
-3 input NOR = ece3663NOR3
-3 input AND = ece3663AND3
-3 input OR = ece3663OR3
-F1 = (AB + BC + AC)' = ece3663F1
-F2=(A*B*C+D*(A+B+C))' = ece3663F2
3) things to make our lives easier
-buffer
-MUX8to1
OUR ALU STUFF - 16b
4) register
-posDLatch
-posEdgeRegister
-registor16b
5) adder
-HalfAdder1b
-FullAdder1b
-FullAdder8b
-FullAdder16b
6) subtract=sub_16b
7) AND=and16b
8) OR =or16b
9) Transmission Gate - used instead of pass gate
-tgate16b
10) No OP = backToBackInverter (I have a feeling it's not necessary.)
11) Multiplier
-AndRow
-AdderRow1
-AdderRow2
-Multiplier8
12) Arithmetic Logic Unit
-MUX8_1_17b
-ALU
-DSP
13) leftShift
INCOMPLETE: SHIFTER = leftShift
*/
//---------WIKI-STUFF----FOLLOW CLASS NAMING CONVENTIONS-----------------1------//
// Cell name: ece3663MUX2to1
// Modified by: Team NAND
// improvement: resized NMOS transistors to reduce transmission delay
// 4/23/10 - conformed to class naming convention
//
- fixed sizing mistakes for area and perimeter for NMOS
subckt ece3663MUX2to1 VDD VSS in0 in1 Select out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (VDD VSS Select selectBar) ece3663Inverter wn=wn wp=wp mult=mult
P5 (net15 Select VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P4 (net15 in1 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P3 (out net15 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P2 (out net31 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P1 (net31 in0 VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P0 (net31 selectBar VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N5 (net35 net15 VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N4 (out net31 net35 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N3 (net43 Select VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N2 (net15 in1 net43 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N1 (net31 selectBar net55 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N0 (net55 in0 VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
ends ece3663MUX2to1
//end subcircuit definition
//Cell name: ece3663MUX4to1
// Modified by: Team NAND
// fixed ability to size mux with variables
// 4/23/10 - conformed to class naming convention
subckt ece3663MUX4to1 VDD VSS in00 in01 in10 in11 Select0 Select1 out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (VDD VSS in00 in01 Select0 net75) ece3663MUX2to1 wn=wn wp=wp mult=mult
I1 (VDD VSS in10 in11 Select0 net79) ece3663MUX2to1 wn=wn wp=wp mult=mult
I2 (VDD VSS net75 net79 Select1 out) ece3663MUX2to1 wn=wn wp=wp mult=mult
ends ece3663MUX4to1
//end subcircuit definition
// Cell name: ece3663tgate
// Modified by: Team NAND
// Added ability to control the size of tgate with variables wn and wp.
// 4/23/10 - conformed to class naming convention
//
- fixed wp and wn sizing mistakes
subckt ece3663tgate VDD VSS in pass out
parameters wp=3u wn =1.5u ln=600n lp=600n mult=1
I3 (VDD VSS pass pass_inv) ece3663Inverter wn=wn wp=wp mult=mult
N0 (in pass out VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
P0 (out pass_inv in VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
ends ece3663tgate
//end of subcircuit definition
// Cell: ece3663tGateMux
// Modified by: Team NAND
// added ability to control sizing from variables wn and wp.
// 4/23/10 - conformed to class naming convention
subckt ece3663tGateMux VDD VSS in0 in1 select out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (VDD VSS in0 selectPrime out) ece3663tgate wn=wn wp=wp mult=mult
I1 (VDD VSS in1 select out) ece3663tgate wn=wn wp=wp mult=mult
I2 (VDD VSS select selectPrime) ece3663Inverter wn=wn wp=wp mult=mult
ends ece3663tGateMux
//end of subcircuit definition
//===============================END OUR WIKI==================================
//------------------------------OTHER PPLS WIKI--------------------------------2---// Cell name: ece3663Inverter
//
An inverter with sizing parameters and parameterized AD,AS,PD,PS
//
The S/D parameters assume a single-finger device
subckt ece3663Inverter VDD VSS in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
MP (out in VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MN (out in VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
ends ece3663Inverter
// End of subcircuit definition
// Cell name: ece3663NAND2
// modified by Team XOR on 3/31/10 to fix naming convention and size for equal PUN/PDN resistances
subckt ece3663NAND2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P1 (Out InB Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
P0 (Out InA Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N1 (net18 InB Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn \
pd=3u+2*wn m=mult
N0 (Out InA net18 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
ends ece3663NAND2
// End of subcircuit definition.
// Cell name: ece3663NOR2
// Modified by Team XOR on 3/31/10 to fix naming convention and size for equal PUN/PDN resistances
subckt ece3663NOR2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P1 (Out InB net10 Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult
P0 (net10 InA Vdd Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult
N1 (Out InB Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult
N0 (Out InA Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult
ends ece3663NOR2
// End of subcircuit definition.
// Cell name: ece3663AND2
// Implementation: NAND in series w/ inverter
// Modified 3/17/2010 by Team Mux to correct faults in netlist parameters
// Modified 4/4/2010 by Team Mux to conform to class conventions
subckt ece3663AND2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P2 (Out net049 Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \
ps=3u+wp pd=3u+wp m=mult region=sat
P1 (net049 InB Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \
ps=3u+wp pd=3u+wp m=mult region=sat
P0 (net049 InA Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp \
ps=3u+wp pd=3u+wp m=mult region=sat
N2 (Out net049 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
N1 (net22 InB Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult region=sat
N0 (net049 InA net22 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn \
ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult region=sat
ends ece3663AND2
//end of subcircuit defn.
//
//
//
//
Cell name: ece3663OR2
Implementation: NOR in series with inverter
Modified 3/17/2010 by Team MUX to standardize transistor names
Modified 3/31/2010 by Team XOR to fix naming convention and size for equal PUN/PDN resistances
// Modified 4/4/2010 by Team MUX to fix wrong bulk connection and conform to class conventions
subckt ece3663OR2 Vdd Vss InA InB Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P2 (Out net21 Vdd Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
P1 (net21 InB net10 Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult region=sat
P0 (net10 InA Vdd Vdd) ami06P w=2*wp l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+2*wp \
pd=3u+2*wp m=mult region=sat
N2 (Out net21 Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
N1 (net21 InB Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
N0 (net21 InA Vss Vss) ami06N w=wn l=lp as=1.5u*wn ad=1.5u*wn \
ps=3u+wn pd=3u+wn m=mult region=sat
ends ece3663OR2
//end subcircuit
// Cell name: ece3663XOR2
// An implementation of a two input XOR =A'*B+A*B'=((A'*B)'*(A*B')')'
//
//
//
//
Inputs to the XOR are named "A" and "B"
Output of the XOR is named "out"
High voltage is named "VDD"
Low voltage (ground) is named "VSS"
//subsubcircuit inverters used have been sized to make worst-case PUN resistance and worst-case PDN
resistance the same
//subsubcircuit NANDs used have been sized to make worst-case PUN resistance and worst-case PDN
resistance the same
//edited by Team ADD at 10:38 p.m. on Sunday, 4 April 2010
subckt ece3663XOR2 VDD VSS A B out
parameters wpGlobal=3u wnGlobal=1.5u lnGlobal=600n lpGlobal=600n multGlobal=1
//subsubcircuits that invert the inputs
//inverter for input A
invA (VDD VSS A notA) ece3663Inverter wp=wpGlobal wn=wnGlobal ln=lnGlobal lp=lpGlobal
mult=multGlobal
//inverter for input B
invB (VDD VSS B notB) ece3663Inverter wp=wpGlobal wn=wnGlobal ln=lnGlobal lp=lpGlobal
mult=multGlobal
//basically first input NAND
p1comma1 (intermediate1 notA VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal
ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
p1comma2 (intermediate1 B VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal
ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
n1comma1 (intermediate1 notA node1 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal
ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
n1comma2 (node1 B VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal ad=1.5u*2*wnGlobal
ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
//basically second input NAND
p2comma1 (intermediate2 A VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal
ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
p2comma2 (intermediate2 notB VDD VDD) ami06P w=wpGlobal l=lpGlobal as=1.5u*wpGlobal
ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal m=multGlobal
n2comma1 (intermediate2 A node2 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal
ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
n2comma2 (node2 notB VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal
ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
//basically third combining/output NAND
p3comma1 (out intermediate1 VDD VDD) ami06P
ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal
p3comma2 (out intermediate2 VDD VDD) ami06P
ad=1.5u*wpGlobal ps=3u+wpGlobal pd=3u+wpGlobal
w=wpGlobal l=lpGlobal as=1.5u*wpGlobal
m=multGlobal
w=wpGlobal l=lpGlobal as=1.5u*wpGlobal
m=multGlobal
n3comma1 (out intermediate1 node3 VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal
ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
n3comma2 (node3 intermediate2 VSS VSS) ami06N w=2*wnGlobal l=lnGlobal as=1.5u*2*wnGlobal
ad=1.5u*2*wnGlobal ps=3u+2*wnGlobal pd=3u+2*wnGlobal m=multGlobal
ends ece3663XOR2
// End of subcircuit definition
// Cell Name: ece3663XNOR2
// Edited by Team XOR: a 2-input XNOR gate built from other subcircuits
// Has tunable parameters including: wp, wn, lp, ln, and m
// Has parameterized AS, AD, PS, PD
// Implements the function:
XNOR = ((F*G)')'
// where F = B + A'B' and G = A + A'B'
// not the most efficient implementation, but this is what the 2008 group chose to do.
// originally this was made of 18 discrete transistors with a ridiculous netlist that was
// very difficult to understand. we've improved this by "packaging" the transistors into
// the gates they had essentially created.
subckt ece3663XNOR2 (VDD VSS A B Out)
parameters wp=3u wn=1.5u lp=600n ln=600n mult=1
NOR (VDD VSS A B center) ece3663NOR2 wp=wp wn=wn lp=lp ln=ln mult=mult
ORtop (VDD VSS B center F) ece3663OR2 wp=wp wn=wn lp=lp ln=ln mult=mult
ORbottom (VDD VSS A center G) ece3663OR2 wp=wp wn=wn lp=lp ln=ln mult=mult
NAND (VDD VSS F G Outbar) ece3663NAND2 wp=wp wn=wn lp=lp ln=ln mult=mult
INVERTER (VDD VSS Outbar Out) ece3663Inverter wp=wp wn=wn lp=lp ln=ln mult=mult
ends ece3663XNOR2
//end of subcircuit defn.
// Cell name: NAND3
// View name: schematic
// Edited by group NOR: 3 input NAND gate with tunable wp, wn, lp, ln, and m
//
Sized for equal pull-up, pull-down to Inv
subckt ece3663NAND3 (VDD VSS A B C OUT)
parameters wp=3u wn=4.5u ln=600n lp=600n mult=1
MNC (NETCB C VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
MNB (NETBA B NETCB VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
MNA (OUT A NETBA VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult region=sat
MPC (OUT C VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
MPB (OUT B VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
MPA (OUT A VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult region=sat
ends ece3663NAND3
//END OF subcircuit definition
// Cell name: NOR3
// View name: schematic
// Edited by group NOR: 3 input NOR gate with tunable wp, wn, lp, ln, and m
//
Sized for equal pull-up, pull-down to Inv
subckt ece3663NOR3 (VDD VSS A B C out)
parameters wp=9u wn=1.5u ln=600n lp=600n mult=1
MPa (netab A VDD VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MPb (netbc B netab VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MPc (out C netbc VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
MNa (out A VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
MNb (out B VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
MNc (out C VSS VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
ends ece3663NOR3
// End of subcircuit definition.
// Cell name: AND3
// View name: schematic
// Edited by group NOR: 3 input AND gate with tunable wp, wn, and m
//
sized for pull-up/pull-down equal to inverter
subckt ece3663AND3 (VDD VSS A B C OUT)
parameters wpA=3u wnA=1.5u multA=1
NAND (VDD VSS A B C Invertin) ece3663NAND3 wp=wpA wn=wnA*3 mult=multA
Inv (VDD VSS Invertin OUT) ece3663Inverter wp=wpA wn=wnA mult=multA
ends ece3663AND3
//end of subcircuit definition
// Cell name: OR3
// View name: schematic
// Edited by group NOR: 3 input OR gate with tunable wp, wn, and m
//
sized for pull-up/pull-down equal to inverter
subckt ece3663OR3 (VDD VSS A B C out)
parameters wpO=3u wnO=1.5u multO=1
NOR (VDD VSS A B C Invertin) ece3663NOR3 wp=wpO*3 wn=wpO mult=multO
Inv (VDD VSS Invertin out) ece3663Inverter wp=wpO wn=wnO mult=multO
ends ece3663OR3
//end of subcircuit definition
// Cell name: ece3663F1
// This circuit implements the function F1 = (AB + BC + AC)'
// It has sizing parameters and parameterized AD, AS, PD, PS.
// Edited by Team XOR; we improved the circuit from 2008 by removing
// two transistors. The old implementation had 12 transistors while
// this implementation only uses 10 transistors. We were able to
// remove one transistor for both the PUN and PDN by simplifying the F1 equation to F1=(A(B+C)+BC)'
// We also sized the implementation to have equal pull-up and pull-down networks.
subckt ece3663F1 Vdd Vss A B C Out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P0 (Out B Node2 Vdd) ami06P w=1.5*wp l=lp as=1.5u*1.5*wp ad=1.5u*1.5*wp \
ps=3u+1.5*wp pd=3u+1.5*wp m=mult
P2 (Node2 C Node1 Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
ps=3u+3*wp pd=3u+3*wp m=mult
P3 (Node1 B Vdd Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
ps=3u+3*wp pd=3u+3*wp m=mult
P1 (Out C Node2 Vdd) ami06P w=1.5*wp l=lp as=1.5u*1.5*wp ad=1.5u*1.5*wp \
ps=3u+1.5*wp pd=3u+1.5*wp m=mult
P4 (Node2 A Vdd Vdd) ami06P w=3*wp l=lp as=1.5u*3*wp ad=1.5u*3*wp \
ps=3u+3*wp pd=3u+3*wp m=mult
N4 (Out C Node4 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N3 (Node4 B Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N2 (Out C Node3 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N1 (Out B Node3 Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
N0 (Node3 A Vss Vss) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn \
ps=3u+2*wn pd=3u+2*wn m=mult
ends ece3663F1
//Ends subcircuit definition
// Cell name: ece3663F2
// An implementation of the function F2=(A*B*C+D*(A+B+C))'
// Inputs to this gate are named "A", "B", "C", "D"
// Outout of this gate is named "out"
// High voltage is named "VDD"
// Low voltage (ground) is named "VSS"
// subcircuit has been sized to make the worst-case PUN resistance and the worst-case PDN
resistance the same
//edited by Team ADD at 11:22 p.m. on Sunday, 4 April 2010
subckt ece3663F2 VDD VSS A B C D out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
//A in parallel with B in parallel with C in PUN
pAparallel (node1 A VDD VDD) ami06P w=(4.0/3.0)*wp l=lp as=1.5u*(4.0/3.0)*wp
ad=1.5u*(4.0/3.0)*wp ps=3u+(4.0/3.0)*wp pd=3u+(4.0/3.0)*wp m=mult
pBparallel (node1
ad=1.5u*(4.0/3.0)*wp
pCparallel (node1
ad=1.5u*(4.0/3.0)*wp
B VDD VDD) ami06P w=(4.0/3.0)*wp l=lp
ps=3u+(4.0/3.0)*wp pd=3u+(4.0/3.0)*wp
C VDD VDD) ami06P w=(4.0/3.0)*wp l=lp
ps=3u+(4.0/3.0)*wp pd=3u+(4.0/3.0)*wp
as=1.5u*(4.0/3.0)*wp
m=mult
as=1.5u*(4.0/3.0)*wp
m=mult
//D in parallel with (A in series with B in series with C) in PUN
pD (out D node1 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp m=mult
pAseries (node2 A node1 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp
m=mult
pBseries (node3 B node2 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp
m=mult
pCseries (out C node3 VDD) ami06P w=4*wp l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+4*wp pd=3u+4*wp
m=mult
//A in series with
nAseries (out A
m=mult
nBseries (node4
m=mult
nCseries (node5
m=mult
B in series with C in PDN
node4 VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn
B node5 VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn
C VSS VSS) ami06N w=3*wn l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+3*wn pd=3u+3*wn
//D in series with (A in parallel with B in parallel with C) in PDN
nD (out D node6 VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn m=mult
nAparallel (node6 A VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn
m=mult
nBparallel (node6 B VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn
m=mult
nCparallel (node6 C VSS VSS) ami06N w=2*wn l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+2*wn pd=3u+2*wn
m=mult
ends ece3663F2
// End of subcircuit definition
//===============================END WIKI STUFF====================================
//-----------------------THINGS TO MAKE OUR LIVES EASIER---------------------------3---// Cell name: buffer
//
two inverters in series
subckt buffer VDD VSS in out
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I1 (VDD VSS in i1) ece3663Inverter wp=wp wn=wn mult=mult
I2 (VDD VSS i1 out) ece3663Inverter wp=wp wn=wn mult=mult
ends buffer
// End of subcircuit definition
// Cell name: 16b Buffer
subckt buffer_16 Vdd Vss \
i15 i14 i13 i12 i11 i10 i9 i8 i7 i6 i5 i4 i3 i2 i1 i0 \
o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
I0 (Vdd Vss i0 o0) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I1 (Vdd Vss i1 o1) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I2 (Vdd Vss i2 o2) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I3 (Vdd Vss i3 o3) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I4 (Vdd Vss i4 o4) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I5 (Vdd Vss i5 o5) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I6 (Vdd Vss i6 o6) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I7 (Vdd Vss i7 o7) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I8 (Vdd Vss i8 o8) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I9 (Vdd Vss i9 o9) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I10 (Vdd Vss i10 o10) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I11 (Vdd Vss i11 o11) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I12 (Vdd Vss i12 o12) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I13 (Vdd Vss i13 o13) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I14 (Vdd Vss i14 o14) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
I15 (Vdd Vss i15 o15) buffer wn=wn wp=wp ln=ln lp=lp mult=mult
ends buffer_16
// Cell name: MUX8to1
subckt MUX8to1 Vdd Vss in0 in1 in2 in3 in4 in5 in6 in7 sel0 sel1 sel2 out
parameters wn=1.5u wp=3u
M6 (Vdd Vss mux4 mux5 sel2 out) ece3663tGateMux wn=wn wp=wp
M5 (Vdd Vss mux2 mux3 sel1 mux5) ece3663tGateMux wn=wn wp=wp
M4 (Vdd Vss mux0 mux1 sel1 mux4) ece3663tGateMux wn=wn wp=wp
M3 (Vdd Vss in6 in7 sel0 mux3) ece3663tGateMux wn=wn wp=wp
M2 (Vdd Vss in4 in5 sel0 mux2) ece3663tGateMux wn=wn wp=wp
M1 (Vdd Vss in2 in3 sel0 mux1) ece3663tGateMux wn=wn wp=wp
M0 (Vdd Vss in0 in1 sel0 mux0) ece3663tGateMux wn=wn wp=wp
ends MUX8to1
//====================END=THINGS TO MAKE OUR LIVES EASIER==========================
//---------------------------------REGISTER----------------------------------------4-------// Cell: posDLatch
// transparent when clk level is high.
subckt posDLatch VDD VSS CLK CLKbar D Q Qbar
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
P0 (link0 CLKbar D VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N0 (D CLK link0 VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
P1 (Q CLK link0 VDD) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
N1 (link0 CLKbar Q VSS) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
I0 (VDD VSS Qbar Q) ece3663Inverter wn=wn wp=wp mult=mult
I1 (VDD VSS link0 Qbar) ece3663Inverter wn=wn wp=wp mult=mult
ends posDLatch
//end of subcircuit definition
//Cell: posEdgeRegister
// This circuit acts as a master-slave positive edge-triggered register
// - two different D-latches combined to create this register
// Q - output of the posEdgeRegister (which is the inverted output of the PosLvlLatch)
subckt posEdgeRegister VDD VSS CLK D Q
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Iclk (VDD VSS CLK CLKbar) ece3663Inverter wn=wn wp=wp mult=mult
//The clock is inverted to produce a negative level latch.
NegLevelLatch (VDD VSS CLKbar CLK D q1 q1bar) posDLatch wn=wn wp=wp mult=mult
PD1 (VDD VSS CLK CLKbar q1bar Qbar Q) posDLatch wn=wn wp=wp mult=mult
ends posEdgeRegister
//end of subcircuit definition
// Cell name: 16bitRegister
subckt register16bit vdd vss CLK d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 q15 q14 q13
q12 q11 q10 q9 q8 q7 q6 q5 q4 q3 q2 q1 q0
parameters wp=3u wn=1.5u
I0 (vdd vss CLK d0 q0) posEdgeRegister wn=wn wp=wp
I1 (vdd vss CLK d1 q1) posEdgeRegister wn=wn wp=wp
I2 (vdd vss CLK d2 q2) posEdgeRegister wn=wn wp=wp
I3 (vdd vss CLK d3 q3) posEdgeRegister wn=wn wp=wp
I4 (vdd vss CLK d4 q4) posEdgeRegister wn=wn wp=wp
I5 (vdd vss CLK d5 q5) posEdgeRegister wn=wn wp=wp
I6 (vdd vss CLK d6 q6) posEdgeRegister wn=wn wp=wp
I7 (vdd vss CLK d7 q7) posEdgeRegister wn=wn wp=wp
I8 (vdd vss CLK d8 q8) posEdgeRegister wn=wn wp=wp
I9 (vdd vss CLK d9 q9) posEdgeRegister wn=wn wp=wp
I10 (vdd vss CLK d10 q10) posEdgeRegister wn=wn wp=wp
I11 (vdd vss CLK d11 q11) posEdgeRegister wn=wn wp=wp
I12 (vdd vss CLK d12 q12) posEdgeRegister wn=wn wp=wp
I13 (vdd vss CLK d13 q13) posEdgeRegister wn=wn wp=wp
I14 (vdd vss CLK d14 q14) posEdgeRegister wn=wn wp=wp
I15 (vdd vss CLK d15 q15) posEdgeRegister wn=wn wp=wp
ends register16bit
//end of subckt defn.
//===================================END REGISTER===================================
//-------------------------------------ADDER----------------------------------------5------------// Cell Name: HalfAdder1b
subckt HalfAdder1b Vdd Vss InA InB SOut COut
parameters wn=1.5n wp=3n
OR1 (Vdd Vss InA InB orOut) ece3663OR2 wn=wn wp=wp
AND1 (Vdd Vss InA InB COut) ece3663AND2 wn=wn wp=wp
INV1 (Vdd Vss COut invOut) ece3663Inverter wn=wn wp=wp
AND2 (Vdd Vss orOut invOut SOut) ece3663AND2 wn=wn wp=wp
ends HalfAdder1b
//end of subcircuit definition
// Cell name: FullAdder1b - Mirror
// Note: be aware that the wp=1.5u
subckt FullAdder1b VDD VSS INa INb
parameters wp=1.5u wn=1.5u ln=600n
Adder implementation
because the 1bit adder has been sized properly internally
cin Co Sum
lp=600n mult=1
P0 (link0 INa VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P1 (link0 INb VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P2 (coutBar cin link0 VDD) ami06P w=wp*2 l=lp as=1.5u*2*wp ad=1.5u*2*wp ps=3u+wp*2 \
pd=3u+wp*2 m=mult
P3 (link1 INb VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P4 (coutBar INa link1 VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P5 (sumBar coutBar link4 VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp \
ps=3u+wp*4 pd=3u+wp*4 m=mult
P6 (link4 INa VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P7 (link4 INb VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P8 (link4 cin VDD VDD) ami06P w=wp*4 l=lp as=1.5u*4*wp ad=1.5u*4*wp ps=3u+wp*4 \
pd=3u+wp*4 m=mult
P9 (link5 INa VDD VDD) ami06P w=wp*6 l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+wp*6 \
pd=3u+wp*6 m=mult
P10 (link6 INb link5 VDD) ami06P w=wp*6 l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+wp*6 \
pd=3u+wp*6 m=mult
P11 (sumBar cin link6 VDD) ami06P w=wp*6 l=lp as=1.5u*6*wp ad=1.5u*6*wp ps=3u+wp*6 \
pd=3u+wp*6 m=mult
N0 (link2 INa VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N1 (link2 INb VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N2 (coutBar cin link2 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N3 (link3 INb VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N4 (coutBar INa link3 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N5 (sumBar coutBar link7 VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2\
pd=3u+wn*2 m=mult
N6 (link7 INa VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N7 (link7 INb VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N8 (link7 cin VSS VSS) ami06N w=wn*2 l=ln as=1.5u*2*wn ad=1.5u*2*wn ps=3u+wn*2 \
pd=3u+wn*2 m=mult
N9 (link8 INa VSS VSS) ami06N w=wn*3 l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+wn*3 \
pd=3u+wn*3 m=mult
N10 (link9 INb link8 VSS) ami06N w=wn*3 l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+wn*3 \
pd=3u+wn*3 m=mult
N11 (sumBar cin link9 VSS) ami06N w=wn*3 l=ln as=1.5u*3*wn ad=1.5u*3*wn ps=3u+wn*3 \
pd=3u+wn*3 m=mult
COUT (VDD VSS coutBar Co) ece3663Inverter wn=wn wp=2*wp mult=mult
SUM (VDD VSS sumBar Sum) ece3663Inverter wn=wn wp=2*wp mult=mult
ends FullAdder1b
// End of subcircuit definition.
// Cell name: FullAdder16b
// Note: BE AWARE that the wp=1.5u because the 1bit adder has been sized properly internally
subckt FullAdder16b Vdd Vss Cin Cout a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0\
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 \
sum15 sum14 sum13 sum12 sum11 sum10 sum9 sum8 sum7 sum6 sum5 sum4 sum3 sum2 sum1
sum0
parameters wp=1.5u wn=1.5u ln=600n lp=600n mult=1
FA0 (Vdd Vss a0 b0 Cin c1 sum0) FullAdder1b wp=wp*5.8 wn=wn*5.8 mult=mult
FA1 (Vdd Vss a1 b1 c1 c2 sum1) FullAdder1b wp=wp*3.7 wn=wn*3.7 mult=mult
FA2 (Vdd Vss a2 b2 c2 c3 sum2) FullAdder1b wp=wp*3.4 wn=wn*3.4 mult=mult
FA3 (Vdd Vss a3 b3 c3 c4 sum3) FullAdder1b wp=wp*3.1 wn=wn*3.1 mult=mult
FA4 (Vdd Vss a4 b4 c4 c5 sum4) FullAdder1b wp=wp*2.9 wn=wn*2.9 mult=mult
FA5 (Vdd Vss a5 b5 c5 c6 sum5) FullAdder1b wp=wp*2.6 wn=wn*2.6 mult=mult
FA6 (Vdd Vss a6 b6 c6 c7 sum6) FullAdder1b wp=wp*2.4 wn=wn*2.4 mult=mult
FA7 (Vdd Vss a7 b7 c7 c8 sum7) FullAdder1b wp=wp*2.2 wn=wn*2.2 mult=mult
FA8 (Vdd Vss a8 b8 c8 c9 sum8) FullAdder1b wp=wp*2.0 wn=wn*2.0 mult=mult
FA9 (Vdd Vss a9 b9 c9 c10 sum9) FullAdder1b wp=wp*1.9 wn=wn*1.9 mult=mult
FA10 (Vdd Vss a10 b10 c10 c11 sum10) FullAdder1b wp=wp*1.7 wn=wn*1.7 mult=mult
FA11 (Vdd Vss a11 b11 c11 c12 sum11) FullAdder1b wp=wp*1.6 wn=wn*1.6 mult=mult
FA12 (Vdd Vss a12 b12 c12 c13 sum12) FullAdder1b wp=wp*1.4 wn=wn*1.4 mult=mult
FA13 (Vdd Vss a13 b13 c13 c14 sum13) FullAdder1b wp=wp*1.3 wn=wn*1.3 mult=mult
FA14 (Vdd Vss a14 b14 c14 c15 sum14) FullAdder1b wp=wp*1.2 wn=wn*1.2 mult=mult
FA15 (Vdd Vss a15 b15 c15 Cout sum15) FullAdder1b wp=wp*1.1 wn=wn*1.1 mult=mult
ends FullAdder16b
//end of subcircuits
//=======================================END ADDER=========================================
//-------------------------------------SUBTRACTOR----------------------------------6--------------subckt sub_16b VDD VSS ovfl \
a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 \
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 \
s15 s14 s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0
parameters wp=1.5u wn=1.5u ln=600n lp=600n mult=1
I0 (VDD VSS b0 b0_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I1 (VDD VSS b1 b1_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I2 (VDD VSS b2 b2_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I3 (VDD VSS b3 b3_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I4 (VDD VSS b4 b4_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I5 (VDD VSS b5 b5_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I6 (VDD VSS b6 b6_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I7 (VDD VSS b7 b7_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I8 (VDD VSS b8 b8_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I9 (VDD VSS b9 b9_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I10 (VDD VSS b10 b10_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I11 (VDD VSS b11 b11_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I12 (VDD VSS b12 b12_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I13 (VDD VSS b13 b13_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I14 (VDD VSS b14 b14_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
I15 (VDD VSS b15 b15_inv) ece3663Inverter wp=wp*5.3 wn=wn*5.3
FA0 (VDD VSS a0 b0_inv VDD c1 s0) FullAdder1b wp=wp*22 wn=wn*22 mult=mult
FA1 (VDD VSS a1 b1_inv c1 c2 s1) FullAdder1b wp=wp*16 wn=wn*16 mult=mult
FA2 (VDD VSS a2 b2_inv c2 c3 s2) FullAdder1b wp=wp*13 wn=wn*13 mult=mult
FA3 (VDD VSS a3 b3_inv c3 c4 s3) FullAdder1b wp=wp*11 wn=wn*11 mult=mult
FA4 (VDD VSS a4 b4_inv c4 c5 s4) FullAdder1b wp=wp*9.3 wn=wn*9.3 mult=mult
FA5 (VDD VSS a5 b5_inv c5 c6 s5) FullAdder1b wp=wp*7.7 wn=wn*7.7 mult=mult
FA6 (VDD VSS a6 b6_inv c6 c7 s6) FullAdder1b wp=wp*6.4 wn=wn*6.4 mult=mult
FA7 (VDD VSS a7 b7_inv c7 c8 s7) FullAdder1b wp=wp*5.3 wn=wn*5.3 mult=mult
FA8 (VDD VSS a8 b8_inv c8 c9 s8) FullAdder1b wp=wp*4.4 wn=wn*4.4 mult=mult
FA9 (VDD VSS a9 b9_inv c9 c10 s9) FullAdder1b wp=wp*3.7 wn=wn*3.7 mult=mult
FA10 (VDD VSS a10 b10_inv c10 c11 s10) FullAdder1b wp=wp*3.0 wn=wn*3.0 mult=mult
FA11 (VDD VSS a11 b11_inv c11 c12 s11) FullAdder1b wp=wp*2.5 wn=wn*2.5 mult=mult
FA12 (VDD VSS a12 b12_inv c12 c13 s12) FullAdder1b wp=wp*2.1 wn=wn*2.1 mult=mult
FA13 (VDD VSS a13 b13_inv c13 c14 s13) FullAdder1b wp=wp*1.7 wn=wn*1.7 mult=mult
FA14 (VDD VSS a14 b14_inv c14 c15 s14) FullAdder1b wp=wp*1.4 wn=wn*1.4 mult=mult
FA15 (VDD VSS a15 b15_inv c15 Cout s15) FullAdder1b wp=wp*1.2 wn=wn*1.2 mult=mult
X0 (VDD VSS Cout c15 ovfl) ece3663XOR2 wpGlobal=wp wnGlobal=wn multGlobal=mult
ends sub_16b
//===================================END OF SUBTRACTOR====================================
//-------------------------------------16b-AND----------------------------------------7------------//Cell Name: and16b
subckt and16b Vdd Vss a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0\
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 \
o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0
parameters wn=1.5u wp=3u
AND0 (Vdd Vss a0 b0 o0) ece3663AND2 wn=wn wp=wp
AND1 (Vdd Vss a1 b1 o1) ece3663AND2 wn=wn wp=wp
AND2 (Vdd Vss a2 b2 o2) ece3663AND2 wn=wn wp=wp
AND3 (Vdd Vss a3 b3 o3) ece3663AND2 wn=wn wp=wp
AND4 (Vdd Vss a4 b4 o4) ece3663AND2 wn=wn wp=wp
AND5 (Vdd Vss a5 b5 o5) ece3663AND2 wn=wn wp=wp
AND6 (Vdd Vss a6 b6 o6) ece3663AND2 wn=wn wp=wp
AND7 (Vdd Vss a7 b7 o7) ece3663AND2 wn=wn wp=wp
AND8 (Vdd Vss a8 b8 o8) ece3663AND2 wn=wn wp=wp
AND9 (Vdd Vss a9 b9 o9) ece3663AND2 wn=wn wp=wp
AND10 (Vdd Vss a10 b10 o10) ece3663AND2 wn=wn wp=wp
AND11 (Vdd Vss a11 b11 o11) ece3663AND2 wn=wn wp=wp
AND12 (Vdd Vss a12 b12 o12) ece3663AND2 wn=wn wp=wp
AND13 (Vdd Vss a13 b13 o13) ece3663AND2 wn=wn wp=wp
AND14 (Vdd Vss a14 b14 o14) ece3663AND2 wn=wn wp=wp
AND15 (Vdd Vss a15 b15 o15) ece3663AND2 wn=wn wp=wp
ends and16b
//end of subcircuit
//=====================================END OF AND========================================
//---------------------------------------16b-OR---------------------------------------8----------//Cell Name: or16b
subckt or16b Vdd Vss a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0\
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 \
o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0
parameters wn=1.5u wp=3u
OR0 (Vdd Vss a0 b0 o0) ece3663OR2 wn=wn wp=wp
OR1 (Vdd Vss a1 b1 o1) ece3663OR2 wn=wn wp=wp
OR2 (Vdd Vss a2 b2 o2) ece3663OR2 wn=wn wp=wp
OR3 (Vdd Vss a3 b3 o3) ece3663OR2 wn=wn wp=wp
OR4 (Vdd Vss a4 b4 o4) ece3663OR2 wn=wn wp=wp
OR5 (Vdd Vss a5 b5 o5) ece3663OR2 wn=wn wp=wp
OR6 (Vdd Vss a6 b6 o6) ece3663OR2 wn=wn wp=wp
OR7 (Vdd Vss a7 b7 o7) ece3663OR2 wn=wn wp=wp
OR8 (Vdd Vss a8 b8 o8) ece3663OR2 wn=wn wp=wp
OR9 (Vdd Vss a9 b9 o9) ece3663OR2 wn=wn wp=wp
OR10 (Vdd Vss a10 b10 o10) ece3663OR2 wn=wn wp=wp
OR11 (Vdd Vss a11 b11 o11) ece3663OR2 wn=wn wp=wp
OR12 (Vdd Vss a12 b12 o12) ece3663OR2 wn=wn wp=wp
OR13 (Vdd Vss a13 b13 o13) ece3663OR2 wn=wn wp=wp
OR14 (Vdd Vss a14 b14 o14) ece3663OR2 wn=wn wp=wp
OR15 (Vdd Vss a15 b15 o15) ece3663OR2 wn=wn wp=wp
ends or16b
//end of subcircuit
//=====================================END OF OR========================================
//---------------------------------------TGATE---------------------------------------9------------//Cell Name: tgate16b
subckt tgate16b Vdd Vss a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0\
o15 o14 o13 o12 o11 o10 o9 o8 o7 o6 o5 o4 o3 o2 o1 o0
parameters wn=1.5u wp=3u
TGATE0 (Vdd Vss in_0 Vdd o_0) ece3663tgate wn=wn wp=wp
TGATE1 (Vdd Vss in_1 Vdd o_1) ece3663tgate wn=wn wp=wp
TGATE2 (Vdd Vss in_2 Vdd o_2) ece3663tgate wn=wn wp=wp
TGATE3 (Vdd Vss in_3 Vdd o_3) ece3663tgate wn=wn wp=wp
TGATE4 (Vdd Vss in_4 Vdd o_4) ece3663tgate wn=wn wp=wp
TGATE5 (Vdd Vss in_5 Vdd o_5) ece3663tgate wn=wn wp=wp
TGATE6 (Vdd Vss in_6 Vdd o_6) ece3663tgate wn=wn wp=wp
TGATE7 (Vdd Vss in_7 Vdd o_7) ece3663tgate wn=wn wp=wp
TGATE8 (Vdd Vss in_8 Vdd o_8) ece3663tgate wn=wn wp=wp
TGATE9 (Vdd Vss in_9 Vdd o_9) ece3663tgate wn=wn wp=wp
TGATE10 (Vdd Vss in_10 Vdd o_10) ece3663tgate wn=wn wp=wp
TGATE11 (Vdd Vss in_11 Vdd o_11) ece3663tgate wn=wn wp=wp
TGATE12 (Vdd Vss in_12 Vdd o_12) ece3663tgate wn=wn wp=wp
TGATE13 (Vdd Vss in_13 Vdd o_13) ece3663tgate wn=wn wp=wp
TGATE14 (Vdd Vss in_14 Vdd o_14) ece3663tgate wn=wn wp=wp
TGATE15 (Vdd Vss in_15 Vdd o_15) ece3663tgate wn=wn wp=wp
ends tgate16b
//===================================END OF TGATE=======================================
//----------------------------------------back to back INV------------------------------10--------subckt backToBackInverter Vdd Vss in out outBar
parameters wn=1.5u wp=3u
I1 (Vdd Vss in out) ece3663Inverter wn=wn wp=wp
I2 (Vdd Vss out in) ece3663Inverter wn=wn wp=wp
ends backToBackInverter
//=====================================END OF NO-OP====================================
//-------------------------------------MULTIPLER--------------------------------------11---------// Cell Name: AndRow
subckt AndRow Vdd Vss x7 x6 x5 x4 x3 x2 x1 x0 y o7 o6 o5 o4 o3 o2 o1 o0
parameters wn=1.5n wp=3n
AND0
AND1
AND2
AND3
AND4
AND5
AND6
AND7
(Vdd
(Vdd
(Vdd
(Vdd
(Vdd
(Vdd
(Vdd
(Vdd
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
x0
x1
x2
x3
x4
x5
x6
x7
y
y
y
y
y
y
y
y
o0)
o1)
o2)
o3)
o4)
o5)
o6)
o7)
ece3663AND2
ece3663AND2
ece3663AND2
ece3663AND2
ece3663AND2
ece3663AND2
ece3663AND2
ece3663AND2
wn=wn
wn=wn
wn=wn
wn=wn
wn=wn
wn=wn
wn=wn
wn=wn
wp=wp
wp=wp
wp=wp
wp=wp
wp=wp
wp=wp
wp=wp
wp=wp
ends AndRow
//Cell Name: AdderRow1
// has HA at both ends...only used in the first row of multiplier
// the sizing for the full adders is done internalls hence wn,wp = 1.5u
subckt AdderRow1 Vdd Vss h g0 g1 f0 f1 e0 e1 d0 d1 c0 c1 b0 b1 a0 a1 o7 o6 o5 o4 o3 o2 o1 o0 cout
parameters wn=1.5n wp=1.5n
HA0 (Vdd Vss a0 a1 o0 cout0) HalfAdder1b wn=wn wp=2*wp
FA1 (Vdd Vss b0 b1 cout0 cout1 o1) FullAdder1b wn=wn wp=wp
FA2 (Vdd Vss c0 c1 cout1 cout2 o2) FullAdder1b wn=wn wp=wp
FA3 (Vdd Vss d0 d1 cout2 cout3 o3) FullAdder1b wn=wn wp=wp
FA4 (Vdd Vss e0 e1 cout3 cout4 o4) FullAdder1b wn=wn wp=wp
FA5 (Vdd Vss f0 f1 cout4 cout5 o5) FullAdder1b wn=wn wp=wp
FA6 (Vdd Vss g0 g1 cout5 cout6 o6) FullAdder1b wn=wn wp=wp
HA7 (Vdd Vss h cout6 o7 cout) HalfAdder1b wn=wn wp=2*wp
ends AdderRow1
//Cell Name: AdderRow2
// has only one HA closes to the lsb...will be used throughout the multiplier
//
except for the first row.
subckt AdderRow2 Vdd Vss h0 h1 g0 g1 f0 f1 e0 e1 d0 d1 c0 c1 b0 b1 a0 a1 o7 o6 o5 o4 o3 o2 o1 o0
cout
parameters wn=1.5n wp=1.5n
HA0 (Vdd Vss
FA1 (Vdd Vss
FA2 (Vdd Vss
FA3 (Vdd Vss
FA4 (Vdd Vss
FA5 (Vdd Vss
FA6 (Vdd Vss
FA7 (Vdd Vss
ends AdderRow2
a0
b0
c0
d0
e0
f0
g0
h0
a1
b1
c1
d1
e1
f1
g1
h1
o0 cout0) HalfAdder1b wn=wn wp=2*wp
cout0 cout1 o1) FullAdder1b wn=wn wp=wp
cout1 cout2 o2) FullAdder1b wn=wn wp=wp
cout2 cout3 o3) FullAdder1b wn=wn wp=wp
cout3 cout4 o4) FullAdder1b wn=wn wp=wp
cout4 cout5 o5) FullAdder1b wn=wn wp=wp
cout5 cout6 o6) FullAdder1b wn=wn wp=wp
cout6 cout o7) FullAdder1b wn=wn wp=wp
//Cell Name: Multiplier8b (complete 8 bit multiplier)
//Function: takes in two 8 bit numbers, multiplies them, and gives the output as a 16 bit number.
subckt Multiplier8b Vdd Vss a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 o15 o14 o13 o12 o11 o10
o9 o8 o7 o6 o5 o4 o3 o2 o1 o0
parameters wn=1.5n wp=1.5n
//Set up the inputs into each adder row
ROW0IN (Vdd Vss a7 a6 a5 a4 a3 a2 a1 a0 b0 ina0_7 ina0_6 ina0_5 ina0_4 ina0_3 ina0_2 ina0_1 o0)
AndRow wn=wn wp=wp
Row1In (Vdd Vss a7 a6 a5 a4 a3 a2 a1 a0 b1 inb0_8 inb0_7 inb0_6 inb0_5 inb0_4 inb0_3 inb0_2
inb0_1) AndRow wn=wn wp=wp
Row2In (Vdd
ina1_2) AndRow
Row3In (Vdd
ina2_3) AndRow
Row4In (Vdd
ina3_4) AndRow
Row5In (Vdd
ina4_5) AndRow
Row6In (Vdd
ina5_6) AndRow
Row7In (Vdd
ina6_7) AndRow
Vss a7 a6 a5
wn=wn wp=wp
Vss a7 a6 a5
wn=wn wp=wp
Vss a7 a6 a5
wn=wn wp=wp
Vss a7 a6 a5
wn=wn wp=wp
Vss a7 a6 a5
wn=wn wp=wp
Vss a7 a6 a5
wn=wn wp=wp
a4 a3 a2 a1 a0 b2 ina1_9 ina1_8 ina1_7 ina1_6 ina1_5 ina1_4 ina1_3
a4 a3 a2 a1 a0 b3 ina2_10 ina2_9 ina2_8 ina2_7 ina2_6 ina2_5 ina2_4
a4 a3 a2 a1 a0 b4 ina3_11 ina3_10 ina3_9 ina3_8 ina3_7 ina3_6 ina3_5
a4 a3 a2 a1 a0 b5 ina4_12 ina4_11 ina4_10 ina4_9 ina4_8 ina4_7 ina4_6
a4 a3 a2 a1 a0 b6 ina5_13 ina5_12 ina5_11 ina5_10 ina5_9 ina5_8 ina5_7
a4 a3 a2 a1 a0 b7 ina6_14 ina6_13 ina6_12 ina6_11 ina6_10 ina6_9 ina6_8
//Set up the adder arrays
ROW0ADD (Vdd Vss inb0_8 ina0_7 inb0_7 ina0_6 inb0_6 ina0_5 inb0_5 ina0_4 inb0_4 ina0_3 inb0_3
ina0_2 inb0_2 ina0_1 inb0_1 inb1_8 inb1_7 inb1_6 inb1_5 inb1_4 inb1_3 inb1_2 o1 inb1_9) AdderRow1
wn=wn wp=wp
ROW1ADD (Vdd Vss ina1_9 inb1_9 ina1_8 inb1_8 ina1_7 inb1_7 ina1_6 inb1_6 ina1_5 inb1_5 ina1_4
inb1_4 ina1_3 inb1_3 ina1_2 inb1_2 inb2_9 inb2_8 inb2_7 inb2_6 inb2_5 inb2_4 inb1_3 o2 inb2_10)
AdderRow2 wn=wn wp=wp
ROW2ADD (Vdd Vss ina2_10 inb2_10 ina2_9 inb2_9 ina2_8 inb2_8 ina2_7 inb2_7 ina2_6 inb2_6 ina2_5
inb2_5 ina2_4 inb2_4 ina2_3 inb2_3 inb3_10 inb3_9 inb3_8 inb3_7 inb3_6 inb3_5 inb3_4 o3 inb3_11)
AdderRow2 wn=wn wp=wp
ROW3ADD (Vdd Vss ina3_11 inb3_11 ina3_10 inb3_10 ina3_9 inb3_9 ina3_8 inb3_8 ina3_7 inb3_7
ina3_6 inb3_6 ina3_5 inb3_5 ina3_4 inb3_4 inb4_11 inb4_10 inb4_9 inb4_8 inb4_7 inb4_6 inb4_5 o4
inb4_12) AdderRow2 wn=wn wp=wp
ROW4ADD (Vdd Vss ina4_12 inb4_12 ina4_11 inb4_11 ina4_10 inb4_10 ina4_9 inb4_9 ina4_8 inb4_8
ina4_7 inb4_7 ina4_6 inb4_6 ina4_5 inb4_5 inb5_12 inb5_11 inb5_10 inb5_9 inb5_8 inb5_7 inb5_6 o5
inb5_13) AdderRow2 wn=wn wp=wp
ROW5ADD (Vdd Vss ina5_13 inb5_13 ina5_12 inb5_12 ina5_11 inb5_11 ina5_10 inb5_10 ina5_9 inb5_9
ina5_8 inb5_8 ina5_7 inb5_7 ina5_6 inb5_6 inb6_13 inb6_12 inb6_11 inb6_10 inb6_9 inb6_8 inb6_7 o6
inb6_14) AdderRow2 wn=wn wp=wp
ROW6ADD (Vdd Vss ina6_14 inb6_14 ina6_13 inb6_13 ina6_12 inb6_12 ina6_11 inb6_11 ina6_10 inb6_10
ina6_9 inb6_9 ina6_8 inb6_8 ina6_7 inb6_7 o14 o13 o12 o11 o10 o9 o8 o7 o15) AdderRow2 wn=wn wp=wp
ends Multiplier8b
//==================================END OF MULTIPLIER================================
//-------------------------------ARITHMETIC LOGIC UNIT------------------------------12-----------// Cell name: 8:1-MUX-17b
subckt MUX_8_1_17b Vdd Vss \
in_0_0 in_0_1 in_0_2 in_0_3 in_0_4 in_0_5 in_0_6 in_0_7 in_0_8 in_0_9 in_0_10
in_0_11 in_0_12 in_0_13 in_0_14 in_0_15 in_0_16 \
in_1_0 in_1_1 in_1_2 in_1_3 in_1_4 in_1_5 in_1_6 in_1_7 in_1_8 in_1_9 in_1_10
in_1_11 in_1_12 in_1_13 in_1_14 in_1_15 in_1_16 \
in_2_0 in_2_1 in_2_2 in_2_3 in_2_4 in_2_5 in_2_6 in_2_7 in_2_8 in_2_9 in_2_10
in_2_11 in_2_12 in_2_13 in_2_14 in_2_15 in_2_16 \
in_3_0 in_3_1 in_3_2 in_3_3 in_3_4 in_3_5 in_3_6 in_3_7 in_3_8 in_3_9 in_3_10
in_3_11 in_3_12 in_3_13 in_3_14 in_3_15 in_3_16 \
in_4_0 in_4_1 in_4_2 in_4_3 in_4_4 in_4_5 in_4_6 in_4_7 in_4_8 in_4_9 in_4_10
in_4_11 in_4_12 in_4_13 in_4_14 in_4_15 in_4_16 \
in_5_0 in_5_1 in_5_2 in_5_3 in_5_4 in_5_5 in_5_6 in_5_7 in_5_8 in_5_9 in_5_10
in_5_11 in_5_12 in_5_13 in_5_14 in_5_15 in_5_16 \
in_6_0 in_6_1 in_6_2 in_6_3 in_6_4 in_6_5 in_6_6 in_6_7 in_6_8 in_6_9 in_6_10
in_6_11 in_6_12 in_6_13 in_6_14 in_6_15 in_6_16 \
in_7_0 in_7_1 in_7_2 in_7_3 in_7_4 in_7_5 in_7_6 in_7_7 in_7_8 in_7_9 in_7_10
in_7_11 in_7_12 in_7_13 in_7_14 in_7_15 in_7_16 \
sel_0 sel_1 sel_2 \
out_0 out_1 out_2 out_3 out_4 out_5 out_6 out_7 out_8 out_9 out_10 out_11 out_12
out_13 out_14 out_15 out_16
parameters wp=1.5u wn=1.5u
I0 (Vdd Vss in_0_0 in_1_0 in_2_0 in_3_0 in_4_0 in_5_0 in_6_0
MUX8to1 wn=wn wp=wp*2
I1 (Vdd Vss in_0_1 in_1_1 in_2_1 in_3_1 in_4_1 in_5_1 in_6_1
MUX8to1 wn=wn wp=wp*2
I2 (Vdd Vss in_0_2 in_1_2 in_2_2 in_3_2 in_4_2 in_5_2 in_6_2
MUX8to1 wn=wn wp=wp*2
I3 (Vdd Vss in_0_3 in_1_3 in_2_3 in_3_3 in_4_3 in_5_3 in_6_3
MUX8to1 wn=wn wp=wp*2
I4 (Vdd Vss in_0_4 in_1_4 in_2_4 in_3_4 in_4_4 in_5_4 in_6_4
MUX8to1 wn=wn wp=wp*2
I5 (Vdd Vss in_0_5 in_1_5 in_2_5 in_3_5 in_4_5 in_5_5 in_6_5
MUX8to1 wn=wn wp=wp*2
I6 (Vdd Vss in_0_6 in_1_6 in_2_6 in_3_6 in_4_6 in_5_6 in_6_6
MUX8to1 wn=wn wp=wp*2
I7 (Vdd Vss in_0_7 in_1_7 in_2_7 in_3_7 in_4_7 in_5_7 in_6_7
MUX8to1 wn=wn wp=wp*2
I8 (Vdd Vss in_0_8 in_1_8 in_2_8 in_3_8 in_4_8 in_5_8 in_6_8
MUX8to1 wn=wn wp=wp*2
I9 (Vdd Vss in_0_9 in_1_9 in_2_9 in_3_9 in_4_9 in_5_9 in_6_9
MUX8to1 wn=wn wp=wp*2
I10 (Vdd Vss in_0_10 in_1_10 in_2_10 in_3_10 in_4_10 in_5_10
out_10) MUX8to1 wn=wn wp=wp*2
I11 (Vdd Vss in_0_11 in_1_11 in_2_11 in_3_11 in_4_11 in_5_11
out_11) MUX8to1 wn=wn wp=wp*2
I12 (Vdd Vss in_0_12 in_1_12 in_2_12 in_3_12 in_4_12 in_5_12
out_12) MUX8to1 wn=wn wp=wp*2
I13 (Vdd Vss in_0_13 in_1_13 in_2_13 in_3_13 in_4_13 in_5_13
out_13) MUX8to1 wn=wn wp=wp*2
I14 (Vdd Vss in_0_14 in_1_14 in_2_14 in_3_14 in_4_14 in_5_14
out_14) MUX8to1 wn=wn wp=wp*2
I15 (Vdd Vss in_0_15 in_1_15 in_2_15 in_3_15 in_4_15 in_5_15
out_15) MUX8to1 wn=wn wp=wp*2
I16 (Vdd Vss in_0_16 in_1_16 in_2_16 in_3_16 in_4_16 in_5_16
out_16) MUX8to1 wn=wn wp=wp*2
ends MUX_8_1_17b
in_7_0 sel_0 sel_1 sel_2 out_0)
in_7_1 sel_0 sel_1 sel_2 out_1)
in_7_2 sel_0 sel_1 sel_2 out_2)
in_7_3 sel_0 sel_1 sel_2 out_3)
in_7_4 sel_0 sel_1 sel_2 out_4)
in_7_5 sel_0 sel_1 sel_2 out_5)
in_7_6 sel_0 sel_1 sel_2 out_6)
in_7_7 sel_0 sel_1 sel_2 out_7)
in_7_8 sel_0 sel_1 sel_2 out_8)
in_7_9 sel_0 sel_1 sel_2 out_9)
in_6_10 in_7_10 sel_0 sel_1 sel_2
in_6_11 in_7_11 sel_0 sel_1 sel_2
in_6_12 in_7_12 sel_0 sel_1 sel_2
in_6_13 in_7_13 sel_0 sel_1 sel_2
in_6_14 in_7_14 sel_0 sel_1 sel_2
in_6_15 in_7_15 sel_0 sel_1 sel_2
in_6_16 in_7_16 sel_0 sel_1 sel_2
// Cell name: ALU
subckt ALU Vdd Vss \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
B_15 B_14 B_13 B_12 B_11 B_10 B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
CNTRL_0 CNTRL_1 CNTRL_2 \
OUT_15 OUT_14 OUT_13 OUT_12 OUT_11 OUT_10 OUT_9 OUT_8 OUT_7 OUT_6 OUT_5 OUT_4 OUT_3
OUT_2 OUT_1 OUT_0 \
CARRY
parameters wn=1.5u wp=1.5u
//Naming Scheme:
//OPERATION_# - output of each unit
//Selection Mux
SEL (Vdd Vss \
nop_0 nop_1 nop_2 nop_3 nop_4
nop_14 nop_15 nop_16 \
add_0 add_1 add_2 add_3 add_4
add_14 add_15 add_16 \
sub_0 sub_1 sub_2 sub_3 sub_4
sub_14 sub_15 sub_16 \
sft_0 sft_1 sft_2 sft_3 sft_4
sft_14 sft_15 Vss \
and_0 and_1 and_2 and_3 and_4
and_14 and_15 Vss \
or_0 or_1 or_2 or_3 or_4
or_14 or_15 Vss \
pss_0 pss_1 pss_2 pss_3 pss_4
pss_14 pss_15 Vss \
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss \
CNTRL_0 CNTRL_1 CNTRL_2 \
OUT_0 OUT_1 OUT_2 OUT_3 OUT_4
OUT_14 OUT_15 CARRY \
) MUX_8_1_17b wn=wn wp=wp*2
nop_5 nop_6 nop_7 nop_8 nop_9 nop_10 nop_11 nop_12 nop_13
add_5 add_6 add_7 add_8 add_9 add_10 add_11 add_12 add_13
sub_5 sub_6 sub_7 sub_8 sub_9 sub_10 sub_11 sub_12 sub_13
sft_5 sft_6 sft_7 sft_8 sft_9 sft_10 sft_11 sft_12 sft_13
and_5 and_6 and_7 and_8 and_9 and_10 and_11 and_12 and_13
or_5
or_6
or_7
or_8
or_9
or_10
or_11
or_12
or_13
pss_5 pss_6 pss_7 pss_8 pss_9 pss_10 pss_11 pss_12 pss_13
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
OUT_5 OUT_6 OUT_7 OUT_8 OUT_9 OUT_10 OUT_11 OUT_12 OUT_13
//Add (carry order Cin, Cout)
//add_16 is the carryout.
//the wp is sized properly at the level of a 1-bit adder.(no need to size properly at this
heirarchy)
add (Vdd Vss \
Vss add_16 \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
B_15 B_14 B_13 B_12 B_11 B_10 B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
add_15 add_14 add_13 add_12 add_11 add_10 add_9 add_8 add_7 add_6 add_5 add_4 add_3 add_2
add_1 add_0 \
) FullAdder16b wn=wn wp=wp
//Subtract
sub (Vdd Vss sub_16 \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
B_15 B_14 B_13 B_12 B_11 B_10 B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
sub_15 sub_14 sub_13 sub_12 sub_11 sub_10 sub_9 sub_8 sub_7 sub_6 sub_5 sub_4 sub_3 sub_2
sub_1 sub_0 \
) sub_16b wn=wn wp=wp
//Shift
sft (Vdd Vss \
A_0 A_1 A_2 A_3 A_4 A_5 A_6 A_7 A_8 A_9 A_10 A_11 A_12 A_13 A_14 A_15 \
B_0 B_1 \
sft_0 sft_1 sft_2 sft_3 sft_4 sft_5 sft_6 sft_7 sft_8 sft_9 sft_10 sft_11 sft_12 sft_13
sft_14 sft_15 \
) LeftShift
//And
and (Vdd Vss \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
B_15 B_14 B_13 B_12 B_11 B_10 B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
and_15 and_14 and_13 and_12 and_11 and_10 and_9 and_8 and_7 and_6 and_5 and_4 and_3 and_2
and_1 and_0 \
) and16b wn=wn wp=wp*2
//Or
or (Vdd Vss \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
B_15 B_14 B_13 B_12 B_11 B_10 B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
or_15 or_14 or_13 or_12 or_11 or_10 or_9 or_8 or_7 or_6 or_5 or_4 or_3
or_1 or_0 \
) or16b wn=wn wp=wp*2
or_2
//Pass
pass (Vdd Vss \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
pss_15 pss_14 pss_13 pss_12 pss_11 pss_10 pss_9 pss_8 pss_7 pss_6 pss_5 pss_4 pss_3 pss_2
pss_1 pss_0 \
)buffer_16 wn=wn wp=wp*2
//Arbitrary
///////////////////////////////
//MULTIPLIER
///////////////////////////////
//arb (Vdd Vss \
//
A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
//
B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
//
arb_15 arb_14 arb_13 arb_12 arb_11 arb_10 arb_9 arb_8 arb_7 arb_6 arb_5 arb_4 arb_3
arb_2 arb_1 arb_0 \
//
) Multiplier8b wn=wn wp=wp*2
//NOP
//Add a buffer between input and output just in case
buff1 (Vdd Vss \
OUT_15 OUT_14 OUT_13 OUT_12 OUT_11 OUT_10 OUT_9 OUT_8 OUT_7 OUT_6 OUT_5 OUT_4 OUT_3 OUT_2
OUT_1 OUT_0 \
nop_15 nop_14 nop_13 nop_12 nop_11 nop_10 nop_9 nop_8 nop_7 nop_6 nop_5 nop_4 nop_3 nop_2
nop_1 nop_0 \
) buffer_16 wn=wn wp=wp*2
buff2 (Vdd Vss \
CARRY \
nop_16 \
) buffer wn=wn wp=wp*2
ends ALU
// Cell name: Complete ALU (with the registers)
subckt DSP Vdd Vss \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
B_15 B_14 B_13 B_12 B_11 B_10 B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
CNTRL_0 CNTRL_1 CNTRL_2 \
OUT_15 OUT_14 OUT_13 OUT_12 OUT_11 OUT_10 OUT_9 OUT_8 OUT_7 OUT_6 OUT_5 OUT_4 OUT_3
OUT_2 OUT_1 OUT_0 \
CARRY CLK
parameters wn=1.5u wp=1.5u
//Input Registers
RegA (Vdd Vss CLK \
A_15 A_14 A_13 A_12 A_11 A_10 A_9 A_8 A_7 A_6 A_5 A_4 A_3 A_2 A_1 A_0 \
ain_15 ain_14 ain_13 ain_12 ain_11 ain_10 ain_9 ain_8 ain_7 ain_6 ain_5 ain_4 ain_3 ain_2
ain_1 ain_0 \
) register16bit wn=wn wp=wp*2
RegB (Vdd Vss CLK \
B_15 B_14 B_13 B_12 B_11 B_10 B_9 B_8 B_7 B_6 B_5 B_4 B_3 B_2 B_1 B_0 \
bin_15 bin_14 bin_13 bin_12 bin_11 bin_10 bin_9 bin_8 bin_7 bin_6 bin_5 bin_4 bin_3 bin_2
bin_1 bin_0 \
) register16bit wn=wn wp=wp*2
//ALU
//uses adders (so the sizing for wn and wp should be equal.
ALU)
alu1 (Vdd Vss \
ain_15 ain_14 ain_13 ain_12 ain_11 ain_10 ain_9 ain_8
ain_1 ain_0 \
bin_15 bin_14 bin_13 bin_12 bin_11 bin_10 bin_9 bin_8
bin_1 bin_0 \
CNTRL_0 CNTRL_1 CNTRL_2 \
o_15
o_14
o_13
o_12
o_11
o_10
o_9
o_8
o_0
\
CARRY \
) ALU wn=wn wp=wp
//Output Register
RegO (Vdd Vss CLK \
it will be sized properly within the
ain_7 ain_6 ain_5 ain_4 ain_3 ain_2
bin_7 bin_6 bin_5 bin_4 bin_3 bin_2
o_7
o_6
o_5
o_4
o_3
o_2
o_1
o_15
o_14
o_13
o_12
o_11
o_10
o_9
o_8
o_7
o_6
o_5
o_4
o_3
o_2
o_1
\
OUT_15 OUT_14 OUT_13 OUT_12 OUT_11 OUT_10 OUT_9 OUT_8 OUT_7 OUT_6 OUT_5 OUT_4 OUT_3 OUT_2
OUT_1 OUT_0 \
) register16bit wn=wn wp=wp*2
ends DSP
o_0
//end of subcircuits
//====================================END OF ALU=====================================
///////////////////////////////////////////////////////////////////////
// Subcircuit: Left Shift
// Created by: Sung Joon Kim, Team NAND, Project_DIC
// Date: April 25, 2010
// a: 16-bit binary input number. a15:MSB a0:LSB
// b: 00=1-bit shift
//
01=2-bit shift
//
10=3-bit shift
//
11=4-bit shift
// z: shifted result. z15:MSB z0:LSB
///////////////////////////////////////////////////////////////////////
// How This Left Shift Works:
//
// The Leftshift is divided into several subcircuits.
// b1b0 are decoded into 4-bit number s4s3s2s1.
// Only one of the sX's is on at a time.
// sX is responsible for leftshfting the input by X bit(s).
///////////////////////////////////////////////////////////////////////
//--------------------------------------------------------------------// Cell name: ls1bit
// Description: This subcircuit shifts inputs left by 1bit
//--------------------------------------------------------------------subckt ls1bit Vdd Vss a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 s1 c0 c1 c2 c3 c4 c5 c6
c7 c8 c9 c10 c11 c12 c13 c14 c15
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Ms1g (c0 s1 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms10 (c1 s1 a0 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms11 (c2 s1 a1 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms12 (c3 s1 a2 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms13 (c4 s1 a3 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms14 (c5 s1 a4 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms15 (c6 s1 a5 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms16 (c7 s1 a6 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms17 (c8 s1 a7 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms18 (c9 s1 a8 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms19 (c10 s1 a9 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms110 (c11 s1 a10 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn
pd=3u+wn m=mult
Ms111 (c12 s1 a11 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn
pd=3u+wn m=mult
Ms112 (c13 s1 a12 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn
pd=3u+wn m=mult
Ms113 (c14 s1 a13 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn
pd=3u+wn m=mult
Ms114 (c15 s1 a14 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn
pd=3u+wn m=mult
\
\
\
\
\
ends ls1bit
// End of subcircuit definition.
//------------------------------------------------------------------------// Cell name: ls2bit
// Description: This subcircuit shifts the inputs left by 2 bits
//------------------------------------------------------------------------subckt ls2bit Vdd Vss a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 s2 c0 c1 c2 c3 c4 c5 c6
c7 c8 c9 c10 c11 c12 c13 c14 c15
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Ms2g1 (c0 s2 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms2g2 (c1 s2 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms20 (c2 s2 a0 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms21 (c3 s2 a1 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms22 (c4 s2 a2 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms23 (c5 s2 a3 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms24 (c6 s2 a4 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms25 (c7 s2 a5 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms26 (c8 s2 a6 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms27 (c9 s2 a7 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms28 (c10 s2 a8 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms29 (c11 s2 a9 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms210 (c12 s2 a10 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms211 (c13 s2 a11 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms212 (c14 s2 a12 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms213 (c15 s2 a13 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
ends ls2bit
// End of subcircuit definition.
//------------------------------------------------------------------------// Cell name: ls3bit
// Description: This subcircuit shifts the inputs left by 3 bits
//------------------------------------------------------------------------subckt ls3bit Vdd Vss a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 s3 c0 c1 c2 c3 c4 c5 c6
c7 c8 c9 c10 c11 c12 c13 c14 c15
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Ms3g1 (c0 s3 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms3g2 (c1 s3 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms3g3 (c2 s3 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms30 (c3 s3 a0 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms31 (c4 s3 a1 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms32 (c5 s3 a2 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms33 (c6 s3 a3 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms34 (c7 s3 a4 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms35 (c8 s3 a5 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms36 (c9 s3 a6 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms37 (c10 s3 a7 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms38 (c11 s3 a8 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms39 (c12 s3 a9 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms310 (c13 s3 a10 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms311 (c14 s3 a11 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms312 (c15 s3 a12 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
ends ls3bit
// End of subcircuit definition.
//------------------------------------------------------------------------// Cell name: ls4bit
// Description: This subcircuit shifts the inputs left by 4 bits
//------------------------------------------------------------------------subckt ls4bit Vdd Vss a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 s4 c0 c1 c2 c3 c4 c5 c6
c7 c8 c9 c10 c11 c12 c13 c14 c15
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Ms4g1 (c0 s4 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms4g2 (c1 s4 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms4g3 (c2 s4 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms412 (c3 s4 Vss Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms40 (c4 s4 a0 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms41 (c5 s4 a1 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms42 (c6 s4 a2 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms43 (c7 s4 a3 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms44 (c8 s4 a4 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms45 (c9 s4 a5 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms46 (c10 s4 a6 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms47 (c11 s4 a7 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms48 (c12 s4 a8 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms49 (c13 s4 a9 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms410 (c14 s4 a10 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
Ms411 (c15 s4 a11 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
ends ls4bit
// End of subcircuit definition.
//----------------------------------------------------------------------// Cell name: b2s2
// Description: This decodes b1b0 to s2 so that only when b1b0=01, s2=1
//
and leftshift by 2-bit can be implemented.
//----------------------------------------------------------------------subckt b2s2 Vdd Vss b0 b1 s2
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Invb1 (Vdd Vss b1 b1b) ece3663Inverter
Invb0 (Vdd Vss b0 b0b) ece3663Inverter
M1 (b1b b0 y2 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
M2 (b1b b0b y2 Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
M3 (Vss b0 y2 Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
buff1 (Vdd Vss y2 link) ece3663Inverter
buff2 (Vdd Vss link s2) ece3663Inverter
ends b2s2
// End of subcircuit definition.
//----------------------------------------------------------------------// Cell name: b2s3
// Description: This decodes b1b0 to s3 so that only when b1b0=10, s3=1
//
and leftshift by 3-bit can be implemented.
//----------------------------------------------------------------------subckt b2s3 Vdd Vss b0 b1 s3
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
Invb1 (Vdd Vss b1 b1b) ece3663Inverter
Invb0 (Vdd Vss b0 b0b) ece3663Inverter
M1 (Vss b0b y3 Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
M2 (b1 b0 y3 Vdd) ami06P w=wp l=lp as=1.5u*wp ad=1.5u*wp ps=3u+wp \
pd=3u+wp m=mult
M3 (b1 b0b y3 Vss) ami06N w=wn l=ln as=1.5u*wn ad=1.5u*wn ps=3u+wn \
pd=3u+wn m=mult
buff1 (Vdd Vss y3 link) ece3663Inverter
buff2 (Vdd Vss link s3) ece3663Inverter
ends b2s3
// End of subcircuit definition.
//-----------------------------------------------------------------------// Cell name: LeftShift
// Description: combines all of the above subcircuits into one.
//
Any combination of b1b0 can be used to shift the input
//
by the desired amount.
//-----------------------------------------------------------------------subckt LeftShift Vdd Vss a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 b0 b1 z0 z1 z2 z3 z4
z5 z6 z7 z8 z9 z10 z11 z12 z13 z14 z15
parameters wp=3u wn=1.5u ln=600n lp=600n mult=1
b2s1
b2s2
b2s3
b2s4
(Vdd
(Vdd
(Vdd
(Vdd
shift1 (
c7 c8 c9 c10
shift2 (
c7 c8 c9 c10
shift3 (
c7 c8 c9 c10
shift4 (
c7 c8 c9 c10
Vss
Vss
Vss
Vss
Vdd
c11
Vdd
c11
Vdd
c11
Vdd
c11
b0
b0
b0
b0
Vss
c12
Vss
c12
Vss
c12
Vss
c12
b1
b1
b1
b1
s1)
s2)
s3)
s4)
ece3663NOR2
b2s2
b2s3
ece3663AND2
a0 a1 a2 a3 a4 a5 a6
c13 c14 c15) ls1bit
a0 a1 a2 a3 a4 a5 a6
c13 c14 c15) ls2bit
a0 a1 a2 a3 a4 a5 a6
c13 c14 c15) ls3bit
a0 a1 a2 a3 a4 a5 a6
c13 c14 c15) ls4bit
bc0 (Vdd Vss c0 x0) ece3663Inverter
bc01 (Vdd Vss x0 z0) ece3663Inverter
bc1 (Vdd Vss c1 x1) ece3663Inverter
bc11 (Vdd Vss x1 z1) ece3663Inverter
bc2 (Vdd Vss c2 x2) ece3663Inverter
bc21 (Vdd Vss x2 z2) ece3663Inverter
bc3 (Vdd Vss c3 x3) ece3663Inverter
bc31 (Vdd Vss x3 z3) ece3663Inverter
a7 a8 a9 a10 a11 a12 a13 a14 a15 s1 c0 c1 c2 c3 c4 c5 c6
a7 a8 a9 a10 a11 a12 a13 a14 a15 s2 c0 c1 c2 c3 c4 c5 c6
a7 a8 a9 a10 a11 a12 a13 a14 a15 s3 c0 c1 c2 c3 c4 c5 c6
a7 a8 a9 a10 a11 a12 a13 a14 a15 s4 c0 c1 c2 c3 c4 c5 c6
bc4 (Vdd Vss c4 x4) ece3663Inverter
bc41 (Vdd Vss x4 z4) ece3663Inverter
bc5 (Vdd Vss c5 x5) ece3663Inverter
bc51 (Vdd Vss x5 z5) ece3663Inverter
bc6 (Vdd Vss c6 x6) ece3663Inverter
bc61 (Vdd Vss x6 z6) ece3663Inverter
bc7 (Vdd Vss c7 x7) ece3663Inverter
bc71 (Vdd Vss x7 z7) ece3663Inverter
bc8 (Vdd Vss c8 x8) ece3663Inverter
bc81 (Vdd Vss x8 z8) ece3663Inverter
bc9 (Vdd Vss c9 x9) ece3663Inverter
bc91 (Vdd Vss x9 z9) ece3663Inverter
bc10 (Vdd Vss c10 x10) ece3663Inverter
bc101 (Vdd Vss x10 z10) ece3663Inverter
bc110(Vdd Vss c11 x11) ece3663Inverter
bc111 (Vdd Vss x11 z11) ece3663Inverter
bc12 (Vdd Vss c12 x12) ece3663Inverter
bc121 (Vdd Vss x12 z12) ece3663Inverter
bc13 (Vdd Vss c13 x13) ece3663Inverter
bc131 (Vdd Vss x13 z13) ece3663Inverter
bc14 (Vdd Vss c14 x14) ece3663Inverter
bc141 (Vdd Vss x14 z14) ece3663Inverter
bc15 (Vdd Vss c15 x15) ece3663Inverter
bc151 (Vdd Vss x15 z15) ece3663Inverter
ends LeftShift
// End of subcircuit definition.
// End of Leftshift unit
V. Multiplier simulation
InA<3>
InB<3>
Out<3>
InA<2>
InB<2>
Out<2>
InA<1>
InA<0>
InB<1>
InB<0>
Out<1>
Out<0>
Simulation: 00000010 X 00000011 = 0000000000000110
Results: This simulation shows the results of our working multiplier. In order to get a 16bit output, our
multiplier allows for the multiplication of two 8bit binary numbers. The first column shows the last 4 bits of
input A, where the top graph is bit A3, while the bottom bit is A0. The second column shows the last 4 bits of
input B, and the third column shows the last 4 bits of the output S. All other bits not included in these graphs are
0. From these graphs, you can see the value of A is 0010, and the value of B is 0011 for 5ns. Looking at the
output, you see the result S is 0110, a valid result for the multiplication of 0010 and 0011. The next figure
shows the full output of S, with bit S15 at the top left, down to S0 at the bottom right, further demonstrating the
correctness of the multiplier.