Using Simulation Techniques to Guarantee
Successful Backplane Design
Shahana Aziz, Muniz Engineering Inc.
(301) 286-5462
Shahana.Aziz@gsfc.nasa.gov
INTRODUCTION
With designs today requiring faster and faster operational speeds, system architectures must address
the need for higher bandwidth to deliver competitive and cost effective products and designs that
meet all design requirements. Backplane designs are no longer simple, requiring only the transport of
signals between cards at a low throughput. Complex systems now require larger number of loads,
higher throughput and dense signal connectivity to meet project requirements. Thus, care must be
taken to properly engineer a backplane design capable of operating at these higher speeds,
delivering clocks and data at frequencies from the tens of MHZ to hundreds of MHz with devices
driving at ever increasing edge rates.
Successful backplane design requires careful analysis, which can no longer be done by following the
“rule of thumb” methodology. Taking variations in loading, device drivers and receivers combinations,
number of slots, density and design margin requirements into consideration – it is no longer practical
to design a backplane without the use of proper analysis and simulation tools. This ensures a design
that will meet all performance metrics. Simulation also guarantees success without resorting to
multiple CAD spins, saving both time and money and providing a higher degree of confidence in the
delivered result.
PROBLEMS THAT EXIST WITH BACKPLANE DESIGN
Whether doing a backplane or a standalone printed circuit board design, an engineer must address
several design challenges. In addition to the general list of problems that exist with any circuit board
design –backplane design includes the added complexity of requiring a design solution that can work
across a range of multiple design variables. For example – a multi slot backplane may need to
accommodate plug-in cards with different possible driver and receiver combinations, and a varying
number of loads. Thus the engineer must consider these variable parameters and ensure that the
solution behaves predictably and reliably across all conditions. Finding this optimal solution under a
changing load condition is not a trivial problem and would not be possible without using the proper
simulation tools that can provide results for all corner cases quickly and accurately.
ADVANCED TOOLS PROVIDE A COMPLETE SOLUTION
The use of advanced simulation tools makes it an easy matter to analyze every aspect of backplane
design. Tools provide a real world environment by importing not only the backplane layout
information, but the information on the plug-in cards as well – thus in simulation the engineer can
“virtually” plug in different loads and analyze the results accordingly. An engineer can analyze how
the loading and parts selection effects issues such as undershoot, overshoot, ringing, crosstalk and
timing at the various destinations, and make enlightened decisions about including or excluding
termination solutions on the backplane, the choice of backplane trace impedance, backplane
dimensions and slot distances. Engineers can also drive back design requirements to the plug-in card
designers such as driver/receiver component selection, termination schemes etc. This environment
provides the capability of determining a complete system solution.
The topic of this paper is to look at the various features of Mentor’s Interconnectix Synthesis (IS) and
Sigrity Inc’s Speed2000 toolset and how these features enable successful and complete backplane
simulation. The IS tool components used to create the simulation environment were IS Analyzer and
IS Multiboard. This paper takes a step-by-step look at creating the simulation environment, setting up
the simulation scenarios and analyzing the results. The following sections provide examples of the
different problem areas that were addressed through the use of the IS and Speed2000 toolsets.
SETTING UP THE MULTIBOARD ENVIRONMENT
The Backplane simulation environment is comprised of the following components:
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1. Individual plug-in card simulation models
2. Backplane simulation model
3. Interconnection matrix
4. Device models
5. Noise rules and simulation stimulus
Individual plug-in card simulation models can be IS files or electrical board descriptions. If using an IS
file – than the entire board layout and modeling information is exported as part of the file. If creating
an electrical board description model, than one must include at a minimum the information that
pertains to the backplane interfaces. In this backplane design example, as the plug-in cards were also
designed in house, IS files of the load cards were used. For the backplane an IS model must be used
so that the simulations can be run from the IS environment.
Figure 1: Backplane IS main window view
The IS Multiboard environment was used to create the interconnection matrix – this defined the
backplane and associated plug-in card connectivity relationship. Figure 2 shows the spreadsheet
view from Multiboard where all the plug-in cards are defined.
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Plug-in cards can be either included or excluded in the simulation to provide a variation on backplane
loading. Results can then be viewed under the various loading possibilities to see what works and
what does not.
Figure 2: Multiboard System Spreadsheet
Next the mating connectors were defined, and the pin to pin connectivity was compiled in a
spreadsheet. Mating pins can be associated by either pin number or net. This is shown in Figure 2.
Figure 3: Connector Mating Matrix
Device Model information is the next important element in the simulation environment. Plug-in card
driver/receiver IBIS models are defined in the individual card model files. Connector model files are
defined in the backplane IS file.
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Connector models, also known as mated model files (mmf’s) contain information on the pin-to-pin
resistance, capacitance and inductance. This gives the simulation real world information about the
mating contact parasitics, thus the simulation does not simply assume an ideal pass through
connector.
Finally, noise rules and stimulus information was defined in the backplane simulation IS file by
classifying nets, defining noise criteria for overshoot, undershoot, crosstalk, timing etc, and defining
the bus throughput pulse trains. Once setup was complete, simulations were run for all problem
areas.
In the case of Speed2000, setup consisted of exporting a speed (.spd) file using the Speed translator.
This .spd file can then be modified to include the appropriate device models required for power
integrity simulations. Current step stimulus is also provided to simulate voltage fluctuations across the
backplane under worse case transient conditions.
PROBLEM EXAMPLES
The following sections provide some of the simulation results. Simulations were run to identify
problems with overshoot/undershoot, crosstalk, timing and validate the affectivity of decoupling
capacitors and transient current response. These examples show the results observed during PCI
bus simulations in an 8 slot CompactPCI backplane, however this methodology can be used for any
type of bus signaling required on a high speed backplane.
Signal Integrity (SI) Analysis
The 1st example shows how multi board was used to identify possible SI problems under the various
loading conditions. The example looks at the PCI bus running across the backplane at a clock rate of
33 MHz and 16.5 MHz data toggle rate. Though this bus speed is not exceedingly fast, due to the
high edge rates of the driver part required on the daughter cards, SI problems were still an issue.
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The parts being used on the daughter card designs have a datasheet specified maximum tolerance of
500 mV of undershoot. IS Multiboard was used to measure the undershoot that would be seen at the
devices with loads ranging from a minimum of 2 to a maximum of 6 plug-in cards.
The first simulation was run with only the 10-Ohm stub terminating resistors at the plug-in cards, as
specified in the CompactPCI specification. However in this situation the undershoot exceeded 900mV
worst case, and was typically observed to be ~700 mV with a fully loaded backplane. Regardless of
the loading it was seen that the absolute maximum tolerance of the part was being violated which
could affect the long-term reliability of the device according to the device vendor.
Figure 4: Undershoot value in a 2 load system with only a
10-Ohm stub terminating resistor
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Figure 5: Undershoot value in a 6 load system with only a
10-Ohm stub terminating resistor
Figure 4 and Figure 5 show the undershoot expected with just the 10 Ohm stub terminating resistor
under a 2 load and 6 load condition respectively. The violation can easily be seen. Thus it was
determined that additional termination had to be added on the backplane to reduce the undershoot to
acceptable levels.
Part Selection Guidance
The next part of the simulation investigated additional backplane termination options. To clamp the
additional undershoot seen on the PCI bussed signals, external diodes were chosen for the
backplane and placed at the far end beyond the final slot. IS simulations were done using two
different types of diodes – one with a .5V forward voltage drop and the other 1V.
The 1st simulation was run with the 1V part. Again simulation results were compiled under the
different loading conditions looking at different driver/receiver combinations.
With this diode used, it was seen that the change in undershoot is marginal – reducing the
undershoot by at best 50 mV, which was not sufficient.
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Given that the goal was to minimize the undershoot to around 500mV, the 2 nd simulation was run with
a diode with .5V forward voltage drop. Using this diode in the simulation a greater improvement was
seen. The same combinations were simulated, this time with a much better result. With a lightly
loaded (2 cards in the system) backplane the undershoot was seen to be at worse case 700 mV,
however, when simulated with the expected operational load (6 plug-in cards), it was seen that the
undershoot was managed to around 400 mV, which was well within the device requirements. The
typical case is shown in Figure 6.
Figure 6: Simulations comparing the no diode condition with the
2 different types of diodes
Table 1 and Table 2 shows a summary listing of the different cases run and the results obtained.
Table 1: Simulation results table with worst case undershoot values
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Undershoot Undershoot
Driver Receiver
w/ Diode
w/o Diode
Slot 8
Slot 5
573.3 mV
677.1 mV
Slot 8
Slot 4
528 mV
702 mV
Slot 8
Slot 3
523.6 mV
681.7 mV
Slot 8
Slot 2
578.1 mV
697 mV
Slot 8
Slot 1
649.4 mV
699.9 mV
Table 2: Simulation results table with typical undershoot values
Undershoot
Driver
Receiver w/ Diode
Undershoot
w/o Diode
Slot 8
Slot 1
735.7 mV
763.4 mV
Slot 5
Slot 8
229.2 mV
604.1 mV
Slot 4
Slot 8
393.8 mV
458.3 mV
Slot 3
Slot 8
413.4 mV
634.8 mV
Slot 2
Slot 8
442.6 mV
662.6 mV
Slot 1
Slot 8
407.2 mV
637.4 mV
It is also possible to use the simulation environment to explore other options for mitigating the
problem. For example, the 10-Ohm stub terminating resistor value can be changed to slow down the
edge rate and reduce undershoot. Figure 7 shows the resultant waveform of using 25-Ohm stub
terminating resistor without the addition of a diode contrasted to having a 10-Ohm stub-terminating
resistor with no diode and with one.
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Figure 7: Simulations Comparing Various Options: 10 Ohm only,
10 Ohm with no Diode, 25 Ohm with no diode
However, such a chance may affect bus timing, which needs to be analyzed completely before
choosing this option as a solution. The simulation tool can also provide this needed information. Thus
the IS environment provides all the necessary signal integrity and timing values needed to make an
engineering decision on the optimum termination scheme, part type and part value.
Timing Analysis
This example looks at how IS was used to analyze signal timing across the backplane. To analyze
timing issues of distributing high speed signals across the backplane, Multi board was again used to
observe the slot to slot routing delays, and rise and fall times of the signals to determine whether all
the bus timing constraints were met. The simulation tool’s waveform viewer allowed markers to be set
to make accurate timing measurements as one would do using an oscilloscope in the lab. The tool
also allows reporting capabilities that provide a results summary.
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Figure 8 displays the typical rise and fall time of a data bit. Figure 9 displays the skew between the
longest and shortest routed trace in the data bus. This ensured that the trace routes were similar
enough not to cause excessive skew at the receiver ends.
Figure 8: Rise and Fall time marker
Figure 9: Skew between Data Bus bits
It is also possible to run simulations in batch mode to create a timing report rather than observe the
waveforms one by one. This is a faster way to review a large set of timing data to identify any
possible timing problems. Using the System Net Delay feature it was possible to generate a report
that will sums up all the board delays as a signal travels across a backplane and multiple boards and
provide a matrix of every driver to every receiver.
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An example from a system net delay report is given below:
BIC/1/pinInst/U7-AK10 HK_Dummy/1/pinInst/U30-246 (Rise 2.164ns 5.379ns)(Fall 2.606ns 5.869ns)
This report means that the delay from the rising edge of U7-AK10, the driver, to the two threshold
points on the rising edge of the receiver, U30-246, is equal to 2.164 and 5.379 ns. In this case, 2.164
is used for worse case analysis (The receiver begins to change logic states), and 5.379 is used for
best case analysis - the receiver has switched high. Similarly on a falling edge, from the driver to the
receiver threshold points, two measurements are provided. From this information it is possible to
conclude that the edge rate is about 3.2 ns. IS can report delays at the pin or the die, and in this
report the information was provided for the pin.
Mitigating Crosstalk
Since a backplane is used to distribute a large number of signals between cards, crosstalk must be
taken into careful consideration. The backplane in this paper was designed to distribute high-speed
clock signals between the slots. Both a 33 MHz clock and an 80 MHz clock was distributed across the
backplane which made it imperative to consider possible crosstalk issues and mitigate any potential
problems.
IS generates crosstalk reports which can be analyzed to determine what the worst case crosstalk
may be on the victim nets and which nets are the associated aggressors. Once this is identified, the
engineer can take steps as needed to reduce or eliminate the crosstalk condition. These guidelines
can then be provided to the layout designer, for better routing rules, optimal spacing and routing layer
selection. Figure 10 shows a section of a crosstalk violation report.
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Figure 10: Crosstalk Report
Verifying Characteristic Impedance
Another feature of the simulation environment is the capability of measuring the characteristic
impedance of a signal trace. Signal integrity, timing, crosstalk – all issues are dependent upon the
impedance on the trace, thus trace impedance is another important design parameter. Using IS,
importing the board construction, material properties, and trace width information the actual value of
impedance could be reported for both single ended and differential traces. The expected versus
observed was than compared and changes were made to meet the desired impedance.
Predicting Input Impedance
Simulations also provide a means to guaranteeing power integrity along with signal integrity.
Simulation tools can compute the input impedance along various points of the backplane allowing
analysis of possible voltage drops during transient events. Incorporating the board information and
models for the capacitors used for decoupling, Speed 2000 can calculate the impedance across a
range of frequencies.
In the following example the backplane decoupling was simulated to see if bulk capacitors were
sufficient to meet low frequency (at <50 MHz) impedance requirements. Assuming 10% ripple on
each supply, target impedance was:
2.5V * 10/100/1 = .25 Ω (1A current draw)
3.3 * 10/100/3 = .11 Ω (3A current draw)
5 * 10/100/1 = .5 Ω (1A current draw)
The following figures show the impedance curve across the frequencies for all three voltage supplies
without and without the decoupling capacitors.
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Figure 11: 2.5V Supply Input Impedance
Figure 12: 3.3V Supply Input Impedance
Figure 13: 5V Supply Input Impedance
Simulating Voltage Transients
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Taking this simulation environment a bit further, it is possible to predict the noise seen on each supply
for a given transient current curve. By important a current waveform stimulus, Speed 2000 can plot
the expected voltage supply behavior curve versus time. The following two figures plots the 3.3V and
5V supply under worse case current conditions with and without capacitors. It is obvious that the
current takes a lot longer and is unstable for a larger duration without the use of decoupling
capacitors. This method can be used to determine the quantity and type of capacitors needed to
guarantee power integrity.
Figure 14: 3.3V Supply Transient Behavior
Figure 15: 5V Supply Transient Behavior
Ensuring Design Margin
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Simply determining a solution that works under one condition is not sufficient. It is also necessary to
study design margins under the various operational scenarios.
Through the use of corner case simulation options, varying the stimulus pattern to include jitter it is
possible to generate an eye pattern diagram to analyze design margins. The IS waveform analyzer
includes an eye pattern generator tool to perform this simulation.
COMPARISONS TO THE REAL WORLD
A simulation methodology is only useful if a good correlation exists to the real world. Comparison
measurements should always be taken to validate the simulation environment, the part models, and
the results. By taking a few key measurements and understanding how they compare to the
simulation, it is possible to then interpolate additional measurements from the simulated. Having an
accurate simulation environment can be the basis of reducing the number of real measurements that
need to be taken, thus saving time, money, and reducing stress on the actual hardware. But the key
to reducing the laboratory measurement phase, is a solid simulation environment.
The following three sets of waveforms show correlation measurements between the simulated result
of a PCI data bus switch on a backplane connector pin and the same waveform as measured on the
actual hardware.
Figure 16 shows the simulated waveform (left) and actual measurement (right) of a PCI AD bit as
seen on a backplane connector pin when using the original 10 Ohm stub terminating resistor and no
additional diode on the backplane. Both agree within ~100 mV with the simulated predicting .81V
undershoot and measurement showing .70V undershoot.
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Figure 16: Simulated versus Actual Measurement of
PCI AD bit with 10 Ohm Stub Resistor
Figure 17 shows the simulated waveform (left) and actual measurement (right) of a PCI AD bit as
seen on a backplane connector pin when using a diode in addition to the 10 Ohm stub resistor. Both
agree within less than 100 mV with the simulated predicting .58V undershoot and measurement
showing .56V undershoot.
Figure 17: Simulated versus Actual Measurement of
PCI AD bit with 10 Ohm and Diode
Finally, Figure 18 shows the simulated waveform (left) and actual measurement (right) of a PCI AD bit
as seen on a backplane connector pin when using no diode but changing the stub resistor to 25.
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Again, both waveforms agree within less than 100 mV with the simulated predicting .21V undershoot
and measurement showing .22V undershoot.
Figure 18: Simulated versus Actual Measurement of
PCI AD bit with 25 Ohm Stub Resistor
In all cases, the high correlation validates the simulation methodology and creates a high degree of
confidence in the remainder of the simulated results.
PRACTICAL APPLICATION OF THE SIMULATION METHODOLOGY
The examples in this paper were taken from a backplane design completed at NASA-GSFC for the
James Webb Space Telescope’s Integrated Science Instrument Module Command and Data
Handling Subsystem Backplane prototype design. Mentor’s IS and Sigrity’s Speed2000 toolsets were
used to detect and mitigate all potential problems during the layout phase before fabricating the
board.
CONCLUSION
As parts get faster, higher throughput is required, and cost and schedule requirements become more
competitive – it is becoming imperative to use a tool to aid in the design of a complex high-speed
backplane. The advantages of using the currently available state of the art tools are numerous and
the results provided by these tools are of high fidelity and great accuracy. The calculations provided
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by the tool contain in-depth information that could not be easily obtained from a laboratory
environment and these simulations can be run in a fraction of the time required to make
measurements in a lab. Not only that, but simulating the hardware performance during the layout
phase makes it possible to identify and mitigate problems well before fabricating the hardware.
Ultimately, this design approach provides a technically superior solution and greatly eliminates
multiple risks from a project’s development cycle.
REFERENCES

http://www.eigroup.org/ibis/

http://www.actel.com/techdocs/models/ibis.html

http:// www.mentor.com/icx

http://www.sigrity.com/support/techpapers/support_tech_doc.htm
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