Exercise 8
Multiplexer Design
This exercise is an introduction in the layout editors Virtuoso Layout Editor,
Virtuoso Layout Accelerator (Layout XL) and Assura verification interactive
products. We will create a multiplexer layout using different commands in
Virtuoso Layout Editor. As a first step we need a new directory to start
CADENCE and which will hold all projects and results. The way we star
CADENCE depends on the used technology. In that case we use AMS 0.35m Si
CMOS metal technology and to start CADENCE go to:
source ~radonov/scripts/.ams350
ams_cds -tech c35b3 -mode fb
The most common shortenings are:
CIW – Command Interpreter Window;
LMW – Library Manager Window;
VLEW – Virtuoso Layout Editor Window;
LSW – Layer Selection Window.
Inverter Design
1. Inverter Schematic and Symbolic view
Before creating a layout view, it is necessary to at first to create the schematic
and symbol view. All views should be kept in a library. To create it in LMW,
go to: File  New  Library. Type the library name in the Library Name
form and attach it to appropriate technology file (in this case TECH_C35B3).
Inverter schematic view
1) Select the created library and in LMW select: File  New  Cellview
2) In the form for new cell creating fill the following:
Library: <your_library name>
Cell Name: Inv
View Name: schematic
A schematic window form appears. In the table below are listed the necessary
elements and the library names they are coming from.
Library
PRIMLIB
PRIMLIB
analogLib
analogLib
Elelment
nmos4
pmos4
vdd
gnd
Type of view
symbol
symbol
symbol
symbol
3) To add element: Add  Instance
You can use the Browse button as well. The elements can be placed multiple
times on the working area in schematic editor. With changing the element
name in Add Instance form you can place all the elements. IN order to
cancel the elements adding, press Esc button from the keyboard.
4) To add pins: Add  Pin. In the pin form type the name of the pin and set
its direction: IN; OUT; IN/OUT
5) After placing all elements, set the wires between them: Add  Wire
6) Save the circuit with the command: Design  Check and Save.
Inverter’s symbolic view
1) Start with the command Design  CreateCellview  FromCellView
2) In the new form that appeared leave the options by default and press OK.
3) In the next form you see, set the pins places – for the IN pin – left; for the
OUT pin – right.
After few seconds a symbol editor window appears. Here you can shape the
inverter’s symbol. The default shape is a rectangle. To change the shape, go
to Add  Shape.
4) The symbol name can be changed as
you select the field “[@partName]”
and press “q” button from the keyboard.
Type the name in Label field.
5) Save the view and close the symbolic
editor.
Inverter symbolic view
2. Creating the Inverter Layout
In LMW go to File  New  Cellview and fill in the fields as shown below:
Library: <library name>
Cell Name: Inv
View Name: layout
Press the button OK to open the layout editor VLEW and the window LSW.
The VLEW working area is separated on 4 parts as the top-right part is the place
you work (Window  Pan or press Tab from the keyboard).
Creating Instances for N- and P-Transistors
To create the N and P-transistor:
1. Choose Create – Instance.
The Create Instance form appears.
2. Type in the form:
Library: PRIMLIB
Cell Name: nmos4
Cell View: layout
Note: This form is called a layout editor options form, which means, it appears
for the duration of the Create Instance command. Look at the buttons on the
form; instead of OK, there is a Hide button. The Hide button lets you hide the
form while you continue to use Create Instance.
3. Move the cursor in VLEW
4. Pressing the right mouse button rotate the transistor on 90 degrees.
Move the cursor to coordinates X=4.3, Y=3 and press the left mouse
button to place the element.
5. To stop the command repeating, press Esc.
6. To place the PMOS transistor repeat to step 5.
Connecting the Inputs and Outputs
Now that you have placed the n- and p-transistors, you need to create
connections to tie them together and create an inverter.
Selecting Layers in the LSW
Every layer in your library is assigned a purpose, such as net or drawing.
Most layouts us layers with purposes of drawing, so by default the Layer
Selection Window (LSW) shows all the layers that are defined as drawing in
your library technology file. The abbreviation dg after each layer name
means drawing.
Click the metal1 dg layer in the LSW. Be sure to use the left mouse button
to select the entry layer. If you click a different mouse button on a layer in
the LSW, you will change the selectability or visibility of the layer.
The metal1 layer is outlined in bold and appears at the top of the LSW. This
tells you metal1 dg is the current entry layer. The layout editor prompts refer
to this as the entry layer.
Connecting the Output
To connect the output of the two transistors,
1. Choose Create – Rectangle. The Create Rectangle form appears.
The prompt in the layout window and CIW reads:
Point at the first corner of the rectangle
2. Click X = 7.5, Y = 15.5 to create the first corner of the rectangle and press the
left button. The prompt in the layout window and CIW reads
Point at the opposite corner of the rectangle
A rectangle appears and stretches as you move the cursor.
3. Click X = 8.5, Y = 19.5 to create the opposite corner of the rectangle.
You have completed the rectangle that connects the output of the two
transistors.
Output connecting
Input connecting
2. Connecting the Input
You are ready to connect the inputs. Use the Create Path command to connect
the inputs for the transistors on the poly1 layer.
Paths are shapes defined by a centerline and a width. You set the width in the
Create Path form and create the path centerline.
1) In the LSW, click the poly1 dg layer.
The poly1 layer appears at the top of the LSW.
The system still prompts you to create rectangles because repeat mode is on.
You do not need to manually stop the Create Rectangle command. It stops
automatically when you choose any other Create or Edit command.
2) Choose Create – Path.
The Create Path form appears. The width is set to 1 micron, which is the
minimum width for the poly1 layer. Use right align option and leave the other
options settings by default.
3) The prompt in the layout window and CIW reads
Point at the first point of the path.
4) The path ends at the bottom right corner of PMOS transistors gate. Double
click with the right mouse button to cancel the command.
5)Press button “o” from the keyboard to make a connection between gate layer
POLY1 and MET1. This contact is necessary for connecting the inverter’s
scheme of the multiplexer. Choose contact P1_C.
6) Move the contact to coordinates X=2.7, Y=14.6.
7) Press button Esc
Adding Power and Ground connections
Polygons are shapes defined by any number of points. Polygons must be closed;
that is, the first point and the last point must be the same. The layout editor can
close the polygon for you automatically.
Adding power connection
1) Select the upper layer of the PMOS transistor
2) Use ruler or button k from the keyboard to draw the guide lines – set 2
microns from left and right in PPLUS layer and 0.7 micron from the
upper layer bound. The width of the power supply bus set to be 2
microns.
3) In LSW choose MET1 dg
4) Choose Create  Polygon and press F3 for additional options. Change
the parameter Snap Mode to L90Xfirst. The Snap Mode parameter
manages the placement and movement of the elements when you draw
the polygon. The option L90 creates two segments suited on 90 degrees
by each other, and Xfirst defines the first segment to be aligned with the
X axis.
5) In VLEW the polygon follows the drawn lines and its starting point is in
the upper left corner of the source in PMOS transistor.
6) To finish the polygon drawing, press Esc.
Note: If you make some error while drawing, press Backspace from the
keyboard so many times as you need to turn back on the stage the error is.
3. Adding ground connections
Use the Copy command to copy and mirror the shape you just created to
build the ground connection.
1) Choose Edit – Copy.
The prompt in the layout
window and CIW reads
Select the figure to be
copied
2) Click the metal1
polygon you just created.
The polygon is selected.
3) Move the cursor slightly
to the right. A copy of the
metal1 polygon follows
the cursor.
You can mirror the copy of the polygon and use it for the ground wire at the
bottom of the inverter. In the Copy form, click Upside Down.
4) Move the mirrored copy of the polygon so it aligns with the metal in the
n-transistor. Click left to place the copy of the polygon.
Mirrored copy
Align the copy of the polygon with the metal in the n-transistor.
The copy of the polygon appears on the metal1 layer.
5) Press the Escape key to stop the Copy command repetition.
Adding N-pocket, contacts to the N-pocket and the
substrate
1) In LWS select layer NTUB dg
2) Press Select Rectangle command
3) The rectangle’s starting point is the upper left
corner of the power supply bus and the end
point is the crossing point between the end of
the PMOS transistor’s N-pocket and the power
supply bus’s right corner.
4) Draw the rectangle and cancel the command
pressing Esc.
When you create an object in VLE, it can be
edited. At first select the object and use one of the
both editing regimes: full or partial. To pass from
one to the other regime press F4 from the
keyboard. You can read the current regime state in
the upper left corner in VLE window.
Adding contacts
The PMOS substrate should be connected to the
power supply.
1) Choose Create  Contact. A new form is
opened
2) In the form Create contact, choose ND_C.
Use the default options.
3) Place the contact on the power supply bus as
shown on the figure.
Inverter layout
For placing a substrate contact to NMOS transistor
follow the same steps and choose contact PD_C instead of ND_C. Place the
contact on the ground bus.
4. Checking Design Rules (DRC)
Before saving the inverter, check the design against your design rules. Interactive
design rule checking is part of Assura™ interactive verification products.
The interactive Design Rule Checker (DRC) uses rules defined in the divaDRC.rul
file. For the tutorial, these rules have been defined for you. For details about the
SKILL functions used to write these rules, refer to the Diva Reference manual.
DRC flags the errors it finds by creating polygons around the errors. The polygons
are created on a layer reserved for markers. The marker layer usually appears as a
blinking layer and is not selectable. DRC removes the error-flag polygons
automatically after you correct the errors and run DRC again.
Starting DRC
1) In VLE choose command Verify  DRC
2) Press button Set Switches and choose the switches: grid, no_erc,
no_info, no_recommendations, no_coverage. The switches determinate
which checks will be implemented.
3) Press OK and start the verification.
In CIW window reads: Total errors found: 0. If there are some errors use
commands:
Verify -> Markers -> Find
Verify -> Markers ->Explain.
To delete markers, go to Verify  Markers  Delete All.
You have completed the inverter layout. However, the layout exists only in
virtual memory. You need to save the design to disk.
To save the design,
Choose Design – Save and close the window.
NAND DESIGN
1. Creating schematic and symbolic NAND view
NAND schematic view
NAND symbolic view
The both views schematic and symbolic have to be created in the same
library as the inverter
2. NAND layout
1) In LMW, choose File  New  Cell View.
2) Fill the form as shown:
Library: < library name>
Cell Name: NAND
View Name: layout
3) Press OK
Adding N- and PMOS transistors
Use command Create  Instance to add N- and PMOS transistors.
1) Choose
nmos4
from
PRIMLIB. Some of the
parameters should be left by
default, others should be
changed. Set width to be 20m
and number of gates – 2.
Deselect
the
following
parameters:
Join all gates
no
Substrate contacts Join all drains
Join all sources
2) Rotate the transistor to 90
degrees before setting its
coordinates to be Х=5.7 and
У=3.
3) Add PMOS transistor (pmos4)
with the same parameters as
those for (nmos4).
4) Set the coordinates to be
Х=5.7, У=17, after the
transistor’s rotation.
5) Cancel the Add command
repetition with pressing Esc.
NAND Input/Outputs connection
Inputs connection
1) In LSW choose layer POLY1 dg
2) Press button ‘p’ from the keyboard to
start creating busses
3) Connect the N- and PMOS gates as
shown in the figure
4) Add the contacts between layers
POLY1-MET1.
Outputs connection
1) Use the line tool (button ‘k’ from the keyboard)
to draw a line with length = 1 micron from
NMOS upper edge mutual contact and one more
line (1 micron) from the middle of the NMOS
drain’s right contact. These lines will be the
guide cursors for inputs connecting
2) In LWS choose layer MET1 dg
3) Press button ‘p’ from the keyboard to create the
busses as you start from PMOS mutual drain
4) Using the second line, on the same manner finish
the bus till the NMOS right drain
5) Cancel the Create Path command pressing Esc
button
Adding power supply and ground busses
Adding power supply busses
To add power supply buss, use the command for
polygon. This bus has to be wider with 2 microns on
the both sides than layer PPLUS for PMOS
transistor and 0.7micron wider than the upper edge
of this layer. The bus width is to 2 microns.
NAND layout
Adding ground busses
Copy the power supply buss to make a mirror and rotate it to horizontal
level. Place the mirror the way to touch the NMOS source left contact.
Adding N-pocket
1) In LSW choose layer NTUB
2) In window VLE press button ‘r’
3) Draw a rectangle similar to inverter’s one
Adding contact to substrate and pocket
Use contact ND_C to connect the PMOS substrates to the source and PD_C
contact for the PMOS transistors substrates.
3. Verifying NAND layout
Check the design rules as you did for the inverter circuit and close the
NAND’s layout.
Multiplexer Design
In this part of the exercise, you will create a hierarchical design. A hierarchical
design is one containing instances of other cells. Those cells, in turn, can contain
instances of cells.
You will create the multiplexer by placing instances of several cells inside the
multiplexer cellview, mux2. Place the following cells from the tutorial library:
mux2_connect, nand2, and Inv, the inverter you created in the previous chapter or
just copied from the master library. Most of these cells contain other cells.
All necessary elements are shown on the table below:
Library
<library name >
< library name >
< library name >
< library name >
analogLib
analogLib
Element
NAND
NAND
NAND
INV
vdd
gnd
Veiw
symbol
symbol
symbol
symbol
symbol
symbol
Creating a New Cellview
1. In the Command Interpreter Window (CIW), choose File – New – Cellview.
The Create New File form appears. In that form set the library, cell, and view
names.
2. Click OK to create the mux2 layout.
A window appears containing just the cellview axes and grid points.
Opening a Schematic for Reference
You can open the schematic view of the mux2 design for reference as you build the
layout view of mux2.
1. Choose File – Open.
The Open File form appears.
2. Click OK or press the Enter key.
Library Name: tutorial
Cell Name: mux2
View Name: layout
Tool: Virtuoso
Library Name: master
Cell Name: mux2
View Name: schematic
The schematic view of the mux2 design appears.
Note: For a better fit of all your windows on your screen, click and hold any corner
of the schematic window and move the mouse until the window is a smaller size.
Then press the f key in the schematic window to fit the schematic drawing within
the resized window.
Creating the First nand2 Instance
You are now ready to place the first instance of the nand2 cell into the mux2
cellview.
1. Move the cursor inside the mux2 layout window and press the i key.
The Create Instance form appears. If you have continued from Chapter 2, the last
cell you placed (ptransistor) is displayed in the form.
2. Type the library, cell, and view names as follows:
3. Click X = 0, Y = 0 to place the first nand2 instance.
The nand2 instance appears
in the mux2 cellview.
4. Press the Escape key to stop
the
Create
Instance
command.
The
Create
Instance form disappears.
5. Press the f key to fit the
design in the window.
6. You need to move to the
right of the nand2. You do
this with the Pan command.
Press the Tab key to start the
Pan command.
7. Click X = 18.0, Y = 18.0 to
move to the right of the
nand2.
Copying the nand2 Instance
You copy the first NAND
instance to create the second NAND instance.
1. Press the c key to start the Copy command.
2. Click anywhere inside the first instance.
The outline and shapes inside the first instance are highlighted.
3. Move the cursor to the right until the second instance aligns with the first.
4. Click to place the copy.
Creating the Inv Instance
Now you place an instance of the inverter layout you created in the previous
chapter or copied
from the master library.
1. Press the Tab key, and click X = 32.0, Y = 18.0 to pan right.
2. Press the i key.
The Copy command is canceled and the Create Instance form appears.
3. In the Create Instance form, type the library, cell, and view names as
follows:
4. You need to mirror the inverter along the X axis. Click Sideways to mirror
the inverter.
5. In the cellview, click X = 40, Y = 0 for the instance origin.
6. Press the Escape key to stop the Create Instance command.
The inverter appears next to the nands. The inverter is not aligned properly
with the nands. You correct this error in the following section.
Editing the Inverter in Place
The inverter you placed in the previous section does not align properly with the
NANDs. You can correct this error by stretching the top half of the inverter up by 1
micron. But you cannot edit the inverter now because you are looking only at an
instance of the inverter cell inside the multiplexer. The inverter does not align with
the NAND.
You could open the inverter cell layout in a separate window and edit the inverter
there, but then you would not be able to see how the inverter aligns with the other
instances in the multiplexer.
The Edit in Place command lets you edit the inverter master cell while viewing it
inside the multiplexer layout. This way, you can edit the inverter instance as it
appears in this cellview and see how it aligns with the NAND next to it.
Opening a Cell to Edit in Place
Open the inverter cell for editing using Edit in Place.
1. Choose Design – Hierarchy – Edit in Place.
The layout editor prompts you to point to a shape in the design to be edited.
2. Click the metal1 polygon at the top or bottom of the inverter.
Note: The transistors are (pcells) parameterized cells. You cannot edit pcells in
place because they must be created by compiling. If you accidentally click on a
shape inside one of the pcells, a message says you cannot edit pcells in place.
When you successfully open the inverter using Edit in Place, you might not notice
any change in the display. Look at the window title to see that you are editing the
Inv layout.
3. Choose Window – Fit Edit.
The Inv layout data is fitted to the window and the border of the inverter is
highlighted in light brown. This confirms you are editing the inverter cell.
You still see the surrounding multiplexer data, but you cannot edit it because
it is at a different level of the hierarchy.
Stretching an Area
Use Stretch to stretch the top of the inverter.
1. Choose Edit – Stretch.
2. You need to define the area you want to stretch. Click X = 29, Y = 18 and
drag the box to a point above and to the right of the area to be stretched.
3. Release the mouse button. The edges you can stretch are highlighted.
The prompt in the CIW reads
Point at the reference point for the stretch
The layout editor often asks for a reference point as you use editing
commands. The reference point is the start-point for the command; for
example, the starting point from which you move a group of objects. In this
case, the reference point is the starting point for the stretch.
The boundary of the instance is still highlighted in light brown. The edges
you can stretch are highlighted in white.
4. Click the top edge of the polygon for a reference point. Move the cursor
up until the edge of the inverter aligns with the NAND.
5. Click to complete the stretch. The inverter and the nand instance now align
correctly. The inverter is still highlighted in light brown to remind you that
you are editing this cell, not the multiplexer.
6. Press the Escape key to stop the Stretch command.
Returning to the Multiplexer
While you edit a cell in place, you cannot edit the surrounding data (in this case,
the other objects in mux2). When you finish editing the inverter in place, you must
return to editing the multiplexer cell.
1. Choose Design – Hierarchy – Return.
Return takes you back to the previous editing level. It also checks whether
you have saved or not. Because you did not save yet, a dialog box appears
asking if you want to save your changes to tutorial Inv layout.
2. Click Yes to save your changes.
Click here to start the stretch. Drag the edge so it aligns with the NAND. The
inverter is saved, and the window title bar shows that you are now editing the
multiplexer (mux2) again.
Creating Pins
Pins show what areas of the multiplexer can connect to routing or other cells when
you placean instance of the mux2 into another design cell.
Note: You create pins coincident with shapes in the instances placed in mux2. If
you make a mistake, it is easier to select and correct pins if the instances in mux2
are unselectable. If you need to make instances unselectable during the following
steps, click the button next to Inst (Instances) in the LSW so it is empty.
1.
2.
3.
4.
5.
6.
Table 1
PIN name
vdd!
gnd!
A
B
SEL
Y
I/O
input/output
input/output
input
input
input
output
Access direction
top, left, right
bottom, left, right
top, bottom
bottom
bottom
right
Layer
met1 dg
met1 dg
met1 dg
met1 dg
met1 dg
met1 dg
1. In the LSW, click the metal1 dg layer.
2. Choose Create – Pin.
The Create Symbolic Pin form appears. You use shape pins in this tutorial,
not symbolic pins.
3. Click the button next to shape pin to open the Create Shape Pin form.
4. In the Create Shape Pin form, type the following in the Terminal Names
field.
vdd! gnd! A B SEL Y You can type any number of names in the Create
Shape Pin (or Create Symbolic Pin) form. Each pin you create is assigned the
next name, from left to right, in the Terminal Names field.
5. Click Display Pin Name to associate the name with the pin.
6. Set the access direction to Top, Left, and Right by clicking Bottom to
turn it off.
7. Create the rectangle for the vdd! pin coincident with the power line at the
top of the multiplexer.
 Start the vdd! pin at corner A.
 Finish the vdd! pin at corner B.
Creating a Guard Ring
In this section, you use Virtuoso® relative object design (ROD) functionality to
create a guard ring around the mux2 design using a multipart ROD object. ROD
functionality is used for defining simple and complex layout objects and their
relationships to each other.
About Multipart Paths
You create a multipart path as the guard ring for the mux2. A multipart path is a
single ROD object consisting of one or more parts at level 0 in the hierarchy on the
same or on different layers. A multipart path consists of a single master path and
one or more subparts. The master path is an ordinary path; however, it is the
defining part of a multipart path; all subparts are based on the master path.
For example, the multipart path shown below has one subpath and one set of
subrectangles. Both the subpath and the set of subrectangles are offset from the
master path
Moving the Design
Before you create the multipart path, you must make room for it. You move the
mux2 design up and to the right.
To move the design:
1. Choose Edit – Select – Select All.
All the elements of the mux2 are highlighted.
2. Choose Edit – Move.
You are prompted in the CIW to point at the reference point for the move.
3. Click X = 0, Y = 0.
You are prompted in the CIW to point at the new location for the move.
4. Click X = 7, Y = 9.5.
The design moves to the right.
5. Press f to fit the design in the window.
Creating the Multipart Path
The best way to create a multipart path is to enter values for the MPP in the Create
Multipart Path form and save the values to a template for future use. Creating
templates for multipart paths allows you to reuse the information to
 Create additional paths
 Edit the path by changing the template

The multipart path you create for this design has a master path, a enclosure
subpath, and a set of subrectangles.
To create the template for this path:
1. Click the diff layer in the LSW.
The diffusion layer is the master path layer.
2. Choose Create – Multipart Path.
The Create Multipart Path form appears.
3. Type these values in the form. The CIW displays warnings. These
warnings do not affect your work.
You are ready to create the metal1 layer as the enclosure subpath.
1. Click Subpart in the Create Multipart Path form.
The ROD Subpart form appears.
2. Click Enclosure Subpath.
The enclosure subpath fields appear.
Table 2
Layer
Choppable
metal1
on
Begin Offset
-0.5
Enclosure
End Offset
Connectivity
-0.5
0.5
Pin
3. Enter these values in the form:
When you choose PIN, a new form appears. Set the following options:
gnd!
Net Name
inputOutput
I/O Type
Bottom, Left,
Access
Right
Direction
Display
Pin No
Name
centerCenter
Reference
Handle
0
Offset X
0
Offset Y
4. Click Add to register this data as subpath parameters.
The data for the enclosure subpath appears in the scroll window at the top of
the ROD Subpart form.
5. Click Apply in the ROD Subpart form to add this data to the template.
The ROD Subpart form remains open.
You are ready to create the contacts as subrectangles.
1. In the ROD Subpart form, click on Subrectangle.
The subrectangle fields appear.
2. Enter these values in the form:
Table 3
Layer
Choppable
Begin
Offset
Enclosure
End Offset
Connectivity
DIFF
on
-0.5
-0.5
0.5
None
3. Click Add to register this data as subrectangle parameters. The data for the
subrectangles appears in the scroll window at the top of the ROD Subpart
form.
4. Click OK in the ROD Subpart form to add this data to the template.
The ROD Subpart form closes.
Save your MPP form values as a template before you draw the MPP in your layout
cellview. Once you enter the last point for the master path, you can no longer make
any changes to the MPP. However, if you save the values as a template, you can
create a similar MPP by loading the template and changing the values as desired.
When you load the template, all the fields display the template data except the Net
Name field, which you must add every time you load a template. If you do not add
the net name, the system beeps and a message appears in the CIW telling you to
add the net name.