Innovative Integration
M44 Hardware Manual
The M44 Hardware Manual was prepared by the technical staff of Innovative Integration, September 1997
For further assistance contact
Innovative Integration
5785 Lindero Canyon Road
Westlake Village, California 91362
PH:
FAX:
email:
WWW:
(818) 865-6150
(818) 879-1770
techsprt@innovative-dsp.com
www.innovative-dsp.com
This document is copyright 1997 by Innovative Integration. All rights are reserved.
VSS\m44\documents\hardware\m44hw.doc
#51032
rev – 3.03
Table of Contents
1.
M44 Hardware Functions .................................................................... 1
1.1
1.2
M44 Hardware Initialization Requirements .............................................................................. 3
PCI Bus Interface ......................................................................................................................... 4
1.2.1 PCI Bus Interface Register Set ............................................................................................. 4
1.2.2 Introduction to PCI Bus Mastering ..................................................................................... 4
1.2.3 Bus Master Transfer Setup and Termination ..................................................................... 5
1.2.3.1
Host DRAM Page Locking ......................................................................................... 5
1.2.4 Bus Slave Setup ...................................................................................................................... 5
1.2.5 Mailbox Access....................................................................................................................... 6
1.2.6 PCI Bus Software support in Developer’s Package ............................................................ 6
1.3
OMNIBUS I/O .............................................................................................................................. 7
1.3.1 I/O Bus Accesses and Hardware RDY Generation ............................................................. 7
1.3.2 I/O Bus Power ...................................................................................................................... 10
1.3.3 I/O Bus Mechanical Specifications ..................................................................................... 10
1.3.4 I/O Bus Timing..................................................................................................................... 11
1.3.5 I/O Bus Module Design Guidelines .................................................................................... 11
1.4
Timers.......................................................................................................................................... 13
1.4.1 AD9850 Direct Digital Synthesizer..................................................................................... 13
1.4.2 8254 Counter-timer ............................................................................................................. 14
1.5
Communication Ports ................................................................................................................ 15
1.6
Digital I/O ................................................................................................................................... 17
1.6.1 Digital I/O Timing ............................................................................................................... 18
1.7
Interrupts .................................................................................................................................... 19
1.8
Multiplexer Control ................................................................................................................... 20
1.9
JTAG Test Bus ........................................................................................................................... 22
2.
Appendices ...........................................................................................23
2.1
Connector pinouts ...................................................................................................................... 24
2.1.1 JP5, JP6, JP9, JP10, P1, P2 - I/O Module I/O Connectors .............................................. 24
2.1.2 JP24-JP27 - I/O Module ‘C44 Bus Connectors ................................................................. 26
2.1.3 JP1, JP2 - Processor Communication Port Headers ........................................................ 28
2.1.4 JP3 – Digital I/O Connector ............................................................................................... 29
2.2
Factory Default Jumper Settings .............................................................................................. 30
2.3
Device Data Sheets ..................................................................................................................... 31
List of Figures
Figure 1: M44 Block Diagram ......................................................................................................................1
Figure 2: M44 Memory Map ........................................................................................................................2
Figure 3: OMNIBUS Control Register Initialization Values .....................................................................3
Figure 4: OMNIBUS I/O Memory Mapping ...............................................................................................7
Figure 5: I/O Module Wait State Generator Example ...............................................................................9
Figure 6: I/O Bus Power Ratings ...............................................................................................................10
Figure 7: OMNIBUS I/O Mechanical Specification .................................................................................11
Figure 8: DDS versus Counter-timer .........................................................................................................13
Figure 9: 8254 Timer Clock Sources ..........................................................................................................14
Figure 10: M44 Communication Port Usage .............................................................................................15
Figure 11: Communication Port Driver Settings ......................................................................................15
Figure 12: Digital I/O Control Registers ...................................................................................................17
Figure 13: Digital I/O Port Timing ............................................................................................................18
Figure 14: Digital I/O Port Timing Parameters ........................................................................................18
Figure 15: External Processor Interrupt Selection, Revisions C and D ..................................................19
Figure 16: External Processor Interrupt Selection, Revision E ...............................................................20
Figure 17: TERM Function Memory Map ................................................................................................20
Figure 18: I/O Module Connector Pinouts ................................................................................................24
Figure 19: I/O Module Bus Connectors .....................................................................................................26
Figure 20: I/O Module Bus Connectors .....................................................................................................27
Figure 21: JP1, JP2 Pin Description ..........................................................................................................28
Figure 22: Digital I/O Connector ...............................................................................................................29
M44 Hardware Manual - 1
1. M44 Hardware Functions
The M44 is a digital signal processor (DSP) card based around the Texas Instruments TMS320C44
processor. The card is compatible with the PCI bus interface and is capable of both bus master and slave
transactions on the host bus. Implementing a modular I/O expansion system, the M44 is particularly suited
to data acquisition and control tasks, and is supported by a collection of OMNIBUS I/O function cards
which provide hardware interfacing to real-world equipment. The M44 is also well suited for I/O slave
activities in existing ‘C4x processor systems, allowing a network of ‘C4x family processors to access data
and control hardware via the external communication port connectors.
The M44’s features include:
1)
2)
3)
4)
5)
6)
7)
8)
TMS320C44 processor (40-60 MHz)
Dual SRAM memory pools (one local, one global)
PCI bus interface (master/slave)
Six channels of on-board timing (on-chip timers or external 8254 and 9850 DDS timebases)
OMNIBUS I/O (two available slots)
Two external communication port connectors
External mux board control connectors (compatible with Mux44)
JTAG hardware emulation support (with passthrough)
The following figure gives a block diagram of the M44.
I/O Module Slot 0
I/O Module Slot 1
Local SRAM
(32K-128Kwords)
TMS320C44 DSP
AD9850 DDS
8254 CTC
PCI Bus Interface
(Master/Slave)
Global SRAM
(32K-512Kwords)
Comm1 Comm4
External
Connectors
PCI Bus
Figure 1: M44 Block Diagram
The following figure gives the processor memory map of the M44.
Function
Digital I/O Data Register
Digital I/O Byte 0 Direction Control
Digital I/O Byte 1 Direction Control
Digital I/O Byte 2 Direction Control
Digital I/O Byte 3 Direction Control
C Language Mnemonic
Address
Bus/Strobe
DIGIO
DIGDIR0
DIGDIR1
DIGDIR2
DIGDIR3
0x300000
0x400000
0x440000
0x480000
0x4C0000
Local Strobe 0
“
“
“
“
2 - M44 Hardware Manual
9850 DDS W_CLK
9850 DDS FQ_UD
9850 DDS Reset
8254 Channel 0 Period Register
8254 Channel 1 Period Register
8254 Channel 2 Period Register
8254 Control Register
I/O Module Strobe 0
I/O Module Strobe 1
I/O Module Strobe 2
I/O Module Strobe 3
I/O Module Strobe 4
I/O Module Strobe 5
I/O Module Strobe 6
I/O Module Strobe 7
Multiplexer Unit 0 Control
Multiplexer Unit 1 Control
External Local SRAM
External Global SRAM
PCI Bus Interface Registers
Figure 2: M44 Memory Map
DDS_W_CLK
DDS_FQ_UD
DDS_RESET
PIT_A
PIT_B
PIT_C
PIT_D
IOMOD0
IOMOD1
IOMOD2
IOMOD3
IOMOD4
IOMOD5
IOMOD6
IOMOD7
MUX0
MUX1
V292_REG
0x500000
0x540000
0x580000
0x600000
0x600001
0x600002
0x600003
0x700000
0x740000
0x780000
0x7C0000
0x800000
0x840000
0x880000
0x8c0000
0x900000
0x940000
0x7FE00000
0x80000000
0x80800000
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
“
Local Strobe 1
Global Strobe 0
Global Strobe 1
M44 Hardware Manual - 3
1.1 M44 Hardware Initialization Requirements
The M44 design requires the following values to be written to its hardware control registers in order to
provide error-free access to on-board hardware:
Register
Address
Value
GMICR
LMICR
0x100000
0x100004
0x36A50000
0x3DA50040
Figure 3: OMNIBUS Control Register Initialization Values
These values are initialized automatically by C programs compiled under the M44 Developer’s Package
software libraries. Be sure to include initialization of these values whenever software is developed outside
the Developer’s Package or when a JTAG hardware assisted debugger is employed for code downloading to
the M44 (i.e. when using Code Composer or any other JTAG debugger package).
Also note that the M44 uses on-board logic to control processor bootstrapping from the global bus SRAM.
This logic controls the IIOF[3..0] processor interrupt input pins and effectively muxes these inputs between
the bootloading function and external interrupt inputs. The logic’s multiplexer is reset by an IACK pulse
from the processor, normally caused by the completion of the ‘C44’s ROM bootloader program. After a
processor board level reset and until this pulse is received by the logic, external interrupts will be gated
away from the processor. Normal application COFF loading under control of the Developer’s Package host
libraries will utilize the ‘C44 bootloader and initialize interrupts correctly. All code loaded outside of the
Developer’s Package (i.e. via a JTAG debugger) will need to execute an IACK instruction to external
memory in order to initialize the external bootload logic and allow the processor to receive external
interrupts.
4 - M44 Hardware Manual
1.2 PCI Bus Interface
The M44 implements a high speed PCI bus master/slave interface for use in transferring data to and from
host computer applications and other hardware installed in the host system. The card is able to directly
access any memory address in the host system, and once initialized can automatically transfer data to and
from the global SRAM memory pool without ‘C44 CPU intervention. The card also responds to bus master
accesses as a bus slave, allowing other bus masters to write or read data directly to/from global SRAM
without intervention from either the ‘C44 or host CPU.
Also included in the PCI interface hardware is a mailbox register set which allows for straightforward
transfer of 32-bit data one word at a time. The mailboxes are mapped in the I/O space on the host PCI bus,
along with the rest of the PCI bus interface control register set.
1.2.1 PCI Bus Interface Register Set
The register set of the PCI bus interface V292PBC device is mapped into the ‘C44’s global memory area
starting at address 0x80800000. This register set allows the ‘C44 to control the PCI bus interface, including
such functions as bus master transfers, slave memory mapping, and the mailbox register set. The PCI bus
configuration space registers also reside within this set. The register set is initialized at system startup from
a serial EEPROM device, allowing the various PCI configuration registers to be set up with required values
prior to the system BIOS’ initialization of the PCI bus. After system plug and play initialization, the
register set is mapped into a 128 byte region of I/O space on the PCI bus, allowing the registers to be
accessed by the host’s operating system or application software.
For a complete listing of available registers and their functions, please see the V292PBC User’s Guide in
the appendices.
1.2.2 Introduction to PCI Bus Mastering
Bus mastering allows the M44 to take direct control of the PCI bus and perform accesses to other hardware
residing on the bus, either directly or through bridge hardware. This feature allows the ‘C44 processor to
program reads and writes directly into the host CPU memory space, thus transferring data into and out of
host memory without taking precious host CPU bandwidth away from other system management and
application tasks. Via this interface, the M44 can also access other PCI slave hardware adapters.
Bus slave access allows either the system host or other bus masters direct access to the M44’s global SRAM
pool. This allows other processors in the system the ability to transfer data to and from the ‘C44’s memory
space without requiring the ‘C44 to be involved in the transaction. This can save processor bandwidth on
the ‘C44 side, allowing it to spend more time processing local data or handling I/O transactions on the I/O
expansion bus.
M44 Hardware Manual - 5
1.2.3 Bus Master Transfer Setup and Termination
Bus master transfer setup is very similar to the initialization of most DMA controllers. The PCI bus
interface requires three variables to be programmed prior to starting a bus master transfer: the PCI memory
address, the offset into ‘C44 global memory, and the count of 32-bit words to be transferred. The direction
and start bits in the bus master control register are initialized last, causing the DMA controller built in to the
interface to begin the transfer. Once the transfer is initiated, the ‘C44 may continue on with other tasks
while the DMA controller processes the transaction.
Although the ‘C44 may poll for completion of the transfer, the bus interface is typically programmed to
interrupt the ‘C44 upon transfer termination. Interrupt-driven bus master transactions allow the processor to
proceed with other tasks while the bus interface hardware completes the transfer transparently.
1.2.3.1 Host DRAM Page Locking
It is generally necessary under most modern host operating systems to perform a page locking and
devirtualization call in order to guarantee the availability of host RAM at a specified physical address. This
is necessary because most currently available host operating systems use virtual memory techniques to page
data between physical RAM and the host disk so as to increase the effective memory size of the system.
Since the M44 bus master feature requires a known host RAM area to which or from which it can transfer
data, and since this data transfer can occur asynchronously from host operating system activities including
virtual memory swaps, the operating system must be restricted from moving data in the space to be used by
the bus master mechanism.
Note that this requirement also applies to other adapter cards used as slaves to an M44 bus master transfer,
but in a slightly different way. The host operating system or applications running under the operating
system must be aware of the bus master transfers being performed to the slave adapter so as to avoid
conflicts. For example, if a bus master write were issued to a disk controller which is simultaneously being
managed by a host operating system device driver, the two functions would likely collide if the device
driver was not made aware of the impending bus master transfer.
The M44 Developer’s Package provides a device driver which automatically locks a portion of host
physical DRAM to provide a data transfer buffer.
1.2.4 Bus Slave Setup
The M44 PCI bus interface maps the global SRAM memory into PCI memory space to allow other PCI bus
masters access to this memory pool. This allows either the system host CPU or another bus mastering card
to deliver data or program information to the M44’s ‘C44 processor without requiring processing time from
the M44 to complete the transfer. The memory is directly mapped into a two MByte region in host
memory (usually above the top of installed host DRAM), allocated during plug and play negotiations when
the host system is first booted. The size is always allocated to two MBytes because the maximum global
SRAM size on the M44 is 512Kwords (512Kx32, or two Mbytes). If the installed global SRAM memory is
smaller than 512 KBytes, the memory image will alias through the allocated two MByte address space (i.e.
multiple copies appear through the allocated area).
6 - M44 Hardware Manual
No explicit software setup other than the basic board initialization (see above) is required in order to use the
global SRAM as a PCI slave memory space.
Note: the M44 PCI bus interface does not support bus master transfers simultaneous with slave global
SRAM accesses. Before attempting to access global SRAM, host software should check for an active bus
master transfer via the V292 register set.
1.2.5 Mailbox Access
The PCI bus interface mailboxes include four 32-bit wide registers which may be used to transfer individual
words between the M44 and host processors. Interrupts may be enabled on writes and reads of these
registers, and there is no handshaking built in to the interface (i.e. either processor can access any mailbox
at any time). The mailboxes are typically used for slow rate data transfer (as in the stdio library provided
with the Developer’s Package) or command passing schemes.
1.2.6 PCI Bus Software support in Developer’s Package
The M44 Developer’s Package includes libraries to drive both bus master transfers and mailbox accesses.
The bus master support includes routines which set up and initiate bus master reads and writes from data
areas in global SRAM. Routines are provided to help manage use of the mailboxes in a data passing
scheme. The C language stdio library in the Developer’s Package also makes use of the mailbox system as
its primary data passing method.
M44 Hardware Manual - 7
1.3 OMNIBUS I/O
The OMNIBUS I/O provides a modular, high-speed expansion area which is directly tied to the ‘C44 local
bus and which is ideally suited for I/O hardware expansion. Direct memory-mapped accesses as fast as one
wait state allow the ‘C44 to transfer data to and from I/O bus peripherals constructed as plug-in modules
which can be mixed and matched to suit the particular user’s functional requirements.
Implemented as two independent I/O module slots, the M44’s I/O bus is accessed as a memory-mapped
peripheral with the M44 providing four decoded chip select signals per slot. The following figure gives the
memory map for the M44’s I/O bus, and shows the decode signal to I/O slot mapping.
Function
C Language Mnemonic
Address
Module Slot
IOMOD0
IOMOD1
IOMOD2
IOMOD3
IOMOD4
IOMOD5
IOMOD6
IOMOD7
0x700000
0x740000
0x780000
0x7C0000
0x800000
0x840000
0x880000
0x8c0000
0
0
0
0
1
1
1
1
I/O Module Strobe 0
I/O Module Strobe 1
I/O Module Strobe 2
I/O Module Strobe 3
I/O Module Strobe 4
I/O Module Strobe 5
I/O Module Strobe 6
I/O Module Strobe 7
Figure 4: OMNIBUS I/O Memory Mapping
I/O module slot 0 is in the upper position (towards the top edge of the card), while slot 1 is in the lower
position (towards the PCI bus edge connector).
Each I/O module slot provides a full 32-bit wide data bus connection to the ‘C44 processor’s local bus, with
12 bits of low-order address signals for additional decoding beyond the four chip select signals available
per slot. Each module also connects to a ‘C44 communication port (port 2 for I/O module 0, port 5 for I/O
module 1) to allow comm port driven I/O. Bus reset, RDY, R/W, and processor clock signals are available,
as are power connections for digital 5V and analog +-5V and +-15V. Timebase connections include timer
channels from both the 8254 counter-timer chip and the 9850 direct-digital synthesizer.
Each I/O module site has a 50 pin undedicated connector (JP5 on site 0, JP9 on site 1), for use in providing
external I/O to/from a module installed in the site. The module’s I/O connector is in turn pinned out to a 50
pin .100” square double row header (JP6 on site 0, JP10 on site 1) on the board and a 15 pin DB style
connector on the end bracket. The DB15 connector provides external access to the highest 15 pins of the
I/O connections.
Connector pinouts for the module sites are provided in the appendices. Individual pin functions are noted in
the tables, and in general the I/O Bus pinout represents a direct connection to the ‘C44 local bus. The
exceptions to this rule are noted below, along with custom module design recommendations.
1.3.1 I/O Bus Accesses and Hardware RDY Generation
The ‘C44 processor’s local bus control register is initialized for hardware wait states in the strobe 0 region
(see M44 Hardware Initialization Requirements, above), which means that the individual I/O modules are
responsible for generating an active low RDY pulse to the ‘C44 processor to terminate bus accesses to their
respective memory mapped areas. This allows each module to individually determine timing for bus
accesses to the memory space in which it is installed, which in turn allows accesses as short as one wait
8 - M44 Hardware Manual
state (and potentially as long as can be generated by the module). The ‘C44 local bus RDY0 pin is shared
across both modules as well as the on-board wait-state generation logic (which is responsible for providing
RDY pulses for on-board peripherals mapped into local strobe 0 space), and is generated by the hardware as
a wired-OR open collector signal (the signal is pulled up to system 5V with a 1Kohm resistor).
The following code example, written in the AMD MACHXL design language, shows how to provide a
logic-based wait state generator for customer-designed modules. The wait state generator is implemented as
a state machine clocked from the processor H1 clock signal (this code is used in the MACH210 CPLD
device on the M44DIG module). The design generates two different levels of wait state length: one wait
state cycles (for the control registers, digital I/O, and ID ROM accesses) and five wait state cycles (for all
UART accesses).
PIN ? H1 COMB
PIN ? /IOMOD0 COMB
PIN ? /IOMOD1 COMB
PIN ? /IOMOD2 COMB
PIN ? /IOMOD3 COMB
PIN ? /LRDY0 REG
NODE ? LRDY0_TRST REG
NODE ? Q[2..0] REG
; IO Module bus wait state generator
CASE (LRDY0_STATE)
BEGIN
dwell:
BEGIN
IF(DUMMY_INPUT) THEN
;fake IF to fix MACHXL compile bug
BEGIN
LRDY0_STATE = 7
LRDY0 = VCC
LRDY0_TRST = VCC
END
ELSE
BEGIN
IF(/IOMOD0 * /IOMOD1 * /IOMOD2 * /IOMOD3) THEN ;if no cycle, remain in dwell
state
BEGIN
LRDY0_STATE = dwell
LRDY0 = GND
LRDY0_TRST = GND
END
ELSE
BEGIN
IF(IOMOD0) THEN
;if UART access, execute five wait cycle
BEGIN
LRDY0_STATE = five_wait_start
LRDY0 = GND
LRDY0_TRST = VCC
END
ELSE
BEGIN
IF(IOMOD1 + IOMOD2 + IOMOD3) THEN
;if any other access, one wait state
BEGIN
LRDY0_STATE = one_wait_start
LRDY0 = VCC
LRDY0_TRST = VCC
END
END
END
END
END
M44 Hardware Manual - 9
one_wait_start:
BEGIN
LRDY0_STATE = dwell
LRDY0 = GND
LRDY0_TRST = GND
END
; jump back to DWELL state
; send LRDY0 active low to 'C44
five_wait_start:
BEGIN
LRDY0_STATE = five_wait_dwell_one
LRDY0 = GND
LRDY0_TRST = VCC
END
five_wait_dwell_one:
BEGIN
LRDY0_STATE = five_wait_dwell_two
LRDY0 = GND
LRDY0_TRST = VCC
END
five_wait_dwell_two:
BEGIN
LRDY0_STATE = five_wait_dwell_three
LRDY0 = GND
LRDY0_TRST = VCC
END
five_wait_dwell_three:
BEGIN
LRDY0_STATE = five_wait_dwell_four
LRDY0 = GND
LRDY0_TRST = VCC
END
five_wait_dwell_four:
BEGIN
LRDY0_STATE = five_wait_dwell_five
LRDY0 = VCC
LRDY0_TRST = VCC
END
five_wait_dwell_five:
BEGIN
LRDY0_STATE = dwell
LRDY0 = GND
LRDY0_TRST = GND
END
;jump back to dwell state
;send LRDY0 active to 'C44
END
Q[2..0].CLKF = /H1
Q[2..0].RSTF = RESET
LRDY0.CLKF = /H1
LRDY0.RSTF = RESET
LRDY0.TRST = LRDY0_TRST
LRDY0_TRST.CLKF = /H1
LRDY0_TRST.RSTF = RESET
Figure 5: I/O Module Wait State Generator Example
10 - M44 Hardware Manual
1.3.2 I/O Bus Power
The I/O bus provides five separate power supplies for use by I/O modules, along with two separate ground
return connections. The following table lists the supplies and their power ratings. A separate digital 5V
supply is provided along with separate digital grounds to minimize the digital noise present on the analog
power supplies.
Pin Name
Voltage
Current Rating (max)
DVCC
+12
-12
AVCC
-AVCC
+AV
-AV
5V (digital)
12V
-12V
5V (analog)
-5V
+15V
-15V
(System dependent)
(System dependent)
(System dependent)
500 mA
500 mA
330 mA
330 mA
Figure 6: I/O Bus Power Ratings
Please note that the AGND and DGND busses are separated on the M44 and for proper ground referencing
they must be tied together on modules which use the analog power supplies (any supply other than digital
5V). Innovative Integration recommends that a ferrite bead (Panasonic EXC-ELSA35V or equivalent) be
used on custom modules to connect the two ground busses in order to prevent high frequency digital noise
on the DGND bus from polluting the clean AGND return.
1.3.3 I/O Bus Mechanical Specifications
The following figure gives mechanical specifications for board size and connector placement and
orientation for I/O bus modules.
M44 Hardware Manual - 11
Figure 7: OMNIBUS I/O Mechanical Specification
1.3.4 I/O Bus Timing
OMNIBUS I/O timing is identical to that of the card’s ‘C44 processor with the following exceptions:
1) IOMODx* signals have a propagation delay of approximately 7-10 ns max through onboard logic,
which causes these signals to trail the ‘C44 LSTRB0* timing by the same amount of time.
2) All other processor bus signals have a small propagation time added to them by connector delays
(approximately 2-3 ns). This slightly affects signal timing to and from the ‘C44 and should be
taken into account when designing I/O module glue logic.
For more information on the ‘C44’s local bus timing specification, see the TMS320C4x User’s Guide.
1.3.5 I/O Bus Module Design Guidelines
The following guidelines should be observed when designing a custom module for the OMNIBUS I/O:
1) Keep all bus line loading to below four CMOS loads per module. If more than four devices are
present on data or address bus lines, buffer the lines with fast (FCT or ABT family) logic.
12 - M44 Hardware Manual
2) Do not decode the IOMODx* strobes further using lower order address lines unless address and
data latching is included for write accesses to the card. The IOMODx* signals already represent
one propagation delay through a set of decode logic on the card (max 7-10 ns), and additional
decoding may drive the resultant strobe trailing edge too far past the close of valid data and
address information from the ‘C44. This can result in failed or intermittent write operations.
3) Keep bus signal trace lengths to the absolute minimum. Interface logic should be placed as close
as possible to the bus connector end of the module.
4) Treat the processor H1 clock signal with special care. Termination may be required to maintain
signal integrity.
5) Since the external DB15 connectors allow the highest 15 pins (pins 35-50) of the Bus’ I/O
connector to propagate to the outside of the system chassis without special internal chassis cabling,
custom module designs should always use these pins for I/O whenever possible.
M44 Hardware Manual - 13
1.4 Timers
The M44 provides a total of six channels of independent timebase generation on board for use in timing
data acquisition, servo controls, real-time counters, and other applications. The functionality is divided into
three devices: two channels of 32-bit timing on the ‘C44 processor, three channels of 16-bit timing on the
8254 counter-timer chip, and a 32-bit direct digital synthesizer (DDS) channel in the AD9850 device. This
section discusses the AD9850 and 8254 devices: for more information on the on-chip timers, see the
TMS320C4x User’s Guide.
1.4.1 AD9850 Direct Digital Synthesizer
The AD9850 direct digital synthesizer (DDS) is a precision programmable clock source which is capable of
generating frequencies in the range of 0 to 30 MHz with a resolution of approximately 0.014 Hz/step (the
exact number is calculated using the equation, Step = Inputclk / 2^32). Unlike a digital counter-timer chip
which uses a digital counter to divide down a high input clock rate, the DDS uses phase-locked-loop
synthesize technology to tune a sine wave oscillator based on an 32-bit digital word. This method realizes a
linear output frequency over input range rather than the nonlinear one associated with counter-timer chips,
whose resolution drops dramatically as the period register used to program them falls. As an example take
the following table, which shows frequency outputs for each of the two types of timebases over input codes:
Input Code
AD9850 Output
Frequency (60 MHz
input clock) (Hz)
AD9850
Frequency Step
(Hz)
8254 Output
Frequency (10 MHz
input clock) (Hz)
8254 Frequency
Step (Hz)
1
2
3
4
5
6
7
8
9
...
65533
65534
65535
0.014
0.028
0.042
0.056
0.070
0.084
0.098
0.112
0.126
0.014
0.014
0.014
0.014
0.014
0.014
0.014
0.014
0.014
5M
2.5M
1.25M
625k
312k
156k
78k
39k
19k
2.5M
1.25M
625k
312k
156k
78k
39k
19k
9k
915.485
915.499
915.513
0.014
0.014
76.2974
76.2962
76.2951
0.0012
0.0011
Figure 8: DDS versus Counter-timer
The counter-timer device has a nonlinear frequency step change over its input code range, as opposed to the
DDS device which maintains a linear frequency step for each input code increment. This results in the
counter-timer’s increases resolution at the high end of its input code range, with a correspondingly low
resolution at the low end. The AD9850 timebase should be selected for use when a fairly fast but very
precise and accurate clock is required by the application.
The M44 Developer’s Package includes a routine (timer()) which makes it easy to set the AD9850’s
output frequency (see the M44 Developer’s Package Software Manual for details).
14 - M44 Hardware Manual
1.4.2 8254 Counter-timer
The 8254 counter-timer provides three 16-bit counter timer channels which may be used as timebase
generators or as external event counters, with the capability to gate counting as needed with external logic.
When used as timebases, 8254 channels zero and one have two possible input signals while 8254 channel
two has a single (external) source. Channels zero and one may be driven by either the on-board 1 MHz
crystal oscillator or the output of the AD9850 DDS circuit, depending on jumper settings (see the table
below for jumper setting information). Channel two is always driven by the 8254_CLK2 signal on the
digital I/O connector.
Channel
Jumper Setting
Input Source
0
JP22 pins 1-2
JP22 pins 2-3
JP23 pins 1-2
JP23 pins 2-3
DDS output
1 MHz oscillator
DDS output
1 MHz oscillator
1
Figure 9: 8254 Timer Clock Sources
Gating of these sources may be accomplished by the GATE[0..2] pins on the digital I/O connector. Pulling
these lines low will stop counting on the corresponding channel. The lines are pulled high by 10K ohm
resistors on the board.
M44 Hardware Manual - 15
1.5 Communication Ports
The M44 provides two external communication port connectors which allow the processor to exchange data
quickly and easily with other ‘C4x-based processor boards. The port connectors are driven (with the
exception of the REQ and ACK lines), allowing long lines to be used between boards. The connector
pinouts used are compatible with Innovative Integration’s other ‘C4x processor boards.
The following diagram shows the comm port usage on the M44. Two ports (ports one and four) are driven
to the external comm port connectors while the other two available ports are connected directly (undriven)
to the I/O bus connectors.
‘C44 Processor
JP14
Comm 2
I/O Module
Slot 0
Comm 5
I/O Module
Slot 1
Comm 1
Comm 4
Drivers/Logic
Drivers/Logic
JP1
Connector
JP2
Connector
JP15
Figure 10: M44 Communication Port Usage
All four comm ports are capable of bidirectional data transfer, but bidirectional usage is not recommended
on the external comm ports with cables longer than approximately two feet. At this distance, token transfer
timing over the unbuffered REQ and ACK lines becomes unreliable. If cables of this length or longer are to
be used, the drivers may be forced into unidirectional mode through the use of jumpers JP14 and JP15,
according to the following table.
Jumper Number
Position
JP15
Off
1-2
2-3
Off
1-2
2-3
JP14
Function
‘C44 comm 4 is input only
‘C44 comm 4 is bidirectional
Reserved
Reserved
‘C44 comm 1 is bidirectional
‘C44 comm 1 is output only
Figure 11: Communication Port Driver Settings
Caution: when the board is jumpered for unidirectional transfer, do not attempt to perform bidirectional
transfers. Doing so can cause drive contention between the ‘C44 processor and the comm port drivers,
potentially causing significant damage to the M44 board. For example, if comm port 4 is jumpered for
unidirectional functionality (input only), do not perform software writes to the comm port’s data FIFO.
Caution: performing a JTAG scan path DSP reset can also cause hardware conflicts when running comm
port based software. Since a JTAG reset initializes the on-chip peripherals as well as the CPU, the comm
16 - M44 Hardware Manual
ports will revert to their normal power-on reset directions. If the M44’s external logic is set to an opposing
direction due to comm port software operation, the drivers will conflict with the ‘C44’s comm port pin
drive, potentially damaging the board. A board level hardware reset will simultaneously reset the external
logic and the ‘C44 device, thus avoiding the problem. A utility for generating a hardware reset
(CARD.EXE) is included with the Innovative Peripheral Libraries.
M44 Hardware Manual - 17
1.6 Digital I/O
The M44 includes 32 bits of software programmable digital I/O for use in controlling digital instruments or
acquiring digital inputs. The digital I/O is mapped into local strobe zero at five addresses: one used to
read/write the digital I./O data, and four more for controlling the direction of the four bytes of digital I/O
The following table lists the addresses and their functions.
Function
Digital I/O Data Register
Digital I/O Byte 0 Direction Control
Digital I/O Byte 1 Direction Control
Digital I/O Byte 2 Direction Control
Digital I/O Byte 3 Direction Control
C Language Mnemonic
Address
DIGIO
DIGDIR0
DIGDIR1
DIGDIR2
DIGDIR3
0x300000
0x400000
0x440000
0x480000
0x4C0000
Figure 12: Digital I/O Control Registers
The direction control registers provide for software control of the drive direction of the port. Each byte is
individually controllable by writing a zero (to select output) or a one (to select input) to the respective
direction control register.
The data register allows software to directly read data from port pins programmed for input, or write data to
pins programmed for output.
Since the digital I/O port is a latching port (meaning that inputs are clocked in on the edge of a strobe signal
and held for the processor to read), there is a jumper selection which allows the user to pick the strobe
source. Jumper JP4 allows the user to select either software read clocking (pins 2-3 shorted) or external
hardware clocking (pins 1-2 shorted). If software clocking is selected, then the port latches programmed for
input will clock in the digital data present on the external pins at the beginning of a read cycle executed on
the port (30-50 ns before the data is returned to the processor, depending on processor clock speed). If
external clocking is selected, then the port will latch data on the falling edge of the TTL signal
EXT_DIG_RD_CLK* on the digital I/O connector. The data will be held for the processor to read until the
next low-going edge of the EXT_DIG_RD_CLK* signal.
The ‘FCT16952 devices used to implement the digital I/O port are capable of sourcing 32 mA and sinking
64 mA per pin.
18 - M44 Hardware Manual
1.6.1 Digital I/O Timing
The following diagram gives timing information for the digital I/O port when used in external readback
clock mode (see above for details). This data is derived from device specifications and is not factory tested.
External
Readback Clock
tSU
Input data
tH
Data Valid
Figure 13: Digital I/O Port Timing
Parameter
min (ns)
tSU
tH
0
10
Figure 14: Digital I/O Port Timing Parameters
M44 Hardware Manual - 19
1.7 Interrupts
The M44 provides a jumper header (JP13) which allows the user to connect any of several different
interrupt sources to the ‘C44 processor’s external interrupt inputs. Interrupts may be triggered by any of the
following sources:
1)
2)
3)
4)
5)
6)
9850 DDS timebase
8254 timebase channels 0-2
External analog triggers 0 and 1
External interrupt inputs 0 and 1
External digital I/O strobe
PCI-to-’C44 interrupt
The following tables list the possible interrupt input to source connections. Note that there are separate
tables for different revision cards.
Processor
Interrupt Input
Source Signal
JP13 Jumper
Position
IIOF0
9850 Timebase
8254 Channel 0 Timebase
External Trigger 0
External Interrupt 0
External Trigger 0
External Interrupt 0
External Interrupt 3
8254 Channel 1 Timebase
External Interrupt 3
8254 Channel 1 Timebase
External Digital I/O Strobe
External Interrupt 1
PCI Interrupt
8254 Channel 2 Timebase
External Trigger 1
External Interrupt 2
1-3
2-4
3-5
4-6
5-7
6-8
7-9
8-10
9-11
10-12
11-13
12-14
15-17
16-18
17-19
18-20
IIOF1
IIOF2
IIOF3
Figure 15: External Processor Interrupt Selection, Revisions C and D
20 - M44 Hardware Manual
Processor
Interrupt Input
Source Signal
JP13 Jumper
Position
IIOF0
9850 Timebase
8254 Channel 0 Timebase
External Trigger 0
External Interrupt 0
External Trigger 0
External Interrupt 0
External Interrupt 3
8254 Channel 1 Timebase
8254 Channel 1 Timebase
External Interrupt 1
8254 Channel 2 Timebase
External Interrupt 2
External Interrupt 3
External Digital I/O Strobe
PCI Interrupt
External Trigger 1
1-3
2-4
3-5
4-6
5-7
6-8
7-9
8-10
10-12
12-14
16-18
18-20
9-11
11-13
15-17
17-19
IIOF1
IIOF2
IIOF3
Figure 16: External Processor Interrupt Selection, Revision E
Please note that the interrupt signals themselves are always TTL push-pull falling edge sensitive. In order
to avoid contention between interrupt sources, only one signal may drive a particular interrupt input at one
time.
1.8 Multiplexer Control
The M44 provides two external multiplexer control bus connectors for use with the TERM external
multiplexer board. Control for the multiplexer connectors is provided at the MUX0 and MUX1 addresses
(see memory map above), with the memory-mapped functions described in the following table.
M44TERM Module
0
1
Function
Mux #0 Channel Select
Mux #1 Channel Select
Mux #2 Channel Select
Mux #3 Channel Select
All Muxes Channel Select
Sample Trigger
Reset
Mux #0 Channel Select
Mux #1 Channel Select
Mux #2 Channel Select
Mux #3 Channel Select
All Muxes Channel Select
Sample Trigger
Reset
C Language Mnemonic
Address
MUX0
MUX0+1
MUX0+2
MUX0+3
MUX0+4
MUX0+5
MUX0+7
MUX1
MUX1+1
MUX1+2
MUX1+3
MUX1+4
MUX1+5
MUX1+7
0x900000
0x900001
0x900002
0x900003
0x900004
0x900005
0x900007
0x940000
0x940001
0x940002
0x940003
0x940004
0x940005
0x940007
Figure 17: TERM Function Memory Map
The control connectors (JP17 for TERM module #0 and JP18 for TERM module #1) select multiplexer
channel numbers and trigger analog sample/hold operations. The first four addresses from the start of each
mux control address map allow the selection of incoming signals on each multiplexer device on the TERM.
M44 Hardware Manual - 21
The fifth address location allows the simultaneous selection of the same channel on all multiplexer devices.
The remaining two addresses trigger analog samples on the sample/hold devices and perform a global reset
of the TERM hardware.
22 - M44 Hardware Manual
1.9 JTAG Test Bus
The M44 implements a JTAG 1149.1-compatible scan path loop through the onboard ‘C44. When
connecting a JTAG controller card cable (from an Innovative Integration debugger card, Texas Instruments
XDS-510, or other vendor’s JTAG hardware), the JP19 connector is used.
M44 Hardware Manual - 23
2. Appendices
24 - M44 Hardware Manual
2.1 Connector pinouts
2.1.1 JP5, JP6, JP9, JP10, P1, P2 - I/O Module I/O Connectors
Connector types: JP5, JP9: AMP .05 Subminiature D male
JP6, JP10: .100” header (M44), 50 pin female SCSI style (cM44)
P1, P2: DB15 male (M44 only)
Number of pins: JP5, JP9: 50
JP6, JP10: 50
P1, P2: 15
Mating connector: JP5, JP9: AMP 173279-3
JP6, JP10: AMP 1-746285-0 (M44), AMP 749621-5 (cM44)
P1, P2: AMP 747303-3
The following table shows the interconnections between the JP5 (I/O module slot 0) and JP9 (I/O module
slot 1) module I/O connectors and their respective external I/O connectors, JP6 and P1 (for I/O module 0)
and JP10 and P2 (for I/O module 1). Please note that the P1 and P2 pinouts only apply to the M44 board.
JP5, JP9 Pin
Numbers
JP6, JP10 Pin
Numbers
P1, P2 Pin
Numbers
1-35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1-35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
Figure 18: I/O Module Connector Pinouts
M44 Hardware Manual - 25
The following diagram gives the physical pin locations for JP6 and JP10 connectors on the cM44 board.
Please note that these physical pin positions do not use the same numbering scheme as standard SCSI 50 pin
connectors.
pin 26
pin 27
pin 1
pin 2
pin 49
pin 50
pin 24
pin 25
Not to scale. Front view of JP6/JP10 connector with
upper edge of the cM44 towards the top of the drawing.
26 - M44 Hardware Manual
2.1.2 JP24-JP27 - I/O Module ‘C44 Bus Connectors
Connector types: AMP .05 Subminiature D male
Number of pins: 50
Mating connector: AMP 173279-3
The following table gives the pin numbers and functions for the JP24 (I/O slot 0) and JP26 (I/O slot 1)
connectors. The functions for JP26 are identical to those of JP24, except where noted.
Pin Number
JP24 Function
1, 19
2, 20
3-18
21,43,40,45,3
9,26,27
28
29
30
31
32
33
34
35-38
Digital +5V
Digital ground
Data bus 0-15
Address bus 0-6
25
23
41, 42
22, 24
44, 46
47, 49
48, 50
Reset (active low)
External interrupt 0
Bus ready (active low)
Processor H1 clock
8254 timebase channel 0
R/W*
9850 timebase
IOMOD0-3 decoded selects
(active low)
-12V
+12V
Analog ground
Analog -15V
Analog +15V
Analog +5V
Analog -5V
Figure 19: I/O Module Bus Connectors
JP26 Function
Direction
(from M44)
O, power
O, power
I/O
O
External interrupt 2
IOMOD4-7 decoded selects
(active low)
O
I
I (open-collector)
O
O
O
O
O
O, power
O, power
O, power
O, power
O, power
O, power
O, power
M44 Hardware Manual - 27
The following table gives the pin numbers and functions for the JP25 (I/O slot 0) and JP27 (I/O slot 1)
connectors. The functions for JP27 are identical to those of JP25, except where noted.
Pin Number
JP25 Function
1, 3-6
2, 19, 20, 49,
50
7
8
9
10
11-18
21
22
23, 25
24,26,27,28,3
0,31, 32
29
33-48
Address bus 7-11
Digital ground
JP27 Function
O
O, power
Comm port 2 REQ
Comm port 2 ACK
Comm port 2 STROBE
Comm port 2 RDY
Comm port 2 data 0-7
8254 timebase channel 1
External trigger 0
Optional Analog +12V
Reserved
Comm port 5 REQ
Comm port 5 ACK
Comm port 5 STROBE
Comm port 5 RDY
Comm port 5 data 0-7
External interrupt 1
Data bus 16-31
External interrupt 3
Figure 20: I/O Module Bus Connectors
Direction
(from M44)
External trigger 1
I/O
I/O
I/O
I/O
I/O
O
O
Power
NA
I
I/O
28 - M44 Hardware Manual
2.1.3 JP1, JP2 - Processor Communication Port Headers
Connector type: .100” header
Number of pins: 26
Mating connector: AMP 746286-6
JP1: Comm Port 1
JP2: Comm Port 4
Pin Number(s)
Pin Name(s)
Pin Direction(s)
Pin Function(s)
1
3
5
7
9, 11, 13, 15, 17, 19,
21, 23
2,4,6,8,10,12,14,16,1
8,20,22,24
25, 26
CREQ
CACK
CSTRB
CRDY
CD0-CD7
I/O
I/O
I/O
I/O
I/O
Token request
Token acknowledge
Data strobe
Data ready
Data lines
DGND
power
Digital ground
NC
-
-
Figure 21: JP1, JP2 Pin Description
M44 Hardware Manual - 29
2.1.4 JP3 – Digital I/O Connector
Connector types: 50 pin header
Number of pins: 50
Mating connector:
The following table gives the pin numbers and functions for the JP3 connector.
Pin Number
JP3 Function
Direction (from
M44)
1-32
33
Digital I/O bit 0..31
External Trigger 0 Input (active
low)
8254 Channel 2 Clock Input
External Trigger 1 Input (active
low)
DDS Clock
8254 Gate 0,1,2 (active low)
8254 Channel 0, 1, 2
NC
External Interrupt Input 0,1,2,3
(active low)
External Dig I/O Readback
Clock (active low)
Digital +5V
Digital Ground
I/O
I
34
35
36
37,39,41
38,40,42
43
44,46,48,50
45
47
49
Figure 22: Digital I/O Connector
I
I
O
I
O
I
I
Power
Power
30 - M44 Hardware Manual
2.2 Factory Default Jumper Settings
M44 Hardware Manual - 31
2.3 Device Data Sheets
32 - M44 Hardware Manual