Quiz 4
ECE 693-002 Fall 2003
Name:
Student Number:
Given: Assume you have an embedded system designed around a system bus. The system includes one
processor “unit”, one memory “unit”, and one peripheral “unit”. The system bus has 32-bit data width and
32-bit addressing. The peripheral collects 32-bit data from the outside world and needs to transfer this data
from its internal data register, Dreg, located at address 0x2000 to location 0x3000 in memory (on the
memory “unit”).
1) Assume standard I/O is used, the ISR is located at address 0x100, a vector address table is used, and the
peripheral is assigned interrupt number 3. Assume any initialization of system hardware has been
completed already. Draw a block diagram of the system and create a list of steps associated with the
operation of this system in order to service the peripheral. These steps should create an ordered list of
actions taken by the system to service the interrupts from the peripheral. All activities of the system should
be included in this list including bus control lines asserted, address bus and data bus lines asserted,
movements of data, as well as the activities performed by the processor.
2) Assume the system described is Problem #1 is altered to support memory-mapped I/O using a DMA
controller. Assume any initialization of system hardware has been completed already. Draw a block
diagram of the system and create a list of steps associated with the operation of this system in order to
service the peripheral. These steps should create an ordered list of actions taken by the system to service
the interrupts from the peripheral. All activities of the system should be included in this list including bus
control lines asserted, address bus and data bus lines asserted, movements of data, as well as the activities
performed by the processor.
Note: You are NOT responsible for creating your own bus protocol for standard read and write bus cycles.
You are welcome to abstract away the details associated with these transfers. However, you must
specifically mention all bus lines (make up the names of these bus lines) needed to support the interrupt
service as well as data and address lines for all transfers, and finally the device that initiates each transfer.
Solution to Problem 1
1) Peripheral receives data from the outside world and asserts INT line to request service from something.
It really doesn’t know which device will service it.
2) The CPU finishes executing its current instruction and checks the INT line, seeing it asserted.
3) The CPU saves the state of the currently executing program and asserts the IACK line.
4) The CPU also initiates a read cycle, reading from the peripheral. The CPU needs the interrupt number
from the peripheral. Assuming this number is stored in some register on the peripheral having address
0x2004, the CPU puts address 0x00002004 on the address bus and sets the M/IO line to 0 indicating that
this address is in the I/O space.
5) The peripheral responds by driving the data bus with the contents of its interrupt number register,
0x00000003 in this case.
6) The CPU reads the interrupt number from the data bus storing it in some local register for temporary
use. The CPU completes the read cycle. The CPU uses this data as an index into the interrupt vector table.
Element 3 of this table contains 0x00000100, the address of the interrupt service routine (ISR). The CPU
jumps to location 0x00000100 and begins executing the ISR. I am assuming that the interrupt vector table
is stored on memory local to the CPU, not requiring a bus transfer to access it.
7) Now, the CPU is executing the ISR. The ISR will contain instructions to move the data from the
peripheral to the memory unit. The first part of this transfer will be to read the data from the peripheral.
So, the CPU initiates a read cycle from the peripheral. The CPU puts address 0x00002000 on the address
bus and sets the M/IO line to 0 to indicate it is reading from an I/O location.
8) The peripheral decodes the address lines and the M/IO line to determine it is the slave of the read
transaction. So, it drives the data bus with the data that is stored in its DREG register. We don’t know
exactly what that data is so I will not explicitly show the data lines.
9) The CPU completes the read cycle by reading the data from the data bus and storing it into a local
register for use within the ISR.
10) The peripheral deasserts the INT line after it’s DREG register is read.
11) The CPU then initiates a write cycle to the memory unit in order to complete the transfer of data from
the peripheral to the memory. The CPU drives the address bus with address 0x00003000, drives the data
bus with the data stored in a local register and originally read from DREG, and sets the M/IO line to 1
indicating it is addressing a location in memory space.
12) The memory unit decodes the address and M/IO lines to determine that it is the slave in the write
transfer. It responds by reading the data bus and storing this info in location 0x3000 on the memory unit.
This data is the data originally moved from the peripheral. The CPU completes the write cycle.
13) The CPU deasserts the IACK line and returns from the ISR back to the foreground program.
Solution to Problem 2
1) Peripheral receives data from the outside world and asserts INT line to request service from someone. It
doesn’t really know which device will service it.
2) The DMA controller (DMAC) detects the INT line is asserted, and it asserts the DREQ line to request
the bus from the CPU.
3) The CPU finishes executing its current instruction and detects that the DREQ line is asserted.
4) The CPU asserts the DACK line and releases control of the system bus (the CPU will no longer be
master of the bus transactions). The CPU continues with the execution of its programs until it requires use
of the system bus. At that point, the CPU must stall waiting to regain control of the system bus.
5) The DMAC detects the DREQ line asserted by the CPU and grabs control of the system bus. The
DMAC also asserts the IACK line which will be used by the peripheral.
6) The DMAC then initiates a read cycle. The DMAC needs to read the data stored in DREG on the
peripheral. The DMAC puts the address 0x00002000 on the address bus.
7) The peripheral decodes the address lines to determine that it is the slave of the read cycle. It then puts
the contents of the DREG register onto the data bus. We don’t know exactly what that data is so I will not
explicitly show the data lines.
8) The DMAC reads the data bus and transfers that data to a local register/buffer and completes the read
cycle.
9) The DMAC then initiates a write cycle to transfer the data to the memory unit. The DMAC puts
0x00003000 on the address bus and the data from its local register/buffer on the data bus. This is the same
data originally read from the peripheral.
10) The memory unit decodes the address lines to determine it is the slave of the write transaction. It reads
the address bus to determine the destination location of the transfer and stores the information from the data
bus into location 0x00003000.
11) The DMAC deasserts the DREQ line and the IACK line, and releases control of the system bus.
12) The CPU deasserts the DACK line and resumes control of the system bus.
13) The peripheral deasserts the INT line.