M.KUMARASAMY COLLEGE OF ENGINEERING,
KARUR.
Department of
Electronics and Communication Engineering
Paper on
VLSI Implementation of 1553 Bus Controller Chip
Submitted by
B.GOWSALYA (3rd year )
Email:
gowsibalu@gmail.com
Abstract— This paper describes the vlsi
implementation of 1553 bus controller chip. This protocol
is based on digital command/response time division
multiplexed data bus for Communication between the
subsystems in a Military aircraft. The communication is
over a pair of wires with different subsystems transmitting
at different points of time in response to commands. The
reliability has proven equally effective on communication
networks in submarines, tanks, target drones, missile and
satellite systems, land-based and launch vehicles, and
space system including the current International Space
Station and Shuttle programs. The hardware used is the
chip called virtex 2B PRO
Keywords- BC, RT, BM, FPGA, MIL-STD-153,FPGA.
became popular not only for aircraft but also land and
sea based systems and also featured in some, nonaircraft related high integrity commercial applications.
After 30 years of its existence it has remained largely
unchanged and unchallenged as the on-board ‘bus’ of
choice for new military systems. Communication is
controlled by the bus controller. we adopt an expensive
foreign 1553B protocol processor in order to design
BCU, the paper introduces a new design method, and
its features includes low cost and with independent
intellectual property rights[1]. 1553IP has the following
advantages. Eliminate Problems Related to Single
Source, Small Footprint, Lower Price and
Flexibility[11].
II.
I. INTRODUCTION
MIL-STD-1553 was first introduced into military
avionics systems in the early 1970s in the USA. It
BUS ARCHITECTURE
There are only three functional modes of terminals
allowed on the data bus: the bus controller, the bus
monitor, and the remote terminal. The 1553 data bus is
a dual-redundant, bidirectional, Manchester II
encoded data bus with a high bit error reliability. All
bus communications are controlled and initiated by a
main
bits of data, and 1 parity check bit. This is the word as it
is transmitted on the bus; 1553 terminals add the sync
and parity before transmission and remove them during
reception[5].
Bus controller [2].The bus controller (BC) is the
terminal that initiates information transfers on the data
bus. It sends commands to the remote terminals which
reply with a response. The bus will support multiple
controllers, but only one may be active at a time. It is
the key part of the data bus system, and the sole control
of information transmission on the bus shall reside with
the bus controller. The bus controller is responsible for
directing the flow of data on the data bus. The bus
controller is the only one allowed to issue commands
onto the data bus.
Fig 2: Word format
Fig 1:Bus Architecture
Bus monitor is the terminal assigned the task of
receiving bus traffic and extracting selected information
to be used at a later time. Bus monitors are frequently
used for instrumentation. A bus monitor is a terminal
that listens to the exchange of information on the data
bus.
Any terminal not operating in either the bus
controller or bus monitor mode is operating in the
remote terminal (RT) mode. Remote terminals are the
largest group of bus components. A remote terminal
must follow the protocol defined by the standard. It can
only respond to commands received from the bus
controller . If a message doesn’t meet the validity
requirements defined, then the remote terminal must
invalidate the message and discard the data .We can
connect up to 31 remote terminals to the bus.
III. WORD FORMATS
There are three types of words: command, status,
and data. A word in MIL-STD-1553 is a sequence of 20
bit times consisting of a 3 bit-time sync wave form, 16
Command words are transmitted only by the bus
controller and always consist of: sync pattern, RT
address field, Transmit/Receive (T/R) field,
sub
address/mode field, word count/mode ,code field ,
parity check bit. Data words always consist of: sync
pattern , data field ,parity check bit. Status words are
transmitted by the RT in response to command
messages from the BC and consist of: sync pattern
(same as for a command word), address of the
responding RT,bit status field, parity check bit.
IV.
INFORMATION
FORMATS
TRANSFER
There are different types of information transfers.
They are bus controller to remote terminal transfers,
remote terminal to bus controller transfers, remote
terminal to remote terminal transfers, mode command
without data word, mode command with data word
(transmit), mode command with data word (receive),
optional broadcast command.
A. Encoding Unit
The type of data encoding used by 1553 is
Manchester II bi phase [10]. A logic one (1) is
transmitted as a bipolar coded signal 1/0 (in other
words, a positive pulse followed by a negative pulse).
A logic zero (0) is a bipolar coded signal 0/1 (i.e., a
negative pulse followed by a positive pulse). A
transition through zero occurs at the midpoint of each
bit, whether the rate is a logic one or a logic zero. The
transmission bit rate on the bus shall be 1.0 megabit per
second.
Fig 3:Information transfer format
In BC to RT transfer the bus controller issues a
receive command and it is followed by the specified
number of data words. The RT , after message
validation, transmit a status word back to the controller.
The command and data words shall be transmitted in a
contiguous fashion with no inter word gaps.
In RT to BC transfer the bus controller shall
issue a transmit command to the RT. The RT shall, after
command word validation, transmit a status word back
to the bus controller, followed by the specified number
of data words. The status and data words shall be
transmitted in a contiguous fashion with no inter word
gaps .In RT to RT transfer the bus controller shall
issue a receive command to RT A followed
contiguously by a transmit command to RT. RT shall,
after command validation, transmit a status word
followed by the specified number of data words.
V.
The first three bit times of all word types is called
the sync field. The command/status sync has a positive
voltage level for the first one and a half bit times, then
transitions to a negative voltage level for the second
one and a half bit times. The data sync is the opposite, a
negative voltage level for the first one and a half bit
times, and then a positive voltage level for the second
one and a half bit times. The encode process as
follows ,make a sync waveform then parallel/serial
conversion ,make a parity bit ,encode the sixteen data
bits and a parity bit.
B. Decoding Unit
Decoding unit includes sync waveform detection of
command and status words, sync waveform detection of
data word and parity checking [1]. With input
frequency of 12MHz, after reset state machine, the
system prepares to detect sync waveform, and when the
bus data state from inactive turned into active, it starts
to detect sync waveform of command words and status
words. The last bit in the word is used as the parity bity
bit which is the parity of 16 preceding bits. It should be
one. If it is not one error message will be sent.
BUS CONTROLLER UNIT
C. Time Detection unit
1553 bus
In this unit , we can calculate the time at which data
is send and the time at which it is received[1]. If it is
above a particular limit it will stop to send and encode,
generate overtime signals for resetting finally.
D. Error Detection unit
In this unit we can find errors that occurs during
transmission and reception[3]. for example the number
of data words send from the controller and that
received at the terminals.
Fig 4:Bus controller block diagram
VI.
CONCLUSION
We have discussed about the vlsi implementation of
1553 bus controller. This reduces the space, increases
the reliability also increases the handling capacity of
emerging complex algorithms, all in a single FPGA. By
implementing MIL-STD-1553 systems within an
FPGA, designers can offload host system processing,
reduce programming requirements, lower the number of
cards in a system and lower costs. This approach is not
only very cost- effective, it also provides the added
computing power.
The design of Bus Controller has been done using
VHDL .The code is written using Xilinx 1SE 10.1 and
its simulation is done through ModelSim XE III 6.4B.
VII. ACKNOWLEDGEMENT
We would like to express our gratitude to the
Almighty God who has been with us during each and
every step of this project. We are graceful to all those
for advising us whenever in need, co-operating with us
and arranging the necessary facilities. We extend our
sincere thanks to ISRO and also to our HOD Prof. K
Rajashekaran, Professor and Head of the Department of
Electronics And Instrumentation Engineering for the
excellent encouragements in course of this work.
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