Chapter 1
Section 1.1
The Metal-Oxide Semiconductor
Field Effect Transistors
An Introduction of MOSFET
In this lecture notes, we shall use metal-oxide semiconductor field effect transistors
(MOSFET) as our conducting devices. We shall not discuss the electronics
properties of these transistors. We merely introduce their functions.
There are two types of MOSFET’s: enhancement type and depletion type.
For each type, there are again two types: N-type and P-type, as shown in Table
1.1-1.
Table 1.1-1 Type of transistors.
Type
Channel
Enhancement
Depletion
N
Enhancement type NMOS Depletion type NMOS
P
Enhancement type PMOS Depletion type PMOS
For each type, we use the symbols shown in Fig. 1.1-1.
1-1
Enhancement Type
NMOS
PMOS
S
D
G
G
D
S
Depletion Type
NMOS
PMOS
D
S
G
G
S
Fig. 1.1-1
D
Enhancement and depletion type transistors.
As shown in Fig. 1.1-1, there are three terminals for each transistor, namely drain
(D), source (S) and gate (G). The terminal with an arrow sign is the source. For all
of these transistors, there is no gate current. In other words, there is only current
going through drain and source as shown in Fig. 1.1-2. The reader should note that
the direction of the current follows the arrow sign of the sources. In NMOS
transistors, the current flows from drain to source while in PMOS transistors, it flows
from source to drain.
1-2
NMOS
PMOS
IDS
ISD
D
S
G
G
S
D
NMOS
PMOS
IDS
ISD
D
S
G
G
S
D
Fig. 1.1-2. Current directions in different type of transistors.
There is actually little difference among the enhancement and depletion
transistors. Throughout of this lecture notes, we shall use enhancement type
transistors. To start with, we shall discuss the NMOS transistors.
As shown in Fig. 1.1-3, there are three important parameters of an NMOS
transistor, namely VGS , VDS and I DS .
It should be reminded here that in an
NMOS transistor, the current flows from drain to source and there is no gate current.
NMOS
IDS
D
G
VDS
S
VGS
Fig. 1.1-3
Voltage and current in a NMOS transistor.
Suppose we have a fixed VGS , the I DS vs VDS curve is as shown in Fig. 1.1-4.
1-3
IDS
For a certain VGS
Region I
Region II
D
G
S
IDS
VDS
Fig. 1.1-4
An I-V curve of an NMOS transistor.
Suppose we apply a voltage between the drain and source terminals. Thus there
is a V DS between these terminals. At the very beginning, as V DS first increases,
I DS increases linearly. After V DS reaches a certain point, I DS stops increasing
and almost remains a constant. Therefore, we say that there are two regions as
indicated in Fig. 1.1-4. Region I is called the triode, or ohmic, region and Region II
is called the saturation, or constant current, region. For Region I, the transistor
almost behaves as a resistor because for a resistor, the current increases linearly with
respect to the voltage across it. That is why this region is also called the ohmic
region. The curve relating I DS with V DS is called an I  V curve.
For different VGS ’s, there are different I DS vs VDS curves, as shown in Fig.
1.1-5. It can be seen that the higher VGS is, the higher I DS is. This phenomenon
will be explained in the next section.
IDS (mA)
Triode
Region
(Ohmic Region)
Saturation Region
D
VGS increasing
G
S
VDS (V)
Fig. 1.1-5
I-V curve of an NMOS transistor for different VGS’s.
1-4
Section 1.2
The Current in the Saturation Region
In this section, we present a formula for the current in the saturation region.
There exists a certain threshold for VGS . This threshold is called Vt . The
transistor is cutoff if VGS  Vt . Throughout of this book, Vt is around 0.5 volts.
If VDS  VGS  Vt , the transistor is in the triode region; otherwise, it is in the
saturation region, as shown in Fig. 1.2-1.
IDS (mA)
VDS  VGS  Vt
Triode
Region
VDS  VGS  Vt
Saturation Region
VGS increasing
D
G
S
VDS (V)
Fig. 1.2-1
The threshold voltage Vt of an NMOS transistor.
In the triode region, obviously, I DS is a function of both VGS and V DS . The
relationship is given by the following formula:
1
W 
2
I DS  K L '  (VGS  Vt VDS  VDS )
2
L
(1.2-1)
where K L ' is a constant and W and L are the width and length of the gate
respectively. The parameter K L ' is given by the integrated circuit manufacturing
process model. At the boundary between the triode and saturation regions, we have
VDS  VGS  Vt
and
VDS
I DS 
1
W
K L '
2
L
(1.2-2)

2
(VGS  Vt )

(1.2-3)
Although Equation (1.2-3) is derived by assuming VDS  VGS  Vt , it is valid for
 VGS  Vt because once VDS  VGS  Vt , the transistor will be in the saturation
1-5
region and I DS will be constant in this region.
I DS will now be independent of V DS and is only a function of VGS . Thus, we
may easily see that Equation (1.2-3) holds if VDS  VGS  Vt . Equation (1.2-3) is
illustrated in Fig. 1.2-2. As will be seen later, VGS will not be too large, except in
some rare cases. Thus, I DS is usually not very large either. Note that a large I DS
will cause a very large power consumption.
IDS
VGS
Vt
Fig. 1.2-2.
The relationship between I DS and VGS .
Fig. 1.2-2 can be quite misleading because it somehow gives the reader the
impression that I DS grows with respect to VGS without any limit. In practice, this
is not the case, as explained in the next section.
1-6
Section 1.3
Transistors
The Behavior of IDS with a Load for NMOS
Consider Fig. 1.3-1 where a load is connected to the drain of the NMOS transistor and
a power supply VDD is connected to the load and a bias voltage VGS is provided at
the gate.
VDD
RL
IDS
D
G
S
VGS
VDS
Fig. 1.3-1. An NMOS transistor with a load.
From the circuit shown in Fig. 1.3-1, we have the following equation:
VDS  VDD  I DS RL .
(1.3-1)
In Equation (1.3-1), there are two variables, namely V DS and I DS . But there
is only one equation. Therefore, we cannot determine I DS from this equation only.
But, we may draw a straight line to illustrate Equation (1.3-1) as in Fig. 1.3-2.
IDS
VDD/RL
VDS=VDD-IDSRL
Load line
VDD
VDS
Fig. 1.3-2. The load line.
What is missing in Equation (1.3-1) is the voltage VGS . Note that current I DS
1-7
is heavily influenced by VGS , as illustrated in Fig. 1.1-5.
Let us combine Fig. 1.1-4
and Fig. 1.3-2 into Fig. 1.3-3.
IDS
VDS=VDD-IDSRL
VDD/RL
For a certain VGS
IDS
VDD
VDS
VDS
Fig. 1.3-3. The determination of I DS and V DS .
Fig. 1.3-3 shows how we can determine the value of I DS by finding the
intersection of the load line and the I-V curve of the transistor . From Fig. 1.3-3, we
know that we can not only determine the value of I DS , but also that of V DS . Note
that the I-V curve is fixed once VGS is given. But the value of RL plays a critical
role now because it determines the slope of the load line. Different RL ’s will give
different load lines and thus different I DS ’s and V DS ’s.
Let us consider the case where VGS changes. There will be a family of I-V
curves.
Case 1:
RL is small.
This case is illustrated in Fig. 1.3-4.
1-8
IDS
I DS 
VDD VDS

RL1 RL1
The highest IDS the transistor can produce.
I1
VGS
increasing
VDD
VDS
VDD
RL1
(b) The load line with a small RL.
IDS
VDS
VDD
D
G
S
VGS
VDS
VGS
(c) VDS versus VGS with a small RL.
IDS
I1
(a) An NMOS transistor circuit
with a small RL.
RL1 small
VGS
Vt
VDD
(d) IDS versus VGS with a small RL.
Fig. 1.3-4. Voltage and current of an NMOS circuit with a small RL .
In this case, as VGS increases, we should note two phenomena: (1) I DS rises
sharply. (2) V DS falls a little. We would like to point out here that V DS is more
important than I DS as V DS is usually the output of the circuit. We shall discuss
this in detail in the next chapter. At present, the reader may simply note that
when RL is small, V DS will not change much as VGS changes.
Case 2: RL is moderate.
The case is illustrated in Fig. 1.3-5.
1-9
IDS
I DS 
VDD VDS

RL 2 RL 2
I
1
VDD
 I2
RL 2
VGS
increasing
VDS
VDD
VDD
(b) The load line with a moderate RL.
RL2
IDS
VDS
VDD
D
G
S
VGS
VDS
VDD
(c) VDS versus VGS with a moderate RL.
VGS
IDS
I1
VDD
 I2
RL 2
RL2 moderate
(a) An NMOS transistor circuit
with a moderate RL.
Vt
VDD
VGS
(d) IDS versus VGS with a moderate RL.
Fig. 1.3-5. Voltage and current of an NMOS circuit with a moderate RL .
We note that the changes of both I DS and V DS are moderate as VGS increases.
In other words, none of them changes sharply.
Case 3: RL is large.
The case is illustrated in Fig. 1.3-6.
1-10
IDS
I DS 
VDD VDS

RL 3 RL 3
I1
VGS increasing
VDD
VDD
 I2
RL 3
RL3
VDS
IDS
VDD
(b) The load line with a large RL.
VDS
D
G
VDD
S
VDS
VGS
VDD
VGS
(c) VDS versus VGS with a large RL.
IDS
(a) An NMOS transistor circuit
with a large RL.
I1
VDD
 I2
RL 3
RL3 large
VGS
Vt
VDD
(d) IDS versus VGS with a large RL.
Fig. 1.3-6. Voltage and current of an NMOS circuit with a large RL .
In this case, we note that I DS rises a little and V DS falls sharply as VGS
increases. Again, we shall emphasize here that the rate of change of V DS is rather
significant. In general, we would like V DS to change drastically.
Fig. 1.3-7 summarizes the three cases.
1-11
VDD
RL
G
IDS
D
S
IDS
RL3 large
VDS
RL2 moderate
RL1 small
I1
VDD
 I2
RL 2
VGS
increasing
VDD
 I3
RL 3
VDS
VDD
For any case, VDS=VDD-IDSRL
VDS
Case 1: RL small (VDS almost constant).
VDD
Case 2: RL moderate(VDS drops slowly).
Case 3: RL large(VDS drops sharply).
VDD
Fig. 1.3-7.
VGS
V DS versus VGS of an NMOS transistor circuit for three different loads.
VGS is called the bias voltage. Its significance will be explained later. V DS is
called the operating point voltage, or simply operating point. Fig. 1.3-8 illustrates
how different operating points are produced. Note that it takes both VGS and RL
to produce an operating point.
From the above discussion, we can see one point: If VGS increases(decreases,
V DS decreases(increases). We may say that the transistor inverts the input.
This is an important point which we will use later.
1-12
IDS
operating points
VDD / RL
VGS increasing
load line
VDS
VDD
Fig. 1.3-8. The operating points.
1-13
Section 1.4
The PMOS Transistors
A typical PMOS transistor is now shown in Fig. 1.4-1.
VSG
G
S
ISD
D
PMOS
Fig. 1.4-1. A PMOS transistor.
For a PMOS transistor, the controlling (biasing) voltage is VSG , as opposed
to VGS in an NMOS transistor. The higher VSG is, the higher I SD will
become. Note that in a PMOS transistor, the current flows from source to drain
which is different from the case in an NMOS transistor.. Fig. 1.4-2 illustrates a
family of I-V curves for PMOS transistors.
ISD
VSG increasing
VSD
Fig. 1.4-2.
I-V curves for a PMOS transistor.
In Fig. 1.4-3, we show the difference between the NMOS circuits and the PMOS
circuits.
1-14
VDD
VDD
RL
G
IDS
S
D
G
D
S
VG
VG
Fig. 1.4-3
RL
Vout
(a) An NMOS
transistor circuit.
ISD
Vout
(b) A PMOS
transistor circuit.
NMOS and PMOS transistor circuits
For the PMOS circuit, we have the following equations:
Vout  VDD  VSD  I SD RL
(1.4-1)
The equation Vout  I SD RL defines the load line for PMOS circuits.
We use the I-V curves in Fig. 1.4-2. First, we plot - VSD vs I SD as in Fig.
1.4-4.
ISD
VSG
0
Fig. 1.4-4.
-VSD
I-V curve for  VSD for a PMOS transistor.
We then plot Vout  VDD  VSD  VSD  VDD as in Fig. 1.4-5.
1-15
ISD
VSG
increasing
VDD
Fig. 1.4-5
Vout
I-V curve for Vout for a PMOS transistor.
Finally, we add the load line which is I SD  Vout / RL to Fig. 1.4-5 to produce Fig.
1.4-6.
ISD=Vout/RL
ISD
VSG
VDD
Fig. 1.4-6
Vout
I-V curves and a load line for a PMOS transistor circuit
Let us compare the two circuits shown in Fig. 1.4-7.
VDD
VDD
IDS
RL
G
Vin
G
D
S
Vout Vin
NMOS
S
D
RL
ISD
Vout
PMOS
Fig. 1.4-7. An NMOS transistor circuit and a PMOS transistor with the same Vin .
For NMOS transistors where S is grounded, I DS is determined by
1-16
VGS  VG and for PMOS transistors where the source is connected to VDD , I SD is
determined by VSG . That is, Vin  VG . But, in this PMOS case, VSG  VDD  VG .
Since VDD is a constant, we conclude that for PMOS transistors, VSG is also
determined by VG . That is, for PMOS circuits, Vin  VG is also true. Thus, in
both cases, we may simply say that VG is the input voltage Vin , as shown in Fig.
1.4-7.
It can be noted that for an NMOS transistor, the higher the current going through
it, the lower Vout . The situation is just the opposite for PMOS transistors. The
higher the current, the higher Vout . They are complementary to each other, a very
useful property which will be discussed later.
For NMOS transistors, if Vin increases, the current increases. Thus for these
transistors, the increase of Vin will increase the current and decrease the output
voltage Vout . For PMOS transistors, if Vin increases, VSG decreases and the
current decreases. However, it can be easily seen that this will in turn decrease the
output Vout . Thus we conclude that for both NMOS and PMOS transistors, the
increase of Vin will decrease the output voltage Vout . Similarly, a decrease of
Vin will increase the output voltage Vout for both NMOS and PMOS transistors.
This is another important property of these transistors.
1-17
Section 1.5
The Depletion Type MOSFET Transistors
The depletion type MOSFET transistors are quite similar to the enhancement type
MOSFET transistors. The only difference is the polarity of Vt . Vt is positive for
enhancement type NMOS transistors, but negative for depletion type NMOS
transistors. It is negative for enhancement type PMOS transistors, but positive for
depletion type PMOS transistors. Fig. 1.5-1 illustrates this.
enhancement
PMOS
depletion
PMOS
IDS
-VGS
Fig. 1.5-1.
depletion
NMOS
enhancement
NMOS
VGS
I DS versus VGS for depletion type and enhancement type transistors.
1-18
Section 1.6
Experiments
In this section, we show several experiments using the SPICE circuit simulation
system. For each circuit and for every experiment, we shall give the SPICE program
written for the purpose. We cannot explain the details of the SPICE program
grammatical rules. The reader may consult any SPICE manual. The VLSI model
for the transistors is mm0355v.1’TT.
In the above sections, we did not mention a term, namely, the body of a transistor.
We shall not elaborate the physical meaning of the body. Throughout the
experiments, for NMOS transistors, the body is connected to the low power supply
while for the PMOS transistors, the body is connected to the high power supply.
Experiment 1.6-1 I-V Curves
The purpose of this experiment is to show a family of I-V curves. The power
supply voltage VDD is set at 3.3V. Fig. 1.6-1 shows the circuit. Table 1.6-1 shows
the SPICE program and Fig. 1.6-2 shows the simulation result.
VDD=3.3V
1
R1=100k
2
3
VGS
out
M1 L=0.35u W=5u
Fig. 1.6-1. The circuit for Experiment 1.6-1.
Table 1.6-1.
Program for Experiment 1.6-1.
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1-19
VDD
R1
V2
1
1
2
0
3.3v
2
0
100k
0v
.param W1=5u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS
3
0
0v
.DC V2 0 3.3v 0.1v SWEEP VGS 0.1v 3v 0.25v
.PROBE I(M1)
.end
IDS
VGS
VDS
Fig. 1.6-2.
Experiment 1.6-2
I-V curve for the circuit in Fig 1.6-1.
A Single I-V Curve and the Load Line
In this experiment, we shall show the intersection of a load line and a single I-V
curve. The circuit is biased at 0.65V. The load is 100K and the power supply
1-20
voltage VDD is set at 3.3V as shown in Fig. 1.6-3 .
Fig. 1.6-4 shows the result.
VDD=3.3V
1
R1=100k
2
out
3
M1 L=0.35u W=5u
0.65V
Fig. 1.6-3. The circuit for Experiment 1.6-2.
Table 1.6-2.
Program for Experiment 1.6-2.
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VDD
R1
V2
1
1
2
0
2
0
3.3v
100k
0v
.param W1=5u
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS
3
0
0.65v
.DC V2 0 3.3v 0.1v
.PROBE I(R1) I(M1)
.end
1-21
IDS
R1=100k
Fig. 1.6-4.
I-V curve and the load line for Experiment 1.6-2.
Experiment 1.6-3 The Operating Point with the Same VGS and a Smaller RL.
In this experiment, we use the same bias voltage
VGS , but a smaller load of
50K, as shown in Fig. 1.6-5. The program is in Table 1.6-3 and the simulation result
is shown in Fig. 1.6-6. As can be seen, we have a higher V DS . This may not be so
good as we shall see later in the next chapters.
VDD=3.3V
1
R1=50k
2
3
out
M1 L=0.35u W=10u
0.65V
Fig. 1.6-5. The circuit for Experiment 1.6-3.
1-22
Table 1.6-3.
Program for Experiment 1.6-3.
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VDD
R1
1
1
0
V2
2
.param
W1=5u
3.3v
2
50k
0
0v
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS
3
0
0.65v
.DC V2 0 3.3v 0.1v
.PROBE I(R1) I(M1)
.end
1-23
IDS
R1 = 50k
VDS
Fig. 1.6-6.
Experiment 1.6-4
I-V curve and the load line for Experiment 1.6-3.
IDS-VGS with Almost No Load
In this experiment, we set the load to be very small so that I DS can grow indefinitely
with VGS . The circuit, the program and the experimenting result are shown below.
VDD=3.3V
1
R1=0.01k
3
2
out
M1 L=0.35u W=5u
VGS
Fig. 1.6-7. The circuit for Experiment 1.6-4.
1-24
Table 1.6-4.
Program for Experiment 1.6-4.
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VDD
R1
1
1
0
3.3v
2
.param
M1 2
W1=5u
3
0
0
0.01k
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS
3
0
0v
.DC VGS 0 3.3v 0.1v
.PROBE I(M1)
.end
1-25
IDS
R1 = 0.01k
VGS
Fig. 1.6-8.
I DS versus VGS for Experiment 1.6-4.
Note in Fig. 1.6-8, we are plotting I DS versus VGS , not V DS .
Experiment 1.6-5
IDS and VDS versus VGS with a Relatively Large Load
We use a load of 100K. Now, I DS can not grow indefinitely with VGS . The
circuit, the program and the experimental results are shown as below. As can be
seen, the I DS quickly becomes a constant because of the load. Similarly, the
simulation also shows that V DS quickly drops to 0. Note that we denote V DS to be
Vout .
VDD=3.3V
1
R1=100k
2
out
3
VGS
M1 L=0.35u W=5u
1-26
Fig. 1.6-9. The circuit for Experiment 1.6-5.
Table 1.6-5.
Program for Experiment 1.6-5.
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VDD
1
0
R1
1
.param
W1=5u
3.3v
2
100k
M1 2
3
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS
3
0
0v
.DC VGS 0 3.3v 0.1v
.PROBE I(M1)
.end
1-27
VDS
IDS
R1 = 100k
VGS
Fig. 1.6-10.
Experiment 1.6-6
Vout and I DS versus VGS for Experiment 1.6-5.
VDS/VGS Relationship with Different Loads
In this experiment, we tested the VDS/VGS relationship for small, moderate and
very large loads. It can be seen that for very small load, VDS changes very slowly
with respect to VGS. For R1=100K, there is an appropriate VGS, namely VGS=0.65V.
But, for R1=10000K, VGS must be smaller than 0.5V. Yet Vt=0.5V. If VGS is smaller
than 0.5V, the transistor is virtually cutoff. An examination of the current for
R1=10000K shows that it is equal to 160na, which indicates that the transistor is
virtually cutoff.
The circuit is in Fig. 1.6-11. The programs are in Table 1.6-6 to Table 1.6-9.
The results are in Fig. 1.6-12 to Fig. 1.6-16.
1-28
VDD=3.3V
1
R1=0.1k
2
out
3
VGS
M1 L=0.35u W=5u
Fig1.6-11. The circuit for Experiment 1.6-6.
Table 1.6-6.
SPICE program for Experiment 1.6-6 with R1=0.1k.
•
•
•
•
•
example1
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•
•
•
•
•
•
•
•
•
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VDD 1
0
3.3v
R1
1
2
0.1k
.param W1=5u
M1
2
3
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
VGS 3
0
0v
.DC VGS 0 3.3v 0.1v
•
.PROBE I(M1)
•
.end
1-29
Vout
VDS
IDS
R1=0.1K
VGS
Fig. 1.6-12.
Vout and I DS versus VGS
Table 1.6-7.
with R1 =0.1k for Experiment 1.6-6.
SPICE program for Experiment 1.6-6 with R1=10k.
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example2
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VDD
R1
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.param W1=5u
M1
2
3
0
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+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
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VGS 3
0
0v
.DC VGS 0 3.3v 0.1v
.PROBE I(M1)
.end
1
0
1
3.3v
2
10k
0
1-30
Vout
VDS
IDS
R1=10K
VGS
Fig. 1.6-13.
Vout and I DS versus VGS
Table 1.6-8.
with R1 =10k for Experiment 1.6-6.
SPICE program for Experiment 1.6-6 with R1=100k.
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VDD 1
0
R1
1
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.param W1=5u
M1
2
3
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
3.3v
2
100k
1-31
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VGS 3
0
0v
.DC VGS 0 3.3v 0.1v
.PROBE I(M1)
.end
Vout
VDS
IDS
R1=100K
VGS
Fig. 1.6-14.
Vout and I DS versus VGS
Table 1.6-9.
with R1 =100k for Experiment 1.6-6.
SPICE program for Experiment 1.6-6 with R1=10000k.
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VDD 1
0
3.3v
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R1
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.param W1=5u
M1
2
3
0
0
+nch L=0.35u W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
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VGS 3
0
0v
.DC VGS 0 3.3v 0.1v
.PROBE I(M1)
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1
2
10000k
Vout
VDS
IDS
RL=10000K
VGS
Fig. 1.6-15.
Vout and I DS versus VGS
with R1 =10000k for Experiment 1.6-6.
In this case, the current is 160na which indicates that the transistor is virtually cutoff.
1-33
R1=0.1k
VDS
R1=100k
R1=10k
R1=10000k
VGS
Fig. 1.6-16.
Vout and I DS versus VGS
with R1 =0.1k, 100k, 10k and 10000k for
Experiment 1.6-6.
Experiment 1.6-7 An Experiment on a PMOS Circuit
In this experiment, we try to obtain I-V curves and load lines for a PMOS
transistor circuit. The circuit is shown in Fig. 1.6-17. The program is in Table
1.6-10 and the result is in Fig. 1.6-18.
1 VDD
Rdm
3G
0.7V
S 1_1 ISD
D 2
VG
RL=2k Vout
Fig. 1.6-17 A PMOS circuit for Experiment 1.6-7
1-34
Table 1.6-10 Program for Experiment 1.6-7
PMOS
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VDD
1
0
3.3v
M1 2
3
1_1 1_1 PCH W=5u
VG
3
0
RL
Vout
Rdm1
2
2
1
0
2k
0
0v
1_1 0
L=0.35u
0.7v
.DC Vout 0 3.3v 0.1v
.PROBE I(Rdm1) I(RL)
.end
In Fig. 1.6-7, there is a resistor Rdm  0 . The reader may wonder why we need
such a resistor. This resistor is there because we want to know the value of I SD in
the PMOS transitor. But the SPICE program insists that all currents in a transistor,
be it an NMOS or a PMOS, is I DS . Therefore if we probe the PMOS transistor
directly, we will see negative currents because after all, current in a PMOS is from
source to drain. If we have a resistor with no value there, it will not incfuence the
behavior of the circuit. But it will allow us to measure the current by probing the
current in the resistor
1-35
Fig. 1.6-18 The I-V curve and the load line of the PMOS circuit in Fig. 1.6-17
Experiment 1.6-8
An Experiment of I-V Curves on a PMOS Circuit
In this experiment, we try to show a family of I-V curves and load lines for a
PMOS transistor circuit. The circuit is shown in Fig. 1.6-19. Table 1.6-11 shows
the SPICE program and Fig. 1.6-20 shows the simulation result.
1 VDD
Rdm
3G
S 1_1 ISD
D 2
VG
RL=2k
Vout
Fig. 1.6-19 A PMOS circuit for Experiment 1.6-8
1-36
Table 1.6-11 Program for Experiment 1.6-8
PMOS
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VDD
1
0
3.3v
M1 2
3
1_1 1_1 PCH W=5u
VG
RL
3
2
0
0
Vout
Rdm1
2
1
0
0v
1_1 0
L=0.35u
0v
2k
.DC Vout 0 3.3v 0.1v SWEEP VG 0 3.3v 0.25v
.PROBE I(Rdm1) I(RL)
.end
1-37
Fig. 1.6-20. A family of I-V curves and load lines for the circuit in Fig 1.6-19.
Experiment 1.6-9
A PMOS Circuit Input/Output Curve
In this experiment, we plot an input/output curve of a PMOS circuit. The circuit is
shown in Fig. 1.6-19. The SPICE program is in Table 1.6-11 and the result is in Fig.
1.6-20.
3.3v
G
VG
Fig. 1.6-19
S
D
ISD
RL= Vout
100k
A PMOS circuit
1-38
Table 1.6-11 Program for Experiment 1.6-9
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VDD
1
0
3.3v
M1 2
3
1_1 1_1 PCH
VG 3
RL 2
Rdm1
0
0
1
0v
100k
1_1 0
W=5u
L=0.35u
.DC VG 0 3.3v 0.1v
.end
Vout
2
VG
Fig. 1.6.-20 Input/output urve of the PMOS circuit for Experiment 1.6-9
1-39
Experiment 1.6-10
A PMOS Circuit Input/Output Curve with R  2 K
In this experiment, we first display the IV-curves of the PMOS circuit and it load
when R  2 K : The program is in Table 1.6-11 and its result is in Fig. 1.6-21.
Table 1,6-11 Program for the first part of Experiment 1.6-10
HW1
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VDD
M1 2
1
3
0
3.3v
1_1 1_1 PCH W=5u
L=0.35u
VG
3
0
0v
RL
2
0
2k
Vout
2
0
0v
Rdm1
1
1_1 0
.DC Vout 0 3.3v 0.1v SWEEP VG 2v 3.3v 0.25v
.PROBE I(Rdm1) I(RL)
.end
Fig. 1.6.-21
IV-curves of the PMOS circuit and its load line for Experiment 1.6-10
We then plotted the inut output curve corrsponding to this load R  2 K .
1-40
The
program is in Table 1.6-12 and the result is in Fig. 1.6-22. The program is in Table
1.6-12 and the result is in Fig. 1.6-23. As can be seen, this curve is not sharp at all.
This is due to small load R  2 K
Table 1.6-12
Program for the second part of Experiment 1.6-10
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VDD
M1 2
VG 3
1
3
0
0
3.3v
1_1 1_1 PCH W=5u
0v
L=0.35u
RL 2
0
2k
Rdm1
1
1_1 0
.DC VG 0 3.3v 0.1v
.end
Fig. 1.6-23
Experiment 1.6-11
The input out curve for Experiment 1.6-10 with R  2 K
A PMOS Circuit Input/Output Curve with R  100K
In this experiment, we repeateded Experiment 1.6-10 with R  100K . The
1-41
results are shown in the following figures. We can see that the input output curve is
much sharper due to the larger load.
Table 1.6-13 Program for the first part of Experiment 1.6-11 with R=100k.
Fig. 1.6-24 The input out curve for Experiment 1.6-11 with R  100K
1-42
Section 1.7
Exercise 1
1. Explain the current directions for NMOS and PMOS transistors.
2. Draw a curve to explain the triode region and saturation region of an NMOS
transistor. Why is the triode region also called the ohmic region? Why is the
other region called the saturation region?
3. What condition separates the triode region and the saturation region?
4. Derive the formula of I DS vs VGS in the saturation region. Note that I DS is
independent of V DS , which is expected in the saturation region.
5. Consider the following circuit in Fig. 1.7-1.
VDD
RL
IDS
D
G
S
VG
VDS
Fig. 1.7-1 A circuit for Problem 5 of Exercise 1
(a) Give the formula relating V DS and I DS .
(b) Explain how V DS and I DS are determined.
6. In the above circuit, plot the curves relating and Vout = V DS for RL small, RL
moderate and RL large.
7. Consider the following PMOS transistor below in Fig. 1.7-2
VDD
G
S
D
VG
RL
ISD
Vout
Fig. 1.7-2 A PMOS circuit for Problem 7 of Exercise 1
1-43
(a) Give the equation describing the relationship between Vout and I SD .
(b) Give the relationship between I SD and VSD .
(c) Draw a diagram relating Vout and I SD for different VSG ' s .
(d) Explain how Vout and I SD are determined.
8. Consider the following circuits in Fig. 1.7-3. For both circuits, Vout decreases
as VG increases. Explain.
VDD
VDD
RL
G
IDS
S
D
G
D
S
VG
VG
ISD
RL
Vout
Vout
PMOS
NMOS
Fig. 1.7-3 NMOS and PMOS circuits for Problem 8 of Exercise 1
9. We often say that the gate bias voltage VGS can be neither too small, nor too
large.
In other words, it has to be appropriate.
1-44
Explain.