PWM Reference
Channels 0, 1, 4, and 5 Get Clock A or Clock SA
Channels 2, 3, 7, and 8 Get Clock B or Clock SB
{A or B} PWM freq = 2e6/((PV) Period){SA or SB} PWM freq = 2e6/(2 (SV)
(PV)
Period)
Three 8-Bit Registers for Each PWM Channel
• PWMCNTx: Counter
• PWMPERx: Period select
• PWMDTYx: “Duty” time (beginning of cycle to polarity switch)
Three Control Bits for Each PWM Channel
• PWMEx: Enable
• PPOLx: Polarity (starting value in each PWM cycle)
• CAEx: Center Alignment
Enable
CAEx – Center Aligned Output Mode on Channel x
1 = Channel x operates in Center Aligned Output Mode
0 = Channel x operates in Left Aligned Output Mode
PPOLx – Pulse Width Channel x Polarity
1 = PWM Channel x output is high at the beginning of the period, then
goes low when the duty count is reached.
0 = PWM Channel x output is low at the beginning of the period, then
goes high when the duty count is reached
Analog to Digital Reference
It is desired to use the analog to digital converter of the MC9S12DP256B microcontroller to sample music using
channel 0 of module AD0. We would like 10-bit resolution and we would like the sampling rate to be as high as
possible. We would like to sample in sequences of 8 samples, and we would like to use an interrupt to signal when
the data is ready. List all the values that should be initialized into all the necessary registers to initialize the A/D
system and start the conversion process. Assume that the Bus Clock is a 2 MHz clock.
ATD0DIEN = xxxxxxx0 //IEN0=0, channel 0 is an analog input
ATD0CTL2 1xxxx01x = //ADPU=1, ETRIGE=0, ASCIE=1
ATD0STAT = 1x11xxxx //Clear SCF and other flags
ATD0CTL3 = 00000xxx //s8c,s4c,s2c,s1c=0 or 1xxx (sequence of 8 conversions)
ATD0CTL4 = 00000000 //SRES8=0 (10-bit mode), SMP=0 (2 cycle conversion), PRS=0 (fastest clock)
//ATD clock = bus clock/(2*(PRS+1)) = 2MHz/2 = 1MHz
//ATD Clock Period = 1 µsec
//2 Clocks for Phase 1 of Sampling
//2 Clocks for Phase 2 of Sampling
//10 Clocks for Conversion
//14 Clocks * 1 µsec = 14 µsec = Conversion Time
//ISR will execute every 14 * 8 µsec = 112 µsec
//channel 0 will sample at 71,429 Hz, max input is 35,714 Hz
0xFFD2 = <ISR address> (i.e. SETVECT(0xFFD2,atd_isr);)
CCR = xxx0xxxx (i.e. ENABLE();)
ATD0CTL5 = xx100000 //scan=1, mult=0, CC,CB,CA=0 (continuously scan channel 0)
void atd_isr(){…}
Controller Area Networks (CAN)
1. Two CAN nodes begin transmitting at almost the same time, node A sends a control ID of 0x3F1 and node B sends a control ID of
0x2F1. What happens, and what should these nodes do? What is the maximum percentage of time lost due to collisions on the CAN
bus? Answer: Node B wins and continues to send its message. Node A loses and becomes a receiver of B’s message. No time is lost.
Recall that ‘0’ is dominant and ‘1’ is recessive. The node that does not read a ‘0’ on the bus while it is sending a ‘1’, is the winner, and
continues to send its message. Since no two nodes are allowed to send the same control ID, there can only be one winner. The losers
will read a ‘0’ while sending a ‘1’ at some point, and from that point they stop sending and become listeners.
2. Using the CAN-bus protocol, what type of frame is sent to request data? Answer: A remote frame.
3. CAN-bus protocol uses NRZ encoding with bit-stuffing. Why is bit stuffing needed? Bit stuffing is used to prevent special
sequences from occurring within data bits. Recall: Error Flag = 6 consecutive dominant bits; End of Frame = 7 consecutive recessive
bits; Error Delimiter = 8 consecutive recessive Bits
4. In normal CAN operation, under what conditions could two nodes transmit at the same time? Answer:
Arbitration,Acknowledgement,Error flag transmission
5. How is the length of a CAN-bus frame determined? Answer: Within a data frame, 4 bits of the Control Field are the Data Length
Code (DLC) and specify the number of bytes of data contained in the message (0 - 8 bytes).
6. In the HCS12 CAN module, what are acceptance registers and mask registers used for? provide hardware message filters to reduce
the number of messages that must be processed in software. The mask determines which bits of the control register are compared and
the acceptance register contains the desired bit values.
Universal Serial Bus (USB)
7. Assuming no other USB devices are present, how many high-speed USB devices can send or receive data at 100Mbps over the same
time interval? Answer: 4
8. Send 101010111111 using NRZI , Answer: If last bit was a 1: 1111110110011, Answer: If last bit was a 0: 0000001001100
9. List one benefit and one drawback when comparing USB to SCI communication. Good: High speed, many devices
Bad: More complex implementation
#define PORTAD _P(0x8F) // port ADC = input only
#define ADR00H _P(0x90) // ADC result 0 register high byte
#define ADR00L
_P(0x91) // ADC result 0 register low byte
#define ADR01H _P(0x92) // ADC result 1 register
#define ADR01L
_P(0x91) // ADC result 1 register low byte
#define ADR02H _P(0x94) // ADC result 2 register
#define ADR02L
_P(0x91) // ADC result 2 register low byte
#define ADR03H _P(0x96) // ADC result 3 register
#define ADR03L
_P(0x91) // ADC result 3 register low byte
#define ADR04H _P(0x98) // ADC result 4 register
#define ADR04L
_P(0x91) // ADC result 4 register low byte
#define ADR05H _P(0x9A) // ADC result 5 register
#define ADR05L
_P(0x91) // ADC result 5 register low byte
#define ADR06H _P(0x9C) // ADC result 6 register
#define ADR06L
_P(0x91) // ADC result 6 register low byte
#define ADR07H _P(0x9E) // ADC result 7 register
#define ADR07L
_P(0x91) // ADC result 7 register low byte
#define ATD0DR00H _LP(0x90) // ADC result 0 register
#define ATD0DR01H _LP(0x92) // ADC result 1 register
#define ATD0DR02H _LP(0x94) // ADC result 2 register
#define ATD0DR03H _LP(0x96) // ADC result 3 register
#define ATD0DR04H _LP(0x98) // ADC result 4 register
#define ATD0DR05H _LP(0x9A) // ADC result 5 register
#define ATD0DR06H _LP(0x9C) // ADC result 6 register
#define ATD0DR07H _LP(0x9E) // ADC result 7 register
IENx = “1” – Input is Digital
IENx = “0” – Input is Analog
10. Name the most appropriate USB transfer type for each operation below: a) _ isosynchronous _Sending the audio signal for a digital
telephone, b) _ control _Checking the ink status on a printer, c) bulk Sending a document to a printer, d) interrupt Sending the out-ofpaper message from a printer
11. In USB, what is the relationship between transfers and packets. Answer: Each transfer consists of one or more transactions, and
each transaction consists of 1 to 3 packets.
12. What is the primary reason why USB would not be the ideal protocol for a distributed control system? Answer: USB would not
allow the components to communicate independently. More: USB relies on the host controller to schedule all communication, and
lateral communication is not supported.
ATD Clock = .5*BusClock/(PRS+1)