Microcomputer System
ECE 3551
Laboratory Experiment 5
FIR Digital Filter Implementation
Preformed By:
Brandon Schmitt
Submitted:
April 27, 2007
Table of Contents
Page
Abstract………………………………………………………… 1
Introduction……………………………………………………. 1
Implementation………………………………………………… 2
Filter Code Implentation….…………………………….. 2
Challenges…………………………………………………….. 3
Conclusion……………………………………………………. 4
Appendix A…………………………………………………… 5
Abstract
The goal of the FIR lab is to design and develop 3 separate implementations of a digital
FIR filter in an embedded platform. Analog Devices’ Blackfin BF533 DSP is to be
utilized to implement a floating point, integer and fract16 number representation version
of the FIR filter.
Introduction
In order to develop the filter implementations Analog Devices’ BF533 DSP on the EZKit Development Board will be used. The BF533 DSP supports development through the
VisualDSP++ development environment. The code is programmed in C then compiled
and loaded onto the development board through a USB interface cable. The EZ-Kit
supports the USB interface, real-time in circuit debugging, and peripheral circuits to
interface audio.
The FIR filter like all analog signal filters is design to reduce the magnitude of frequency
components outside the desired range. Unlike analog implementations of signal filters
built with capacitors, inductors and resisters, the FIR is a digital filter. A fast digital
signal processor (DSP) such as the BF533 is used to create a model of the filter in
programmed code. The model then acts upon small sections of the analog signal sampled
forty-eight thousand times per second.
By implementing software versions of a filter it is possible to configure multiple stages
with multiple coefficients and delay lines quickly and efficiently. A change to a digital
filter can be made by altering a line of code avoiding the need to remove, reconfigure and
rebuild analog components. Some digital implementations can be reprogrammed while
the chipset is inside a working production board, as is the case with the EZ-Kit
development board. To change the filter’s structure, coefficients, and as such frequency
response, a programmer needs only to change a few lines of code and reload the program
onto the DSP’s chipset. The result is a high quality filtering system which is easy to
implement and can outperform much more complex analog filter designs.
The FIR filter’s implementation is greatly simplified when compared to the IIR
implementation of the previous lab. The filter’s calculations are computed entirely with
the time domain representation of the signal with no need to store previously calculated
results.
The filter’s calculations can be modeled by the following mathematical representation.
M
yn    k xn  k  (kepuska, p.3)
k 0
where Bk is the kth filter coefficient, and M is the total number of filter coefficients.
The larger the value of M the more defined with sharper frequency response the filter
becomes.
Implementation
The first step to implementing the FIR filter on Analog Devices BF533 is to initialize and
configure the appropriate registers and subsystems of the DSP. For this lab the analog to
digital converter (ADC), digital to analog converter (DAC), direct memory addressing
(DMA), serial port, leds 4 through 9 and EZ-Kit push buttons SW4 and SW5 were
necessary.
Initialization of serial port, dma, ADC and DAC did not differ from the previous audio
labs in the class. To configure the SW4 and SW5 switches FlashA PortA was set to input.
To configure leds 4 through 9, the six least significant bits of FlashA PortB were set to
output and the data was set to zero. The data update resulted in all six leds controllable
through the FlashA_PortB_Data register and set to off.
Audio input was achieved by converting the analog signal waveform to a digitally
sampled stream of 24-bit samples at a rate of forty-eight thousand times per second. The
data was converted by the AD1386 digital to analog converter on the EZ-Kit
development board, and passed to the processor via the SPORT0 serial port interface.
The sampled signal values arrive and the SPORT0 interrupt is triggered. Depending upon
the system output state which is selected by the user using the switches SW4 and SW5
the value is then bit shifted to the left eight places to adjust the range such that the sample
can be handled as a 32-bit integer and passed to either the low pass filter processor, the
high pass filter processor, or the value is not bit shifted and sent directly to the output.
Filter Code Implementation
The FIR filter is represented as an array of 21 floating point coefficients. The input
samples are stored in a buffer equal in size to the size of the filter coefficients. A circular
buffering technique overwrites the oldest same in the buffer with the newest each time a
new sample is received.
The buffer populates with the latest sample being placed at the position indicated by the
count variable which then increments by one until the end of the buffer is reached. Then
the count variable is reset to zero and begins incrementing with each new sample.
The output is determined by multiplying each sample by the associated filter coefficient.
With circular buffering employed the coefficient multiplication processes in two separate
passes, for samples from count to zero, then the buffer size to count + 1.
count = ((count + 1) % 21);
iBuffer[count] = (iOrigLeftIn << 8);
float output = 0.0;
int n = 0;
int i = 0;
for(i = count; i >= 0; i--)
{
output += DebugLowPass[n++] * iBuffer[i];
}
for(i = 20; i > count; i--)
{
output += DebugLowPass[n++] * iBuffer[i];
}
if (DebugCount < 1024)
{
buffer[DebugCount++] = ((int)(output) >> 8);
}
iTxBuffer1[INTERNAL_DAC_L0] = ((int)(output) >> 8);
The low and high pass filters are implanted using the same processing code with different
coefficients.
Challenges
The largest challenge experienced with the FIR lab was related to the number of
coefficients to process. Upon implementation of the filtering code, significant distortions
were observed in the output waveforms regardless of frequency. Upon troubleshooting
the function it was determined that the code should perform properly. Reducing the total
number of coefficients from 101 to 21 by removing 40 from both front and back of the
array resulted in a distortion-free waveform. The reduction of the coefficients also
increased the pass band of the high pass filter by approximately 50%.
With time restrictions in place only the floating point implementation was completed.
After reviewing course material it is quite possible that fract16 or full integer
representations will increase the processing efficiency to the point where additional
coefficients may be added.
One of the most useful troubleshooting tools used was to record 1024 samples into a
buffer integer array then halt the code and examine the buffer using Visual DSP++’s plot
function. By passing an input sinusoidal waveform from Matlab, then viewing the output
plot it helped significantly when tracking down signal distortion issues in the code.
Conclusion
After reducing the number of coefficients the filter performed quite well. The output
signals examined matched the input signals shape with the exception of attenuating the
stop band frequencies. Test frequencies of 250, 750, 10,000 and 15,000 hertz were
examined.
The low pass filter passed the 250 Hz signal with little attenuation while completely
attenuating the 15 kHz signal. The high pass filter performed equally well with the
inverse effect on the two test frequency extrema.
For future labs the only improvement would be to add equipment to the lab which would
allow qualitative measurements of filter signal output to be taken. An addition to the
laboratory manual regarding the Matlab code necessary to generate a pure tone sinusoid
would also have been helpful.
Appendix A: References
1. ECE 3551 MICROCOMPUTER SYSTEMS 1, Lab 5—Learn to process audio data,
Dr. Veton Kepuska.
2. ADSP–BF533 EZ-Kit Lite Evaluation Systems Manual, Analog Devices.