Homework Cover Sheet
CMPEN 411
Fall 2015
Section 1
NAME:
Homework
your-name-here
1
Total score:
Check list:
Homework turn-in:
Homework library and file names:
Correct Homework folder zipping, all files and the report file (in your hw1lastname folder):
Schematic files, error:
Layout files, DRC error, LVS matching:
Simulation files, hspice .sp file names:
Project simulation, top cell layout simulation:
Number of test input cases and simulations:
Test output wave form and correctness (function) check shown:
Test output wave form timing (and show worst case propagation delays) shown:
Homework report cover page, report file name, use the sample format:
Homework report - overall algorithm, cell hierarchy, circuit and layout design descriptions:
Homework report - figures and explanations:
Homework report - answers to questions:
Others:
Tool Use/Problem:
Comments:
Summary of Design Parameters: (Please fill-in based on your design)
Number of transistors:
total =
Layout size:
total area =
um**2
Worst case delay time:
Td =
nsec.
AT2 design efficiency =
um 2 * nsec2
Complete schematic design: completion = yes/no
Complete layout design:
completion = yes/no
Layout DRC error check passed:
yes/no
pmos =
nmos =
X=
um
Y=
um
Maximum clock cycle:
Freq. =
MHz
Worst case signal delay from:
To:
Complete schematic design verified with simulation: yes/no
Complete layout design verified with simulation: yes/no
LVS check passed:
yes/no
HOMEWORK 1 Report
1. Objective:
Learn the VLSI CAD tools and chip design concepts with a simple circuit.
2. Tasks:
Log into a Lab-218 machines, be familiar with basic UNIX commands.
Complete each steps on the CAD tool tutorial. Learn the VLSI CAD tools and chip design concepts with a simple circuit.
Creating a schematic and a chip layout of an AND gate. Simulate the netlist with the Hspice tool for the function
verification and signal delay measurement.
Experience a complete chip design homework/project and its proper submission.
3. Circuit/Block Diagram:
Figure 1. The main circuit to design and simulate, a 2 input AND gate with a changeable load capacitor CL.
4. Schematic Design and Simulation:
figures and explanations here
5. Layout Design and Simulation:
figures and explanations here
6. Simulation for Performance Parameters, Critical Timing, Noise Margin, and Process Variation Corners:
figures and explanations here (simulation result plots without any explanations are very difficult to understand)
7. Data Sheet/User's Guide:
explain how to use your chip. list each signal, show sample signal-timing diagram of proper use of your chip,
figures and explanations here
8. Answers to Questions:
answers, figures, and explanations here
9. Conclusion:
write the summary of what was designed and its key parameters.
explain what I learned. and explain how to improve the layout, speed, and power-use.
And list any comments.