SIM UNIVERSITY
SCHOOL OF SCIENCE AND TECHNOLOGY
DESIGN AN AUDIO METER
USING FPGA
STUDENT : ALAGENTHIRAN S/O NADESON (E0605744)
SUPERVISOR
PROJECT CODE
: MAK LIN SENG
: JUL2009/ENG/041
A project report submitted to SIM University
in partial fulfilment of the requirements for the degree of
Bachelor of Engineering (or Bachelor of Electronics)
May 2010
Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
(E0605744 )
ABSTRACT
In this project the main aim is to design an audio meter using development boards
with Field Programmable Gate Arrays (FPGA). An additional microphone component
was added and Very High Speed Integrated Circuit (VHSIC) or VHDL was used as
the hardware description language (HDL). The development was done using Xilinx
Saprtan3E and 3A development board with XC3S500E FPGA and XC3S700A. Some
initial study about the audio meters and sound measurements were being studied.
Then, a suitable microphone was determined after some research, which was the
PMOD MIC product readily available for Xilinx or DIGILENT development boards.
This was followed by determining the suitable HDL to write the coding. Research was
done for the suitable FPGA development boards readily available from manufacturers
for evaluation. The programming was done on multiple VHDL Blocks required for
the audio meter which will eventually display a sound measurement in decibels (dB).
The blocks were designed and then followed by a top level code which will integrate
the implement the design. The software simulation was done before downloading the
final design into the FPGA and testing it. This design is able to capture sound via the
microphone, able to perform measurement, convert the signal into dB and display
onto the Liquid Crystal Display (LCD).
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Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
(E0605744 )
ACKNOWLEDGEMENT
First of all, I would like to thank my family for encouraging me to further my studies
to a Bachelors Degree level despite enduring financial difficulties and missing a lot of
my love and time dedicating to them. Next is my project supervisor Mr. Mak Lin
Seng who is my core motivator in providing all technical and moral support to make
my project journey to a success. I would also like to thank my company supervisors
Mr. Lee Yow Wei for allowing me to take time off and additional leaves to attend to
my project and my colleagues who covered my duties while I’m not around . In
addition I would also want to appreciate the following individuals for providing
support during the project: Mr. Felix Keng, Mr. Min Thu Naung, Mr. John Kent, Mr.
Abdul Azeez Mr. Steven Tan, Mr. S. Jamaludeen, and Mr. Loo Soon Koon.
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Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
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TABLE OF CONTENTS
Contents
Page
ABSTRACT
i
ACKNOWLEDGEMENT
ii
TABLE OF CONTENTS
iii
LISTS OF FIGURES
iii
Figure 1.1.1a: Oscilla SM930 Screening Memory audiometer.
1
Figure 1.1.1b: An audiometric test being conducted in a sound proof
room.
2
Figure 1.1.2a: Analogue & Digital Audio Level Meters with UK (BBC) scale custom
2
numbering from 1-7 (software based).
Figure 1.1.2b: Audio level Meter from a Sony beta Recorder.
2
Figure 1.1.2c: An Analogue VU meter.
2
Figure 1.1.2d: Common Sound Level Meters which is handheld (left)
and Software based (right).
Figure 1.1.2e: An Audio Visual studio equipped with audio meter in a
mobile broadcasting van.
Figure1.1.3.1a: Audio Level Meter Application Circuit using National
Semiconductor IC, LM3915.
Figure1.1.3.1b: Audio Meter Application Circuit using National
Semiconductor IC, LM3916.
Figure1.1.3.1c: Audio Level Meter Circuit Using BC108B transistors
and small panel meter.
Figure 2a: An example of a logic block in an FPGA.
Figure2b: An Example of a Digital Audio Meter (or Level Meter) Block
diagrams.
Figure2.1: FPGA Design Flow.
Figure 2.3.1 : Two types of old PPM (mechanical zero on the left and
right hand side restpectively).
3
3
4
5
5
8
9
10
15
Figure 2.4.1: A low Voltage Microphone Pre-amplifier circuit.
16
Figure 2.4.2: The Differences of an analogue signal before and after
17
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Design An Audio Meter Using FPGA
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companding.
Figure 3.1.1.1a: Spartan-3A Development Board
22
Figure 3.1.1.1b: Spartan-3E Development Board
22
Figure 3.1.1.2: Altera’s Cyclone II FPGA Starter Board.
23
Figure 3.1.3.7: A 3.55mm Audio Jack.
27
Figure 3. 1.4a: PMOD peripheral module board with microphone for
Spartan3A or 3E boards.
Figure 3.1.4b: PMOD MIC Block diagram takes in analog sound
through microphone and outputs a digital sound signal.
Figure 3.3.1: Initial Concept of Audio Meter design using FPGA
(Revision1).
Figure 3.3.2: Audio Meter design using Voltage Averaging, Floating
Point, and Logarithmic Calculations (Revision2).
Figure 3.3.2.1. ADC Connection Diagram (left) and Block Diagram
(right).
Figure 3.3.3: Audio Meter FPGA using Programmable Memory Block
Diagram (Revision3)
Figure 3.3.3.3: LCD Display for permanent characters.
Figure 3.3.3.4: Connection Diagrams from Spartan3A and 3E to PMOD
MIC board.
Figure3.4: ADC code corresponding to the input voltage
Figure 4.1a: Jumper J30 settings for Master Serial Mode on Spartan-3E
board. [43]
Figure 4.1b: Jumper J26 & J46 settings for Master Serial Mode on
Spartan-3A board
Figure 4.2.1: Audiometer_toplevel.vhd block diagram.
Figure 4.2.2: Timing diagram for ADCS7574 ADC chip on PMOB MIC
board.
Figure 4.2.3: LCD Character Set
28
29
29
30
31
33
36
37
38
40
40
41
43
44
Figure 5.1.1a: Simulation Results Showing the signals (FPGA clock
(CLK), divided clock signal (SCLK), START, chip select (nCS) and the
49
initial ADC’s output signal (DATA)).
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Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
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Figure 5.1.1.b. : Simulation Results Showing the signals (FPGA clock
(CLK), divided clock signal (SCLK), START, chip select (nCS) and the
50
ADC’s output signal (DATA) 1st and 2nd value, DONE signal).
Figure 5.1.2a: Prototyping Setup for Programming and testing.
51
Figure5.2.1b: Downloading the audiometer_toplevel.bit (bitstream) file 52
on to the FPGA.
Figure5.2.1c: Result of the Permanent LCD Character from the program. 52
Figure5.2.1d: Result on LCD after START &RESET push button
53
asserted once in sequence.
Figure5.2.1e: Result on LCD after START & RESET push button
54
asserted the second time in sequence.
Figure 6.1: Initial Calibration Testing Using WWW DFG Sine Wave
55
Generator (right) and Peak Level Meter (right)
LIST OF TABLES
v
Table 3.1.2: Decision Matrix to choose the 3 different boards available.
24
Table 3.3.3.1: LCD Character to be written in ROM (*.coe file)
34
Table 3.3.3.1: LED codes to be written in ROM (*.coe file)
35
Table 3.4: ADC codes and their corresponding values to be set.
39
Table 4.2.2: Signal Naming in PMODMic.vhd program.
42
Table 4.25a: Signal Naming in LCD_controller_al.vhd program.
46
Table 4.25b: Control Signal combinations
47
LIST OF FORMULAS
v
Formula 2.5a: Power dB (10 log rule)
18
Formula 2.5b: Voltage dB (20 log rule)
19
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Design An Audio Meter Using FPGA
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Formula 3.3.2.2: VRMS Calculation
31
Formula 3.4a: LSB Calculation
38
Formula 3.4b: Voltage in dB
39
CHAPTER ONE: INTRODUCTION
1
1.1. Background and Motivation
1
1.1.1. Misconceptions (Hearing Test)
1
1.1.2. ALM, SLM, VU, PPM
2
1.1.3. Integrated Circuits
4
1.1.3.1. Common Audio Level Meter Circuitry Available
4
1.1.4. Why FPGA?
6
1.2. Objectives
6
1.2.1. Project objective
6
1.2.2. Overall objective
6
1.3. Scope
6
1.4. Layout of the Project report
6
1.5.Project Management
7
CHAPTER TWO: REVIEW OF THEORY AND PREVIOUS WORK
8
2.1 .
10
2.1.1 .
FPGA Development Process
Design Entry
10
2.1.2. Synthesis
10
2.1.3 .
11
Design Implementation
2.1.3.1 . Translate
11
2.1.3.2 Map
11
2.1.3.3 Place and Route (PAR)
12
2.1.4 . Xilinx Device Programming
12
2.1.5 . Design Verification
12
2.1.5.1. Behavioural Simulation
12
2.1.5.2. Functional
13
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Design An Audio Meter Using FPGA
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Simulation
2.1.5.3. Static Timing Analysis
13
2.2
14
Hardware Description Language
2.2.1
Verilog
14
2.2.2
VHDL
14
2.3
Peak Program Meter
15
2.4
Key Components in sound measurement
16
2.4.1
Pre- amplifier.
16
2.4.2
Compandor.
17
2.4.3
Analogue to Digital Converter.
18
2.6
Audio Level in
Decibels :Formula : 10 log
18
Rule and 20 log rule
2.7
Previous Works of Audio Meters using FPGA
20
2.7.1
DPLCM based on Altera Cyclone 2
20
2.7.2
Digimeter Based on Xilinx Spartan 3E
20
2.7.3
LABVIEW FPGA
20
CHAPTER THREE: DESIGN
21
3.1. Hardware Selection
21
3.1.1. FPGA Development Boards and Kits
21
3.1.1.1. Xilinx
22
3.1.1.2. Altera
23
3.1.2. Decision Matrix
24
3.1.3. Microphone Selection
25
3.1.3.1. Sensitivity
25
3.1.3.2. Frequency range
25
3.1.3.3. Signal Conditioning Requirements
26
3.1.3.4. Directionality
26
3.1.3.5. Frequency Response
26
3.1.3.6. Impedance
26
3.1.3.7. Handling Noise
26
3.1.4.
27
PMOD MIC
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Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
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3.2.
Software Selection
29
3.3.
Design Procedures (Block Diagrams).
29
3.3.1.
Initial Design: Audio Meter Design using FPGA (Revision1)
3.3.2.
Audio Meter FPGA using Voltage Averaging, Floating Point
and Logarithmic Calculators (Revision2).
29
30
3.3.2.1.PMOD MIC Block
31
3.3.2.2.Voltage Averaging Circuit Block
32
3.3.2.3.dB Conversion Circuit Block
32
3.3.2.4.Display Block
32
3.3.3.
33
Audio Meter FPGA Using Programmable Memory (Revision2)
3.3.3.1. LCD ROM Block
34
3.3.3.2. LED ROM Block
35
3.3.3.3. LCD Controller Block
36
3.3.3.4. PMOD MIC block
37
3.4.
38
Decibel calculation
CHAPTER FOUR: DESIGN CONFIGURATION AND SOFTWARE
DEVELOPMENT
40
4.1. FPGA Board Configuration
40
4.2. VHDL programs
41
4.2.1. Audiometer_toplevel.vhd
41
4.2.2. PMODMic.vhd
42
4.2.3. LCD_ROM.xco
44
4.2.4. LED_ROM.xco
45
4.2.5. LCD_controller_al.vhd
45
4.2.6. Audiometer_toplevel.ucf
48
CHAPTER FIVE: RESULTS & SIMULATION
49
5.1 Software Simulation
49
5.1.1. Spartan3A_MIC_tb.vhd
49
5.1.2. LCD_controller_al_tb.vhd
50
5.1.3. LCD_ROM.xco & LED_ROM.xco
50
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Design An Audio Meter Using FPGA
5.1.4.
Audiometer_toplevel_tb.vhd
Alagenthiran S/O Nadeson
(E0605744 )
51
5.2 Testing on Hardware
51
CHAPTER SIX: CALIBRATION AND FINE TUNING
55
55
6.1. Calibration and Finalization.
CHAPTER SEVEN: CONCLUSION & FUTURE WORK
57
7.1. CONCLUSIONS
58
7.2. FUTURE WORK
58
7.2.1. Audio Meter FPGA (Revision 2)
58
7.2.2. IPCORE
58
7.2.3. MICROBLAZE 32 bit Soft Processor.
58
7.2.4.LABVIEW FPGA
58
7.2.5.International Standards
58
CHAPTER EIGHT: REFLECTION
58
8.1. Project Management
58
8.2. VHDL Programming
58
8.3. FPGA Development
58
8.4. Stress Management
58
REFERENCES
60
APPENDIX A: Main Codes
63
Audiometer_toplevel.vhd
63
PMODMic.vhd
66
LCD_Controller_al.vhd
70
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Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
(E0605744 )
APPENDIX B: TEST BENCH CODES
78
Spartan3A_MIC_tb.vhd
78
lcd_control_tb.vhd
81
APPENDIX C: User Constraints CODE
84
Audiometer_toplevel.ucf
84
APPENDIX D: Decibel Calculations Worksheets
87
APPENDIX E: Gantt Chart
88
APPENDIX F: Spartan-3A Specs
89
APPENDIX G: Spartan-3E Spec
90
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Design An Audio Meter Using FPGA
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(E0605744 )
CHAPTER ONE
INTRODUCTION
1.1. Background and Motivation
1.1.1. Misconceptions (Hearing Test)
When we refer the term “audiometer”, it is commonly associated with the
device (Figure 1.1.1a) used for conducting hearing test to evaluate hearing loss
for patients in the medical industry especially at hospitals or ear specialists’
clinics. In other words this test is also called as audiometric test where
normally the patient is required to sit in a sound proof room (Figure 1.1.1b).
[1, 2]
Figure 1.1.1a: Oscilla SM930 Screening Memory audiometer. [3]
Figure 1.1.1b: An audiometric test being conducted in a sound proof room. [2]
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Design An Audio Meter Using FPGA
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1.1.2. ALM, SLM, VU and PPM
In this project, it is more focused on “Audio Meter”. The definition of the
term “audio” refers to an electrical signal produced from the sound pressure
wave being converted into an electrical energy [4] and “meter” is a
measurement device, in this case, for audio signals. [5, 6]
A more commonly used term are Audio Level Meter (ALM) (Figures 1.1.2a &
1.1.2b), Level Meter, Volume Units (VU) Meter (Figure 1.1.2c), Peak
Programme meter (PPM), Sound Level Meter (SLM) (Figure 1.1.2d).
Figure 1.1.2a: Analogue & Digital Audio Level Meters with UK (BBC) scale
custom numbering from 1-7 (software based) [7]
Figure1.1.2b: Audio level Meter from a Sony beta Recorder
Figure 1.1.2c: An Analogue VU meter. [8]
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Figure 1.1.2d: Common Sound Level Meters which is handheld (left) and
Software based (right) [10, 11]
Commonly, the available Audio Meters comes with three different type of
indicators used for the Audio Meters. Namely, LED lights & measurement
(e.g. 90.0 decibels (dB)) indicators for digital Audio Meters (Figure
1.1.2b&1.1.2d) whereas for Analogue Audiometers comes with needle and
scale indicators (Figure 1.1.2a and 1.1.2c)
Audio Level Meters, Peak Programme Meters and VU Meters are also used in
audio post production in music, radio and television (TV) industries (Figure
1.1.2e) [12,13].
Figure 1.1.2e: An Audio Visual studio equipped with audio meter in a mobile
broadcasting van [14].
Those meters’ purpose is to ensure the suitable loudness range is received by
the viewers or listeners of the music or TV [10]. On the other hand, a Sound
level Meter is more for industrial usage which is used to monitor noise
pollution levels where workplace safety is concerned (e.g. industrial
environmental and aviation industry). [15]
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1.1.3. Integrated Circuits
1.1.3.1. Common Audio Level Meter Circuitry Available
There are many readily available integrated circuit (IC) designs for direct
installation on circuit for various applications.
Audio Level Meter (VU meter) circuit in Figure 2.3.1a is using LM3915, an
IC manufactured by National Semiconductor (NS). This circuit will convert
the audio input source to its corresponding audio level in terms of 10 LEDs.
The IC will sense the analogue input voltage level and drives the LEDs to
provide logarithmic 3dB per step analogue display [17].
Figure1.1.3.1a: Audio Level Meter Application Circuit using
National Semiconductor IC, LM3915.
Another Audio Level Meter circuit example is the one using LM3916 IC by
NS. Similar to LM3195, this IC is a bar graph or LED driver chip. The LEDs
output correspond to the standard VU meter scale of -20dB to +3db but
without -2dB. And the circuit below provides for a mono audio display but can
be modified for stereo as well. One different thing in this circuit is a
potentiometer is connected to the IC to set the +3db reference so that when a
0dB audio signal is send into the input, the 0dB LED should light up. Another
special thing is the circuit can also be switched to a bar graph or a dot graph
where only the particular LED will light up with reference to the audio level
[18].
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Design An Audio Meter Using FPGA
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Figure1.1.3.1b: Audio Meter Application Circuit using
National Semiconductor IC, LM3916.
Audio Level Meter using BC108B (Figure 1.1.3.1b), NPN transistors
manufactured by Siemens and Central Semiconductor, is another simple way
of measuring the analogue audio signal. In this circuit the signal goes through
the two transistors, which function as common emitter amplifiers and then
routed into a full bridge rectifiers formed by 1N4148 diodes, which then
converts the signals into varying DC voltage. The audio levels can be
measured using a small panel meter [19].
Figure 1.1.3.1c: Audio Level Meter Circuit Using BC108B transistors and
small panel meter.
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1.1.4. Why FPGA?
When it comes to designing audio measurements, there are not many designs
out there using FPGA prototyping boards. This project will discuss on the
possible techniques of designing one audio measurement prototype.
1.2. Objectives
1.2.1. Project objective
The main objective of this project is to design an Audio Meter using FPGA.
The initial objective of this project is to compare and evaluate the FPGA
prototyping boards readily available in the market and a selection is to be
made. The aim of this project will be to capture the sound from an audio input
and process the signal to generate a reading on a display panel (e.g. a seven
segment Light Emitting Diode (LED) or Liquid crystal display (LCD)) panel
on the development board.
1.2.2. Overall objective
The Audio Meter is a commonly used and needed device in the industry and
there are many ways of building one. As the FPGA chips are less used in
designing an Audio Meter, this project will be one of the first to choose FPGA
as a platform to develop it. In addition, this project will be a trial run for an
Audio Meter development on an FPGA platform. By using FPGA the number
of the integrated circuit (IC) chips need to used could be can reduced on the
circuit board as the FPGA chips has programmable logic in it.
1.3. Scope
The design of this audio meter is based on readily available FPGA prototyping boards
and an external microphone to capture the sound.
1.4. Layout of the Project report
This project report is divided into FIVE phases: Firstly, the research portion will
include the research on audio meters, sound measurements, microphones, FPGA,
HDLs followed by the discussion and selection of a suitable microphone, FPGA and
development boards, HDLs and software platform selections. Third, will be the
previous work done and the technology involved and the methodology involved. Next,
will be the simulation and testing and results gathering. Followed by the problems
encountered and any recommended improvements.
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Design An Audio Meter Using FPGA
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1.5. Project Management
Project management was done using five stages as mentioned below:





Research and Proposal
Design
Testing and Results Gathering
Finalization
Conclusion
A Gantt chart was used to manage this project (APPENDIX E).
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CHAPTER TWO
REVIEW OF THEORY AND PREVIOUS WORK
As the name suggests, the FPGA is a programmable semiconductor device that
are programmed using logic circuit diagram or source code in a HDL in order
to define how the chip to work. These chips contain logic blocks which has
programmable logic components. They also contain memory sections which
can be in a form of complete memory block or simple flip-flops. The FPGA
can be programmed as simple logic gates or complex combinational functions.
The architecture of the FPGA contains an array of configurable logic blocks
(CLB) (Figure 2a), input or output (I/O) pads and routing channels.
Figure 2a: An example of a logic block in an FPGA [20]
The concept of an Audio Meter is generally, there’s an audio signal being
input into the circuit and the output signal is measured where this will show
the volume of the audio. A typical concept of a digital Audio Meter illustrated
in the block diagrams in Figure 2b.
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Design An Audio Meter Using FPGA
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Figure2b: An Example of a Digital Audio Meter (or Level Meter)
Block diagrams [16].
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Design An Audio Meter Using FPGA
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2.1. FPGA Development Process
In FPGA development process, there are key fundamental processes which are
involved in FPGA design flow (Figure2.1) explained in the next subsections.
Figure2.1: FPGA Design Flow [33].
2.1.1.Design Entry
This is the very first stage in the FPGA development process. There are a few design
types to be chosen from. They are Hardware Description Language (HDL), schematic,
state machine based design types or a combination of both can be chosen [34]. The
schematic based design is a better choice if the design is hardware based and if the
design is more complex or algorithm based then HDL will be more appropriate and for
state machine based design is when a designer chooses to enter design using a series of
states [34]. In this project we’ll focus on HDL based design.
2.1.2.Synthesis
This is the stage where checks for code syntax errors and translating the HDL codes
into device netlist format are done. The translation will be into a complete circuit with
logical elements like flip-flops and logic gates. A net list is generated if there’re more
than one sub designs. The functionality of the design at different points in the design
flow will be verified here. The process also analyzes the design hierarchy which will
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ensure optimization is done for the design architecture according to the designer
selected. The netlists are saved in an NGC (Native Generic Circuit) file format. To
perform this, a synthesis tool (e.g. Xilinx Synthesis Technology or XST) is needed
[34].
2.1.3.Design Implementation
The implementation stage involves three major processes which are Translate, Map,
and Place and Route.
2.1.3.1.
Translate
In this process, all the input netlists and constraints are combined into a logic design
file. That information is saved in a NGD (Native Generic Database) file. An NGD
build program is used to perform that. Defining constraints is simply assigning the
ports in the design to the physical elements such as the FPGA pins, switches, and
buttons of the targeted device and also to specify time requirements of the design. All
those information are then stored in a User Constraints File (UCF) using the tools like
Plan Ahead, PACE or Constraint Editor.
2.1.3.2.
Map
The mapping process, divides the whole circuit with logical elements into sub blocks
such that they can be fit into the FPGA logic blocks. This is done by fitting the logic
defied by the NGD file into the targeted FPGA elements, via a Map program. Those
elements are the Configurable Logic Blocks (CLB).That, Input Output Blocks (IOB).
After mapping a Native Circuit Description (NCD) file. In this file, the physical
representation of the design mapped into the FPGA components will reside.
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2.1.3.3.
Alagenthiran S/O Nadeson
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Place and Route (PAR)
In this process, a PAR program is used. This is where the sub blocks from the map
process is placed into logic blocks according to the constraints defined and the logic
blocks in the FPGA is connected. The mapped NCD file is taken by the PAR tool as
input and a completely routed NCD file as output produced. The output NCD then will
have the routing information.
2.1.4.Xilinx Device Programming
In order to load the design into the FPGA chip, the design needs to be converted to a
format so that the FPGA can accept it. A physical connection to the FPGA board such
as the USB cable is needed to perform this. This format is called a bit stream where a
file with a *.BIT extension will be generated. A BITGEN program which performs this
task the takes in the routed NCD file in the earlier process is to generate the bit stream
file in order to configure the target FPGA device. In Xilinx ISE Webpack, IMPACT
tool is provided to perform the programming.
2.1.5.Design Verification
Before the design is finalized it can be verified during, before or after the Synthesis,
Implementation and device programming processes. There are covered in the
subsections below:
2.1.5.1.Behavioural Simulation
Also know as Register Transfer Level (RTL) Simulation, this is the very first
verification step in the design flow hierarchy. This simulation is done before the
Synthesis process to verify the RTL (behavioural code) and to confirm whether the
design is functioning and as what the designer intended. During this process, the
signals, variables, procedures and functions are observed and traced. This process
allows the designer to quickly fine tune the HDL code if the functionality is not met.
At this stage the designer will not know the timing and the resource usage properties
since the codes are not synthesized yet. Simulation tools such as ISIM, ModelSim XE,
PE or SE can be used.
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2.1.5.2. Functional Simulation
After the HDL codes have been translated, a Functional Simulation or Post Translate
Simulation needs to be done using the same tools mentioned in Behavioural
Simulation. This simulation provides information of the logic operation of the circuit
and this is where the designer can verify the functionality of the design rectification
can be done in this stage if the desired functionality of the code is not achieved and
will need to follow through the flow steps again.
2.1.5.3. Static Timing Analysis
This verification can either be done after MAP or PAR processes using Plan Ahead
tool. The signal path delays of the design derived from the design logic is listed in the
Post MAP timing report. The timing delay information is incorporated in the Post
Place and Route timing report to provide a summary of the design.
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2.2.
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Hardware Description Language (HDL)
HDL is basically, any language from a class of computer programming
languages for formal description of electronic circuits or digital logics. The
two widely used HDLs are Verilog and VHDL [23].
2.2.1. Verilog
This HDL is at Register Transfer Level (RTL) and used in design, verification
and implementation of digital logic chips, analogue and mixed circuits. The up
to date version is the Verilog 2005 (IEEE Standard 1364-2005) and there’s
also a superset version, System Verilog [24].
2.2.2. VHDL
The abbreviation of Very High Speed Integrated Circuit (VHSIC) Hardware
Description Language, VHDL is a design- entry language for FPGA and
application specific integrated circuits in electronics design of digital circuits.
The recent version of VHDL is VHDL 4.0, with IEEE 1076-2008 standards.
As its name suggests, VHDL is more for a high speed IC circuit applications.
One major advantage of VHDL is the behavior of the required system is
allowed to be described and verified before the synthesis tools convert the
design into hard wired design [25].
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2.3.Peak Program Meter
In this design, the more appropriate concept to be used in this project is Peak
Program Meter (PPM). The PPM (Figure2.3.1) is an electronic instrument that
is able to measure the loudness or volume of an audio signal [30].
Figure 2.3.1 : Two types of old PPM (mechanical zero on the left and right
hand side restpectively).
PPM is actually a quasi peak (almost or not quite peak) meter which has a
slow integration time of around 5-10ms which was deliberaly design to be in
this timing. This is because PPM could avoid overloads casued by peaks and
ignore fast peaks as the ear could only tolearate distortions lasting for a few
miliseconds.
There are many types of audio level meter available but the most commonly
followed stardards are British and German designs as specified in IEC 6026810 standards. In Britain the, British Boradcasting Corporation (BBC) used a
number methods (0-7) and after many development stages, BBC PPM was set
as a standard, which is BS 6840-10:1991. Which soon adapted by many
countries in the world which then called, IEC 60268-10:1991: "Sound system
equipment. Methods for specifying and measuring the characteristics of peak
programme level meters".
Similarly, the broadcaster in Germany aslo developed PPM independently
from UK and came up with a quasi peak design with fast rise and slow decay
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design which then standardized as DIN 45406. This is more commonly used in
northen Europe and scandinavian countries.
In USA, PPM was rejected in favour of Standard Volume Indicator (VU
Meter) due to cost factor. The VU meter was just 1dB behind the PPM and the
USA researchers believed was good enough and belive that VU meter is a
comercial alternative to PPM.
2.4.
Key Components in sound measurement.
2.4.1.
Pre- amplifier.
In order to amplify a low level audio signal such as pickup, microphone, turntable,
into line level signals, a pre-amplifier (or pre-amp) is needed. This component
provides a voltage gain but not significant current gain [35].
Figure 2.4.1: A low Voltage Microphone Pre-amplifier circuit [36]
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2.4.2.
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Compandor
Companding (Figure 2.4.2) is a process in signal processing that mitigates the
detrimental effects of a channel with limited dynamic range. There’s an electronic
component that can per form this process called a compandor.
Figure 2.4.2: The Differences of an analogue signal before and after companding.
In audio recording, the dynamic range of a signal is compressed before transmission
and is expanded to the original value at the receiver. In this project an analogue
electronic signal such as sound is used [37].
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2.4.3.
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Analogue to Digital Converter.
The audio signal from microphone will be of analogue format. Therefore, a conversion
to a digital format is needed as the FPGA is a digital electronic chip. Therefore an
Analogue to Digital Converter (ADC) component is needed. This component will
convert a continuous signal to discreet digital numbers [38].
ADCs have resolution which is the number of the discreet values that it can produces
over a range of analogue values. For example, For a Full scale measurement range of
0 to 10 volts, if the ADC resolution is 12 bits (212 = 4096 quantization levels (codes)),
the ADC voltage resolution will be (10V - 0V) / 4095 steps = 10V / 4095 steps
0.00244 V/step
2.44 mV/step [38].
2.5. Audio Level in Decibels: 10 log Rule and 20 log rule
To measure a sound pressure level, a logarithmic unit (base 10) that expresses the
magnitude of a physical quantity (usually power or intensity) relative to a specified or
implied reference level is used. The term used for this measurement unit is called
Decibel (dB).
To measure power quantities like power or intensities, the following Formula 1 is used:
Formula 2.5a: Power dB (10 log rule)
L represents the ratio of a power value P1 to another power value P0, and then LdB
represents that ratio expressed in decibels. However, to measure the Field Quantities
(e.g. amplitude, voltage), the below Formula 2 is used.
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Formula 2.5b: Voltage dB (20 log rule)
Where A0 is reference amplitude and A1 is measured amplitude.
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2.6. Previous Works of Audio Meters using FPGA
2.6.1. DPLCM Project based on Altera Cyclone 2.
This project, Digital Peak Level and Correlation meter (DPCLM) was done by
an FPGA enthusiast which is quite similar to this project but using Altera
Cyclone 2 development board and various different approaches [26]. The
designer of this project was using different audio source, which is a Sony
Philips Digital Interface or more commonly referred to as S/PDIF source into
the FPGA board. The designer has done a lot of higher level arithmetic
calculation by using advanced VHDL programming. The program will take in
the digital audio signals and display the peak level, A&B channel correlation
and the sampling rate on several seven segment LEDs and also on a large set
of LEDs in a bar display. The peak level will display the peak audio level of
the signal. On top of that he also did a lot of electronics prototyping by
designing his own I/O interface board to be connected to the FPGA board. He
has also made an improvement to his work by displaying on the Vacuum
Fluorescent Display (VFD) which is commonly used in consumer electronics
products (e.g. car audio player, microwave oven, etc) [27]. Comparing to my
work, he is taking a preprocessed 2 channel digital stereo signal.
2.6.2.
Digital Level Meter Based on Xilinx Spartan 3E
Similar to the above design, this was done using Spartan3E dev kit, and using
just a bar LED display no calculation was involved. [29]
2.6.3. Audiometer Using LabView FPGA.
National Instruments’ LabView FPGA software also could be used to design a
simple audio meter. As this is more a graphical user interface (GUI) method of
design on FPGAs. Another approach of FPGA design but the software needs
to be purchased a cost [46].
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CHAPTER THREE
DESIGN
3.1. Hardware Selection:
3.1.1.FPGA Development Boards and Kits
For industry level or research applications, FPGA development has become
easier when the two major FPGA chip manufacturers namely, Xilinx and
Altera have been designing FPGA Development boards or kits. These boards
and kits provide the end users or developer to have an integrated design boards
which cater most of the electronic accessories on board. In addition to that,
they also provide design tools (software) [20].
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3.1.1.1.Xilinx
At Xilinx there are quite a number different boards and kits available from
Xilinx and partner companies. The two main categories are Spartan family and
Virtex Family. Spartan boards and kits are ideal for entry-level developments
and applications. As compared to Spartan, Virtex boards and kits are more
suitable for high-end performance systems. In summary, comparing the
functions, specs and costs, the more suitable boards for are of Spartan-3 Series
[21]. One good board to consider is Spartan3A (Figure 3.1.1.1a) and another is
the Spartan3E (Figure 3.1.1.1b) where both have analogue capture circuit and
accessories header I/O port and a miniature stereo jack (3.5mm).
3.5mm
stereo
output jack
Analogue
Capture I/O
port
J18/J19/J20
Header pins
for
accessories
like PMOD
MIC.
Figure 3.1.1.1a: Spartan-3A Development Board
Analogue
Capture I/O
port
J1/J4/J2
Header pins
for
accessories
like PMOD
MIC.
Figure 3.1.1.1b: Spartan-3E Development Board
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3.1.1.2.Altera
In contrast to Xilinx’s two, Altera has three different FPGA chip
families, Arira, Cyclone and Stratix. Altera also development kits both
from them and Partner companies. In summary, there are many audio
video, Digital Signal Processing (DSP), embedded systems and also
FPGA development boards and kits available. The more suitable
development boards are of different range. To best suit the cost,
function and specs, Cyclone II FPGA Starter Board (Figure 3.1.1.2)
can be considered. This board specifically has the microphone input
jack readily available. Comparing Xilinx there’s a need to get another
microphone interface I/O card. Another difference of this board from
Xilinx is the display panel is a 7-segment LED display compared to
Xilinx’s LCD panel.
Figure 3.1.1.2: Altera’s Cyclone II FPGA Starter Board.
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3.1.2 Decision Matrix
A list of FPGA development kits and the key factors were taken into consideration
before selecting the boards.

Cost

Memory Size

Clock Speed

Display & Indicators

Connectors

Analog Interface

Support & Resources
To select the appropriate evaluation boards and other peripheral hardware, a decision
matrix [39] was used (Table1). A ranking of 1-10 with 10 is for the best is given. The
weights for the factors are then given according to the importance (1-100%). The total
score is calculated by the multiplying each ranking with their corresponding weights
followed by the summing up each columns for each of the boards.
Score
Factors
Total
Cost Size & Speed & Switches Display& Connectors Analog Support & Score
Memory Clocks
Indicators
Interface Resources
Weight
30%
5%
3%
2%
5%
10%
10%
Spartan 3E
6
10
8
10
8
8
8
Spartan 3A
3
10
8
10
8
8
8
Cyclone 2
10
5
10
8
5
8
10
Table3.1.2: Decision Matrix to choose the 3 different boards available.
30%
8
10
3
95%
7.14
6.84
6.66
In overall Xilinx boards are preferred due to the resources and technical support
available and the loaning service provided by Singapore Polytechnic out of good will.
After calculating the total score Spartan 3E was chosen first it is available first
followed by 3A. But there’s a need to purchase an additional peripheral microphone. In
contrast if budget was allocated, Altera board will be preferred as it has a better audio
codec chip and preferred board by FPGA experts for audio prototyping.
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3.1.3. Microphone Selection
There are three different types of microphones available:
 Dynamic microphones: An ideal one for general purpose with simple design with
few moving parts and is sturdy and resilient to rough handling. This type of
microphones are more likely suitable for handling high volume (e.g. from musical
instruments or amplifiers). They have no internal amplifier and do not require
batteries or external power.
 Condenser microphones: This type of Microphones requires power from a battery
or external source (called "phantom power"). The audio signal out from the
microphone is stronger signal than that from a dynamic. They are also more
sensitive and responsive than dynamics, making them well-suited to capturing
subtle nuances in a sound. However, they are not ideal for capturing high volume
as the high level of sensitivity makes them prone to distortion. A condenser simply
means capacitor, where energy is stored in the form of an electrostatic field. This
type of microphone, which uses a capacitor to convert acoustical energy into
electrical energy.
 Electret condenser microphone: This microphone uses a special type of
capacitor which has a permanent voltage built in during manufacture. Like a
permanent magnet, in that it doesn't require any external power for operation.
Therefore a power source (e.g. a battery or “phantom Power” is not required. The
other feature is the same as a normal condenser microphone.
The selection of the suitable microphone depends on the criteria [31, 32] below:
3.1.3.1. Sensitivity: This determines how much voltage is generated per units sound
pressure level (mV/Pa). A more sensitive microphone of 50 or 100Mv/Pa normally
large) is required if there’s a need to characterize lower level sounds. For louder sound
like jet aircraft, a less sensitive microphone is sufficient.
3.1.3.2. Frequency range: the audible range is 20 to 20 kHz and many microphones
extend well beyond this.
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3.1.3.3. Signal Conditioning Requirements: This refers to the external power
requirements of the microphones. A common type is the IEPE (Integrated Electronic
Piezoelectric) as know as ICP, Isotron, and Deltatron. These microphones require a
low-level DC current to power an on-board preamplifier in the microphone housing.
3.1.3.4. Directionality: To decide which suitable directional pattern that the
microphone works. There are three types:
 Omnidirectional: All directions.
 Unidirectional: One direction
 Bidirectional: Two opposite directions.
3.1.3.5. Frequency Response: Normally, flat response patterns are best, but in many
cases a tailored response will be even better.
3.1.3.6. Impedance: Low impedance is better than high impedance.
3.1.3.7. Handling Noise: A microphone is likely to be subjected to any sort of
handling noise or vibration. It is desired to have a microphone which prevents
unwanted noise from being picked up. High quality hand-held microphones usually
attempt to isolate the diaphragm from vibrations using foam padding, suspension, or
some other method. Low quality ones tend to transfer vibrations from the casing right
into the diaphragm, resulting in a terrible noise.
As there are a huge variety of microphones available, a suitable one in terms of
hardware also needs to be considered. This one is particularly the connectors. For
FPGA prototyping boards, the suitable ones are 3.5mm jack (Figure 3.3.2a)
incorporates into stereo headphones and mono microphones [32] which is also the one
that most computers (PC) and Notebook Computers are having.
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Figure 3.1.3.7: A 3.55mm Audio Jack.
A readily available PC microphones like SOUND MAX SUPERBEAM. As
mentioned in earlier section this jack is easily able to inserted into Altera’s Cyclone 2
evaluation kit but not so simple for Xilinx.
If this microphone were to be used on Xilinx Boards, there’s a need to perform a
modification on the 3.5mm jack where an additional connector is needed and two
wires (+/ -) will need to be connected into the analog input connection of the FPGA
Boards.
3.1.4. PMOD MIC
Knowing and going through all those above selection criteria, the decision to
choose the suitable microphone was made simple by DIGILENT as there is a
preinstalled microphone a peripheral board for FPGA prototyping boards
comes with a very low cost of S$25. This I/O interface board called PMOD
MIC (Figure 3.3a) has been specifically designed for use with DIGILENT and
XILINX development kits which will work on an SPI interface via a 6
accessories header pins I/O peripheral ports (i.e. J1/2/J4 on Spartan3E and
J18/J19/J20 on Spartan3A).
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
Figure 3.1.4a: PMOD peripheral module board with microphone for
Spartan3A or 3E boards [25].
This board consists of an analogue microphone, an SA575DTB IC which is a
compandor chip and ADCS7476 chip which is an Analogue to Digital Converter
(ADC). The Compandor IC is connected as an Automatic Level Configuration (act as a
pre-amplifier) and the ADC converts the analogue volts into 12bit digital code. The
ADC takes the supply voltage as the reference voltage therefore the max output in
decibels will be 0dB. By using the PMOD MIC as the analogue interface, the internal
Spartan3A/3E analogue capture circuit is not being used. The design will be much
simpler when using a direct digital input to the FPGA where the on board analogue
capture circuit on Spartan 3A and 3E boards can be bypassed. The block diagram of
PMOD microphone can be illustrated as in Figure3.3b below:
Figure 3.1.4b: PMOD MIC Block diagram takes in analog sound through
microphone and outputs a digital sound signal.
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3.2. Software Selection
The selection of software is quite straight forward as they go by which manufacturer
the designers select. As we have selected Xilinx boards, the evaluation version of
Xilinx’s ISE Webpack is selected. For the synthesis and simulation tools, the software
package comes with XST ISIM respectively. However, there’re options to use
evaluation version of ModelSim XE for simulation for limited period of time. Since
cost is constraint. The free software is used. Since the starter kit was and older one
therefore, the development are started from the older software Webpack ISE 8.1 (latest
was 11.1). The plan was when the evaluation period expires, will decide to upgrade
every 3 months). The final design was made with 11.1 versions.
3.3. Design Procedures (Block Diagrams).
3.3.1 Initial Design: Audio Meter Design using FPGA (Revision1)
The FPGA needs to be programmed in order to produce the output
corresponding to the analogue input level from a microphone. During the
research period, the block diagram of an Audio Meter using FPGA was
proposed. The diagram shows some fundamental concepts in different blocks
below in Figure 3.3.1:
Figure 3.3.1: Initial Concept of Audio Meter design using FPGA (Revision1).
Keeping in mind that the different CLBs in the FPGA chip, the appropriate HDL
codes planned to be written to design the FPGA chip to generate the output correctly.
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As most of the designs using FPGA done we using LEDs and 7-segment LED
displays, this project will explore on the display on LCD module.
3.3.2.
Audio Meter FPGA using Voltage Averaging, Floating Point and Logarithmic
Calculators (Revision2).
After extensive research and understanding the basic block diagram was redesigned
and new approach was taken to develop the Audio Meter. In this design, a real time
calculation of the audio sound level will be achieved. The revised block is as per
below:
FPGA
PMOD MIC
Converting to dB
Voltage Averaging Ckt.
Microphone
`
20 *Log (VRMS)
V*V
12x12
Multiplier
Pre-amp
Logarithm
Circuit
Multiplier
by20
ADC (12 bit)
Clock converter
(50 to12.5MHz)
Divide period of time
12 bit divider
Display (8bit)
Clock converter
(50 to12.5MHz)
Convert to BCD (4bit data, 3bit signal)
Sqrt
dB
value
Counter 4-bit
Finite State
Machine
Other Text
(e.g. reading
is __dB)
VRMS
LCD
Figure 3.3.2: Audio Meter design using Voltage Averaging, Floating Point, and
Logarithmic Calculations (Revision2).
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In this revision, the design will be using the PMOD MIC peripheral board input to the
Spartan 3E and 3A FPGA boards. In this design there are three major blocks.
3.3.2.1.PMOD MIC Block
This block will need to be programmed to accept the analog audio signal from the
microphone to go through the pre-amp and finally to convert the Analog signal into a
12 bit digital data signal. The PMOD MIC board needs to be powered with a supply
voltage of minimum 2.7 V to maximum 5.25V. From the J1 and J18 peripheral board
a 3.3V and GND is pre routed and ready for use without programming. For the ADC,
there’s a need to input a 12.5MHz (max. 20MHz) to clock input. This is where the 50
MHz clock supply on Spartan 3E and 3A boards will be divided and supply back to
the input. Next is the chips select signal (low) which will inform the ADC to perform
conversion once there’s logic 0. Those are the physical Input/ output (I/O) connection
required. [44]
Figure 3.3.2.1. ADC Connection Diagram (left) and Block Diagram (right).
3.3.2.2.Voltage Averaging Circuit Block.
In this block, the FPGA needs to be programmed to take in the digital ADC codes and
perform some averaging in order to determine the average voltage level over the
continuous signal (Formula 3.3.2.2). In the case of a set of n
values
, the RMS value is given by:
Formula 3.3.2.2: VRMS Calculation [40]
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Since the data is a 12 bit digital data, 12 bit multipliers, adders, dividers were
required. There’s also a need to determine the coding for square root function. And
possibly a floating point units is needed as there will be decimal point involved.
3.3.2.3. dB Conversion Circuit Block:
In order to display the value in dB there’s a need to use the 20 log rule. The result of
the Voltage Averaging Circuit is then divided by the reference voltage (ADC’s, i.e.
VDD) then perform a logarithm function followed by a multiplication of 20.
3.3.2.4. Display Block:
The display block will then take in the logarithmic value in dB and print on the
screen. In order to perform this, the digital codes need to be converted to an
equivalent Binary-coded Decimal (BCD) format then sent in to the LCD. Then the
initializes and the command is send first to display on the starting addresses (location
of the first alphabet) on the characters to be printed followed by the LCD
CHARACTER CODE of the alphabet. For Spartan 3E, the data signal will 4 bit data,
therefore the signal need to be send 4bit by 4 bit. Optionally, other alphabets can be
printed onto the screen.
However, the Revision 1 design was dropped due to complexity of the design and
short time duration was available. The division and multiplying was not as difficult
but time was consumed to look for logarithm function in VHDL and also in floating
point.
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3.3.3. Audio Meter FPGA Using Programmable Memory (Revision3).
This is the final revision of the design (Figure 3.3.3.) where the values of the dB are
pre-calculated and stored in Read Only Memory (ROM) a Look up table Concept
(LUT).
Figure 3.3.3: Audio Meter FPGA using Programmable Memory Block Diagram
(Revision3)
If compared to Revision1 block diagram, the newer version has 4 new blocks
introduced:
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3.3.3.1. LCD ROM Block:
Also an IPCORE block, this is a distributed memory with ROM configuration. When
data reading comes in to the input, the ROM recognizes it as an address and will
output the corresponding value stored in the address (the pre-calculated dB value in
LCD Character code). This is done by writing the values in binary format in a file
(*.coe format) when generating this IP core. The values stored are as per Table2
below:
Characters to be written (dB)
LCD Character code (for three digits )
3 spaces for Reset or No Reading
00100000 00100000 00100000
-80
00101101 00111000 00110000
-70
00101101 00110111 00110000
-60
00101101 00110110 00110000
-50
00101101 00110101 00110000
-40
00101101 00110100 00110000
-30
00101101 00110011 00110000
-20
00101101 00110010 00110000
-10
00101101 00110001 00110000
0 (two spaces and 0)
00100000 00100000 00110000
Table 3.3.3.1: LCD Character to be written in ROM (*.coe file)
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3.3.3.2. LED ROM Block:
Similar to LCD block, the 8 bit binary numbers to light up the LEDs will be stored in
a file (*.coe format ). When the reading is -70dB, “10000000” data will be read and
only LED7 will light up. When 0dB, “11111111” data will be read and all 8 LEDs
will light up. All the possible values on the 10dB scale and the LED codes are shown
in Table3.
dB Values
LED code (“1” ON, “0” OFF)
Reset or No Reading
00000000
-70 (including -80)
10000000
-60
11000000
-50
11100000
-40
11110000
-30
11111000
-20
11111100
-10
11111110
0
11111111
Table 3.3.3.2: LED codes to be written in ROM (*.coe file)
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3.3.3.3. LCD Controller Block
This block is a but more simpler than Display block in the previous design there’s no
need to convert to BCD numbers as the LCD characters are already being written in to
the ROM. And for Spartan3A, a straight 8bit data can be written to the LCD. The
LCD will be initialized with command and the permanent characters (Figure to be
displayed are mapped on a state machine design.
AUDIO METER
READING=
dB
Figure3.3.3.3: LCD Display for permanent characters.
However, the three variable characters will be mapped to the ROM and will be
displayed between “=” and “dB”.
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3.3.3.4. PMOD MIC block:
The function of this block is not changed from previous revision. The connection
diagram from PMOD MIC board to Spartan 3A and 3E are shown in Figure 3.2.1.3.4
below:
Spartan 3E board
PMOD MIC board
Spartan 3A board
PMOD MIC board
Figure 3.3.3.4: Connection Diagrams from Spartan3A and 3E to PMOD MIC board.
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3.4. Decibel calculation
The calculation was done as per the ADC datasheet requirements. The 12-bit ADC
code is taken into as the analog input voltage and the reference voltage (Vref) is the
supply voltage (or VDD). In a 12-bit ADC resolution, 4096 codes that can be
generated (0 to 4095 or 000000000000 to 111111111111 in binary). To calculate the
voltage per step of the Least Significant Bit (LSB) can be derived from Formula 4
[41] below:
The LSB step width for the ADCS7476 is as per below:
1LSB = VDD / 4096
Formula 3.4a: LSB Calculation [41]
Figure3.4: ADC code corresponding to the input voltage
In this case the Spartan 3A and 3E boards provide a supply voltage of 3.3V to the
PMOD board. Therefore, VDD = 3.3V,
o Using Formula4 1LSB = 3.3V/4096= 0.00080566V.
o The first ADC code with real value is “1” or 000000000001.Therefore the
calculation will be as follows:
0.5 *LSB= 0.5 *0.00080566V=0.00040283V
o After all this calculation is done the next value “2” will increment by
1LSB and so on till 4095.
o When the ADC code is equals to 4095 or 111111111111 (12bit), the
corresponding analog voltage calculation should be :
1.5LSB = 3.3V-(1.5x 0.00080566V) = 3.2988V
o For the logarithmic calculation, Formula 2.5b explained in Chapter 2.5 can
be applied to derive Formula 5:
Voltage dB= 20*log (Vin/Vref) = 20*(Vin/VDD)
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Voltage dB = 20* log (Vin/3.3V)
Formula 3.4b: Voltage in dB
o From the above explanation, the calculation for ADC code “1” or
000000000001 will be:
o Voltage dB = 20*log (Vin/3.3V) = 20*log (0.00040283V /3.3V) = 78.27dB ~ -80dB.
o For ADC code “4095” or 111111111111 the dB value will be:
o Voltage dB = 20*log (Vin/3.3V) = 20*log (3.2988/3.3V) = 0dB (Full
scale).
As there are too many values to be computed, the data are being computed in an Excel
sheet attached APPENDIX D in rounded to the nearest 10dB. Then there’ll be just
very few information to store. This is done to simplify so that the repetitive values
could be avoided. From observation, the LSB step is very small. Therefore, the
accuracy for each ADC code up to decimal point is not expected for this project. The
decibel values for the range of codes are as per Table 4 below:
ADC Code dB value
0
No Value
1
-80
2
-70
3 to 8
-60
9 to 24
-50
25 to 77
-40
78 to 244
-30
245 to 772
-20
773 to 2440
-10
2441 to 4095
0
Total Code:
Count
1
1
1
6
16
53
167
528
1668
1655
4096
Table 3.4: ADC codes and their corresponding values to be set.
The rounding off is done to the nearest 10 or 0. Where 0 to 4 will be logged in as 0
and 5 to 10 will be 10.
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CHAPTER FOUR
DESIGN CONFIGURATION AND SOFTWARE DEVELOPMENT
4.1. FPGA Board Configuration
Before downloading the bitstream file to program the FPGA on the Xilinx Evaluation
boards, a decision need to be made on which configuration mode that the boards that it
should operate. The more commonly used is the Master Serial mode. This can be done
by putting on the appropriate jumpers on the boards (Figure 4.1a and 4.1b).
Figure 4.1a: Jumper J30 settings for Master Serial Mode on Spartan-3E board. [43]
Figure 4.1b: Jumper J26 & J46 settings for Master Serial Mode on Spartan-3A board
[43]
In this mode the bitstream can be downloaded into the FPGA via the on-board USBJTAG and provides an in-system programming the on-board Platform Flash PROM
(Xilinx XCF04S) to store the image.
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4.2. VHDL programs
As explained in Chapter 3.3, the codes for different blocks in Revision 2 design the
VHDL codes are written into the following filenames.
 PMODMic.vhd
 LCD_ROM.xco
 LED_ROM.xco
 LCD_Controller_al.vhd
All of the different programs are connected through a top level design called
Audiometer_toplevel.vhd file. The detailed codes are provided in APPENDIX A.
4.2.1. Audiometer_toplevel.vhd
This program basically links the entire component block and also includes the LED
Display and the sampling codes. The Block Diagram to show all the connections in the
top level module is illustrated below:
Figure 4.2.1: Audiometer_toplevel.vhd block diagram.
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4.2.2. PMODMic.vhd
This program incorporates the Moore State Machine and a clock divider.
This program has four inputs and outputs. The signals are explained in the Table 4.22
below:
Signal
I/O
Name.
Type.
CLK
Input
RST
Input
SDATA Input
Source.
No. of Function
Bits
Spartan-3E/3A 1
To supply to the clock divider process to
board
which results in 12.5MHz (SCLK) signal.
Spartan-3E/3A 1
To reset the operation. State will go to Idle
board
mode.
PMOD MIC
16
board
This is the analog data information taken
in from Compandor which is coming from
the Microphone.
When there are 4 leading zeroes, the
following 12bits will be read as data for
conversion.
START Input
Program
1
To inform the program when to start a
conversion.
SCLK
Output Program
1
This is the 12.5MHz result from the clock
divider process to clock the ADC.
DATA
Output Program
12
In the SDATA signal, when there are 4
leading zeroes, the following 12bits will be
read as data for conversion. DATA is the
12 bit signal that will supply to other
VHDL Component.
nCS
Output Program
1
The active low ship select signal to turn on
the ADC.
DONE
Output Program
1
To tell the program that a conversion is
completed and wait for the next data.
Table 4.2.2: Signal Naming in PMODMic.vhd program.
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In this program, the state machine comprises of three states, Idle, Shit-In and Sync
DATA. The Idle state is the beginning state where nCS and DONE will be 1. When
START signal is set to one, the State will now enter Shift In mode where nCS and
DONE will be 1. A counter will count till 15 to serially shift in the 16 bits SDATA
information from the microphone through the compandor. When the counter hits 15,
the 12 bit information from SDATA signal (MSB to LSB) will be captured into DATA
and output from ADC. At this point of time nCS and DONE signals will turn to 1 to
disable the ADC and tell the program that a conversion is completed. The START
signal will then become 0 and the finite state machine will go into Idle state again. In
any point of the state the RST button is pressed, the state will go into Idle.
This program was designed to meet the timing requirements [44] in the ADC
datasheet.
Figure 4.2.2: Timing diagram for ADCS7574 ADC chip on PMOB MIC board.
In addition, the 12.5MHz clock pulse for ADC was also created using the Digital
Clock Module (DCM) in a file named DCM_12_5_CLK.xaw. This feature replaces the
clock divider process.
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4.2.3. LCD_ROM.xco
As is this a Xilinx Core component a graphical user interface will let the designer to
select the intended requirements. A distributed memory type was chosen as to save
resources. The memory type chosen was a single port ROM with a 12 bit resolution
which will create an input (a) and a 24 bit output data (spo). The 24 bit data (8bit per
character) contains the addresses of the ASCII 3 characters of the dB values (e.g. 70dB) LCD Character Set (Figure 4.2.3). The ROM is filled with all the dB values for
4096 ADC codes will be written into a file named LCD_COE_file.coe.
Figure 4.2.3: LCD Character Set [42, 43].
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After the IP core is generated, the component is then instantiated and port mapped into
the respective ports in the top level program. The input is mapped to DATA signal
from PMOD MIC and the output is to ASCII code signal.
4.2.4. LED_ROM.xco
To display the LED, a ROM with the same configuration was used. The data is filled in
a filed named LED_ _COE_file.coe. The 12 bit input (a) is mapped to DATA signal
from PMOD MIC and the output is to the 8 bit LED output.
4.2.5. LCD_controller_al.vhd
To program the LCD an initialization need to be done so as to inform the component to
work on user specified behaviour [42, 43]. The two main signal involved in controlling
the LCD module are control and sf_d. Control is a three bit signal mapped to (MSB to
LSB) LCD_RS, LCD_R/W and LCD_ E,. While sf_d is an eight bit command or data
signal. The explanation for the signals’ definitions and functions are in Table 4.25a.
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Signal Generic Signal Name Type
Name
in Program
LCD_DB<7>
sf_d ,<7>
Description
Remarks
Data bit 7
-
Data or
Instruction
Data or
Instruction
Data or
Instruction
Data or
Instruction
Data or
Instruction
Data or
Instruction
Data or
Instruction
Data bit 6
-
Data bit 5
-
Data bit 4
-
Data bit 3
When using the four-bit
interface, drive these
signals
Control
Register Select
Data or
Instruction
LCD_DB<6>
sf_d ,<6>
LCD_DB<5>
sf_d ,<5>
LCD_DB<4>
sf_d ,<4>
LCD_DB<3>
sf_d ,<3>
LCD_DB<2>
sf_d ,<2>
LCD_DB<1>
sf_d ,<1>
LCD_DB<0>
sf_d ,<0>
LCD_RS
Control<2>
Data bit 2
High.
Data bit 1
Data bit 0
-
0: Instruction
register during
write operations.
Busy Flash during
read operations
1: Data for read or
write operations
LCD_RW
Control<1>
Control
Read/Write Control 0: Write, LCD
accepts data
1: Read, LCD
presents data
LCD_E
Control<0>
Control
Read/Write Enable
Pulse
0: Disabled
-
1: Read/Write
operation enabled
Table 4.25a: Signal Naming in LCD_controller_al.vhd program.
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To summarize the 3 bit Control signal, Table 4.25b will show the function of the 3 bits
combination used in this program.
Control (2:0)
Function
000
Disable LCD
001
Instruction, accept data and enable display
110
Data, accept data, disable display
101
Data, accept data, disable display
Table 4.25b: Control Signal combinations
As a general guideline the below method is used [42, 43]:
 Power-On Initialization
The initialization sequence first establishes that the FPGA application wishes to use
the four-bit data interface to the LCD as follows:
1. Wait 15 ms or longer, although the display is generally ready when the FPGA
finishes configuration. The 15 ms interval is 750,000 clock cycles at 50 MHz.
2. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
3. Wait 4.1 ms or longer, which is 205,000 clock cycles at 50 MHz.
4. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
5. Wait 100 s or longer, which is 5,000 clock cycles at 50 MHz.
6. Write LCD_DB<7:4> = 0x3, and pulse LCD_E High for 12 clock cycles.
7. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz.
8. Write LCD_DB<7:4> = 0x2, and pulse LCD_E High for 12 clock cycles.
9. Wait 40 s or longer, which is 2,000 clock cycles at 50 MHz.
 Display Configuration
After the power-on initialization is completed, the four-bit interface is established.
The next part of the sequence configures the display:
1. Issue a Function Set command, 0x28, to configure the display for operation on the
Spartan-3A/3AN Starter Kit board.
2. Issue an Entry Mode Set command, 0x06, to set the display to automatically
increment the address pointer.
3. Issue a Display On/Off command, 0x0C to turn the display on and disable the
cursor and blinking.
4. Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock
cycles) after issuing this command.
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4.2.6. Audiometer_toplevel.ucf
In this file the physical I/O signals on the FPGA is then mapped to the corresponding
pins names. The PMOD MIC board is mapped to the peripheral I/O port J1 (for
PSartan3-E) and J18 (for Spartan3A). LED signal name to the discreet LED
component, sf_d to the data input of the LCD and the Control signals to LCD_E,
LCDRS and LCD R/W of the LCD Module. For testing purpose, START signal from
PMOD MIC was assigned to a pushbutton (EAST). The RST also assigned to
pushbutton (West) [42, 43].
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CHAPTER FIVE
RESULTS & SIMULATION
5.1 Software Simulation
The simulation of the design initially was done on block level, followed by the top
level design. The simulation attached in APPENDIX
5.1.1. Spartan3A_MIC_tb.vhd
The Initial block PMODMic.vhd was tested using a simulation code where it
manually will mimic the 50MHz FPGA Clock (CLK) and outputs 12.5MHz (SCLK
signals), leaving chip select (nCS to low ) to allow ADC conversion (toggling to 1
also tried) and then sending in the SDATA signal (mimicking the Microphone
reading) and send into the ADC. The Major block which has the program and
command to operate the ADC was tested using ISIM simulation software and below
are the results:
CLK Period
=20000ps or
=50MHz
SCLK Period
=80000ps or
=12.5MHz
START =1
nCS =1
DATA =
Undefined
(no decode
pattern yet)
Figure 5.1.1a: Simulation Results Showing the signals (FPGA clock (CLK),
divided clock signal (SCLK), START, chip select (nCS) and the initial ADC’s
output signal (DATA)).
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Next will be the diagram showing the output signal after manually sending in a
serially shifted in data through SDATA signal “111111111111” indicating the
full level ADC code followed by another random number “000111111111”.
This was done by sending in a four leading zeroes to signal the program to
capture the next 12bits of DATA bits (for 16 clock cycles). The DONE signal
will become 1 and the 12 bits is captured into the DATA. The output can be
clearly seen at the DATA for the two sets of numbers.
After the 4leading zeros and 12 other bits per SCLK clock, the
output decode are achieved, with all the other conditions
(START=1, nCS=0)
DONE=1 after 16bits of
valid bit patterns being
captured.
1st Decoded
DATA=111111111111
2nd Decoded
DATA=000111111111
Figure 5.1.1.b. : Simulation Results Showing the signals (FPGA clock (CLK),
divided clock signal (SCLK), START, chip select (nCS) and the ADC’s output
signal (DATA) 1st and 2nd value, DONE signal).
5.1.2. LCD_controller_al_tb.vhd
The program was the words as expected on the FPGA Boards’ LCD panel, except the
converted value of the sound. Issue continued to debug.
5.1.3. LCD_ROM.xco & LED_ROM.xco
These IPCOREs are pre-tested programs by Xilinx therefore it was not necessary to
test them again.
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5.1.4. Audiometer_toplevel_tb.vhd
After the verification of the individual blocks, the top level program also needs to be
verified. But at this point of time the program was not working.
5.2. Testing on Hardware
5.2.1 Actual Testing on FPGA.
Spartan-3A, PMID and the notebook computer is connected Below figure is the
prototyping environment set up (Figure 5.1.2a).
Figure 5.1.2a: Prototyping Setup for Programming and testing.
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The program was then downloaded on the FPGA using IMPACT software (Figure5.2.1b).
Figure5.2.1b: Downloading the audiometer_toplevel.bit (bitstream) file on to the FPGA.
The results observed on the LCD displayed were correct for the permanent display
characters set (Figure5.2.1c).
Figure5.2.1c: Result of the Permanent LCD Character from the program.
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After the START button (push button SOUTH) was asserted once followed by the
RESET button (push button EAST). The all the 8LED was fully lit (Figure 5.2.1d).
Figure5.2.1d: Result on LCD after START &RESET push button asserted once in
sequence.
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After the START button is asserted the second time LED0 was switched off and when the
RESET button was asserted, character “1” will appear on the LCD screen. Indicating 1dB
(Figure5.2.1e).
Figure5.2.1e: Result on LCD after START & RESET push button asserted the second
time in sequence.
But not the reading of the actual dB values measured from the microphone.
The reset button was working as well. The issue was continued to debug as the START
signal was not appropriately mapped. It was then decided to assign the signal to a loop
process after a few clock cycles to reference the 44.1 kHz audio sampling.
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CHAPTER SIX
CALIBRATION AND FINE TUNING
6.1. Calibration and Finalization.
For calibration, after some research it was found that this can be done using
actual audio mixers available in recording studios or simply can be done via
software. One of the software, Peak Program Meter, is provided by Darkwood
[7]. For the testing and calibration there’s free to use tone generator software
application by Digital Recordings [29] that will generate user configurable
tone. The amplitude and frequency are adjustable.
Before using the VHDL design on Spartan3A board to calibrate, a demo was
done using Peak Program Meter, the WWW frequency generator and a
microphone (Superbeam soundMAX [46]) which is connected to the computer.
The distance of the microphone was adjusted till the expected dB level is
matching with the source. In this experiment a 500Hz signal with -20dB
amplitude was generated and the closest measurement was approximately 20dB (Figure 6.1).
Figure 6.1: Initial Calibration Testing Using WWW DFG Sine Wave
Generator (right) and Peak Level Meter (right)
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CHAPTER SEVEN
CONCLUSION & FUTURE WORK
7.1. CONCLUSIONS
The different FPGA evaluation kits were evaluated and finally design was tried on
Spartan-3E and 3A boards. The development of an Audio Meter using FPGA was
realized. This is discovered through extensive research on the methodologies and
previous work done. The Audiometer Project was concluded with the Revision3 design
results. The VHDL codes are able to be verified using ISIM simulation environment.
As the design is not able to display on the Development Kit, the objective was only
partially met. However, this project will be a guideline to other researchers to learn the
design algorithm and techniques and apply to their own work.
7.2. FUTURE WORK
This project needs to be fine tuned on the codes and timing constraint. A calibration
needs to be done after the behavioural simulation to achieve the final results.
7.2.1. Audio Meter FPGA (Revision 2)
To continue further on this project, the more complicated approach which is the Audio
Meter FPGA (Revision 2) design with the real time decibel calculation proposed in
Chapter 3 can be tried upon. The additional DCM clock with the 12.5MHz speed
created can be tried upon to replace the clock division method in the PMODMic.vhd
program.
7.2.2. IPCORE
Another approach for this design is by choosing and using various IPCOREs to shorten
and simplify the design.
7.2.3. MICROBLAZE 32 bit Soft Processor.
In the Embedded Development Kit (EDK) software there’s a possibility of developing
this project using C++ codes and a combination of HDL. However the XPS software
is a licensed version with a shorter trial period that Webpack ISE. Thus some resources
are needed to purchase the software licence.
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7.2.4.LABVIEW FPGA
An audio meter design can be achieved by using the above software kit [46] provided
by National Instruments using their Virtual Instruments (VI) techniques which are a
faster and simpler approach. But the software comes with high cost too.
7.2.5. International Standards
As mentioned in Chapter 2, the IEC standards can be explored further and incorporated
into this design.
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CHAPTER EIGHT
REFLECTION
Through this project there are a lot of skills being acquired. Those include research,
problem solving, technical report writing oral presentation, design , testing,
evaluation and the more important ones are, Project Management, VHDL
programming, FPGA development stress management. The utmost skill learnt, is
designing the audio measurement it self.
8.1. Project Management
Time management is a key concern when doing a project, especially with UNISIM.
Due to the par time nature of this course, efficient time needed to be allocated to do
the project, other modules and work.
There were a lot of timelines need to be well planned and the urgency of missing
those deadlines set need to be taken very seriously.
8.2. VHDL Programming
As a non programmer, where all my previous work involved in hardware
development, a very big challenge was taken when this project was chosen as it
involved programming. The skills needed to be learned very quickly in order to start
designing. There are a lot of discoveries being made when trying to learn the new
programming language. The where more organized trainings, usually incur cost and
the freely available ones are most of the time conducted during office hours. The
other alternatives are books and online tutorials provided by the FPGA manufacturers
and other experts on video as well. The more practical ones are learning by examples.
8.3. FPGA Development
Learning to develop FPGA really needs a very good in depth understanding of VLSI
circuits. For a beginner like me who did not learn about VLSI circuits, this was quite
difficult and challenging project to start with. After attending a training organized by
Xilinx on FPGA development using Centos (an embedded operating system ), I
discovered that there are more details needed to be considered when developing an
FPGA design and this can be realized when working on higher capability FPGA chip
and kits.
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8.4. Stress Management
In the recent economic crisis major companies had done their restructuring and some
even reduced a number of their staffs. Especially in my situation, all my fellow
colleagues were retrenched and I was spared and posted to another department where
I had to start to learn things all over again. I needed to stay back and learn the new job
well and also manage my studies. In this period of time, where all are asked to clear
their annual leave and take no pay leaved at the company specified dates and receive
pay cuts. Moreover, I also had to bare with my medical treatment costs which needed
frequent rehabilitation session. When the project was chosen and allocated, out of our
surprise there was no budget allocation for a project which was based on hardware
realization by evaluating different development kits available in the market. In this
situation I had used my soft skills which I’ve learned in my work to negotiate with the
school and other alternative sources to make some arrangement to provide the board
for this project. Only after a few months, out of good will my supervisor manage to
loan me one (Spartan-3E) and later stage Spartan-3A. During this period, a lot of
confusion was encountered on where to start and delays where made. But with a
strong determination to complete this Capstone project this stage of project was
achieved. During this project period, I also consulted some elder family members,
lecturers, friends and colleagues regarding the problems encountered and they
encouraged me and guided me to go through the correct path to solve them and
motivated me on not to give up.
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REFERENCES
[1] http://en.wikipedia.org/wiki/Audiometer (Last accessed 24th April 2010).
[2]http://www.discoveriesinmedicine.com/Apg-Ban/Audiometer.html (Last accessed
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[3] http://www.economedical.com.au/product/oscilla-sm930-screeningaudiometer.html (Last accessed 30th July 2009).
[4] http://www.testing1212.co.uk/a.htm (Last accessed 24th April 2010).
[5] http://www.testing1212.co.uk/m.htm (Last accessed 24th April 2010).
[6] http://dictionary.reference.com/browse/meter (Last accessed 30th July 2009).
[7] http://www.darkwood.demon.co.uk/PC/meter.html (Last accessed 30th July 2009).
[8] http://api.ning.com/files/BO3cgrWV*ckZG14Aj-6uk-ZI8x3vV9luAZSgseydWMNxGQ*MLUGZfTsLFzaEIWdVE-FYxzP6qFeMZqifLyMQWcPwOKEPaD/VU_Meter.jpg (Last accessed 30th July
2009).
[9] http://www.electronic-circuits-diagrams.com/audioimages/audiockt14.shtml (Last
accessed 30th July 2009).
[10] http://centertek.trustpass.alibaba.com/product/11942229100000121/Data_Logger_Sound_Level_Meter.html (Last accessed 30th July 2009).
[11] http://en.wikipedia.org/wiki/Loudness_monitoring (Last accessed 30th July
2009).
[12] http://en.wikipedia.org/wiki/VU_meter (Last accessed 23rd April 2010).
[13] http://www.caban.nl/outside_broadcast.html (Last accessed 30th July 2009).
[14] http://en.wikipedia.org/wiki/Sound_level_meter (Last accessed 30th July 2009).
[15] http://www.audiofile-engineering.com/support/manuals/sp/1/online/ch08s02.html
(Last accessed 30th July 2009).
[16] http://www.free-electronic-circuits.com/circuits/audio-level-meter.html (Last
accessed 30th July 2009).
[17] http://wiredworld.tripod.com/tronics/audio_level.html (Last accessed 30th July
2009).
[18] ttp://www.datasheetcatalog.com/datasheets_pdf/B/C/1/0/BC108B.shtml (Last
accessed 30th July 2009).
[19] http://en.wikipedia.org/wiki/Field-programmable_gate_array (Last accessed 3rd
August 2009).
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Alagenthiran S/O Nadeson
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[20] http://www.xilinx.com/products/boards_kits/index.htm (Last accessed 3rd
August 2009).
[21] http://www.altera.com/products/devkits/kit-dev_platforms.jsp (Last accessed 3rd
August 2009).
[22] http://en.wikipedia.org/wiki/Hardware_description_language (Last accessed 3rd
August 2009).
[23] http://en.wikipedia.org/wiki/Verilog (Last accessed 3rd August 2009).
[24] http://en.wikipedia.org/wiki/VHSIC_Hardware_Description_Language (Last
accessed 3rd August 2009).
[25]
http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,401,517&Prod=PMODMIC (Last accessed 5th August 2009).
[26] http://www.beis.de/Elektronik/DPLCM/DPLCM.html (Last accessed 1st
February 2010).
[27] http://en.wikipedia.org/wiki/Vacuum_fluorescent_display (Last accessed 23rd
March 2010).
[28] http://members.optushome.com.au/jekent/FPGA.htm (Last accessed 23rd April
2010).
[29] http://www.digital-recordings.com/www-instruments/www-slm/slm_help.html
(Last accessed 24th April 2010).
[30] http://en.wikipedia.org/wiki/Peak_program_meter (Last accessed 8th May,
2010).
[31] http://digital.ni.com/public.nsf/allkb/81524737B762B14186256EBC007A1689
(Last accessed 8th May, 2010).
[32] http://www.mediacollege.com/audio/microphones/choosing.html
(Last accessed 8th May, 2010).
[33]
http://www.xilinx.com/itp/xilinx8/help/iseguide/html/ise_fpga_design_flow_overview
.htm (Last accessed 11th May, 2010).
[34] http://www.vlsi-world.com/content/view/28/47/1/2/ (Last accessed 11th May,
2010).
[35] http://en.wikipedia.org/wiki/Preamplifier (Last Accessed 11th May, 2010).
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ENG499 CAPSTONE PROJECT REPORT
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Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
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[36] http://electroschematics.com/865/low-voltage-microphone-preamplifier/ (Last
Accessed 11th May, 2010).
[37] http://en.wikipedia.org/wiki/Companding (Last Accessed 11th May, 2010).
[38] http://en.wikipedia.org/wiki/Analog-to-digital_converter (Last Accessed 11th
May, 2010).
[39] http://rfptemplates.technologyevaluation.com/What-is-a-Decision-Matrix.html
(Last Accessed 11th May, 2010).
[40] http://en.wikipedia.org/wiki/Root_mean_square (Last Accessed 11th May, 2010).
[41] http://pdf1.alldatasheet.com/datasheetpdf/view/83642/NSC/ADCS7476AIMF.html (Last Accessed 11th May, 2010).
[42] Xilinx, Spartan-3E FPGA Starter Kit User Guide (UG230 v.1.1), Xilinx Inc., 20th
June 2008.
[43] Xilinx, Spartan-3A/AN FPGA Starter Kit User Guide (UG334 v.1.1), Xilinx Inc.,
19th June 2008.
[44] http://www.national.com/mpf/DC/ADCS7476.html (Last Accessed 12th May
2010).
[45] http://www.andreaelectronics.com/buy/productdesc/superbeam_array.htm
(Last Accessed 13th May 2010).
[46] http://www.ni.com/fpga/ (Last accessed 23rd April 2010).
[47] Digital System Design Using VHDL,
http://users.ece.utexas.edu/~roth/book/book.htm (Last Accessed 12th May 2010).
APPENDIX A: Main Codes
-------------------------------------------------------------------------------------------------------------------------------------------------Audiometer_toplevel.vhd-------------------------------------------------------------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
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entity Audiometer_toplevel is
Port ( CLK : in STD_LOGIC;--50MHz clk signal
RST : in STD_LOGIC;-- Asynchronous RESET signal
START : in STD_LOGIC;--This signal will tell when to start conversion
SCLK : out STD_LOGIC;--12.5MHz serial CLK after division
nCS : out STD_LOGIC;--This is the chip select signal to turn ON the ADC
LED : out STD_logic_vector (7 downto 0);
control : out std_logic_vector (2 downto 0); -- LCD_RS, LCD_RW, LCD_E
sf_d: out STD_LOGIC_VECTOR (7 downto 0); --LCD data bus
SDATA : in STD_LOGIC); -- This signal is to cater the data is serially shifted into
end Audiometer_toplevel;
architecture Behavioral of Audiometer_toplevel is
---------------------------------------------------------- FIFO Componenent
--------------------------------------------------------component FIFO
port (
clk: IN std_logic;
din: IN std_logic_VECTOR(11 downto 0);
rd_en: IN std_logic;
rst: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(11 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
---------------------------------------------------------- LED ROM Componenent
--------------------------------------------------------component LED_DISTMEM
port (
a: IN std_logic_VECTOR(11 downto 0);
spo: OUT std_logic_VECTOR(7 downto 0));
end component;
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---------------------------------------------------------- LCD ROM Componenent
--------------------------------------------------------component LCD_DISTMEM
port (
a: IN std_logic_VECTOR(11 downto 0);
spo: OUT std_logic_VECTOR(23 downto 0));
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of LED_DISTMEM: component is true;
attribute syn_black_box of LCD_DISTMEM: component is true;
attribute syn_black_box of FIFO: component is true;
--------------------------------------------------------------SIGNALS---------------------------------------------------------------MicComponent Signal, User interface signals
signal DATA : std_logic_vector(11 downto 0);
signal DONE : std_logic;
------------------------------------------------------------------------------------------------------------FIFO
signal din: std_logic_VECTOR(11 downto 0);
signal rd_en: std_logic;
signal wr_en: std_logic;
signal dout: std_logic_VECTOR(11 downto 0);
--signal
empty: std_logic;
--signal
full: std_logic;
signal FIFO_output : std_logic_vector (11 downto 0);
--------------------------------------------------------LCD controller signals
------------------------------------------------------signal ASCII_Values : std_logic_vector (23 downto 0);--LCD ASCII Values
--signal control : std_logic_vector (2 downto 0); -- LCD_RS, LCD_RW, LCD_E
--signal sf_d : STD_LOGIC_VECTOR (7 downto 0); --LCD data bus
--------------------------------------------------------LED process signals
------------------------------------------------------signal LED_ROM_output :std_logic_vector (7 downto 0):="00000000" ;
signal LED_temp : std_logic_vector (7 downto 0):= "00000000";
------------------------------------------------------begin
mic: entity work.MicComponent
port map (
--General usage
RST=>RST,
CLK=>CLK,
--Pmod interface signals
SDATA=>SDATA,
SCLK=>SCLK,
nCS=>nCS,
--User interface signals
DATA => DATA,
START => START,--pushbutton BTN_West
DONE => DONE);
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--FIFO
ADCFIFO: FIFO
port map (
clk=> CLK,
din=> DATA,
rd_en => START,--pushbutton BTN_West
rst=> RST,
wr_en=>DONE,
dout=> FIFO_output,--LED, LCD ROM
empty=> open,
full=> open);
LCDROM : LCD_DISTMEM
port map (
a => FIFO_output, --or DATA,
spo => ASCII_Values);
LCD_control : entity work.LCD_control
port map (
ASCII_Values=> ASCII_Values,
rst => RST,
clk => CLK,
control => Control,
sf_d => sf_d);
LEDROM : LED_DISTMEM
port map (
a => FIFO_output,--or DATA,
spo => LED_ROM_output);
---------------------------------------------------------------LED coding process
-------------------------------------------------------------LED_proc : process (RST, CLK, DONE, FIFO_output)
begin
if RST = '1' then
LED_temp<= "00000000";
elsif (CLK'event and CLK = '1') then
if (DONE ='1') then
LED_temp<= LED_ROM_output;
LED<=LED_temp;
end if;
end if;
end process;
end Behavioral;
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----------------------------------------------------------------------------------------------------------------------------------------------------------- PMODMic.vhd--------------------------------------------------------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity MicComponent is
Port ( CLK : in STD_LOGIC;--50MHz clk signal
RST : in STD_LOGIC;-- Asynchronous RESET signal
START : in STD_LOGIC;--This signal will tell when to start conversion
SCLK : out STD_LOGIC;--12.5MHz serial CLK after division
DATA : out STD_LOGIC_VECTOR (11 downto 0); --this is the data signal which contains the
--ADC code
nCS : out STD_LOGIC;--This is the chip select signal to turn ON the ADC
DONE : out STD_LOGIC;-- This signal is to tell that the conversion is done
SDATA : in STD_LOGIC); -- This signal is to cater the data is serially shifted into
end MicComponent;
architecture MIC of MicComponent is
---------------------------------------------------------------------------------------This mic will be designed to operate in a way of a finite state machine (FSM).
--Signal assignments:
--current_state: Is a pointer signal that will point at the current state of the controller's FSM.
--next_state: Is apointer signal that will point at the next state of the controller's FSM.
--temp: Is a 16-bit vector signal that will store the serially shifted-in data into the ADC
--clk_div: The divided 12.5MHz CLK signal that will clock the Mic
--clk_counter: This signal is used to to create the divided clock signal
--shiftcounter: This is a counter that will be used to count the shifted data from the ADC
--endshiftcounter:This signal is used to enable the counter for shifted data in the ADC.
--enparallelLoad:This signal will be used to enable the load of the shifted data in the counter.
-------------------------------------------------------------------------------type states is (Idle,
ShiftIn,
SyncData);
signal current_state : states;
signal next_state : states;
signal temp
: std_logic_vector(15 downto 0);
signal clk_div
: std_logic;
signal shiftCounter : std_logic_vector(3 downto 0) := x"0";
signal enShiftCounter: std_logic;
signal enParalelLoad : std_logic;
signal clk_1_int : std_logic := '0';
signal clk_1 : std_logic := '0';
signal clk_2_int : std_logic := '0';
signal clk_2 : std_logic := '0';
signal clk_SCLK_int : std_logic := '0';
signal clk_SCLK : std_logic := '0';
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begin
---------------------------------------------------------------------------------Clock Divider Process:
--Below will be the clock divider process where the 50MHz clock signal
--from Spartan3E board will be divided into 12.5MHz clock signal to drive the ADC.
-------------------------------------------------------------------------------clock_divide1 : process(CLK)
begin
if (CLK = '1' and CLK'event) then
clk_1_int <= not(clk_1_int);
clk_1 <= clk_1_int; --CLK (50MHz) is divided by two= 25MHz assing to clk_1
end if;
end process;
clock_divide2 : process(clk_1)
begin
if (clk_1= '1' and clk_1'event) then
clk_2_int <= not(clk_2_int);
clk_2 <= clk_2_int;
clk_div <= clk_2_int; --CLK (25MHz) is divided by two= 12.5MHz
SCLK <= clk_2_int; --assigned to clk_div and SCLK
end if;
end process;
------------------------------------------------------------------------------------ Counter:
-- Next is the Counter. This process will collect the converted data and send to output.
-- The 16bits of data from ADC will be shifted inside the temporary registers when the endshiftcounter
-- is activated.The counter is a 4bit, which will keep shifting the data into the temp register
-- for 16 clock cycles.When the enpararrelLoad signal is generated in in the SyncData state,
-- the converted data will then be placed in the output signal, DATA.
----------------------------------------------------------------------------------counter : process(clk_div, enParalelLoad, enShiftCounter)
begin
if (clk_div = '1' and clk_div'event) then
if (enShiftCounter = '1') then --when endShiftCounter is activated
temp <= temp(14 downto 0) & SDATA; --16bit data is stored in temp and AND with
-- SDATA
shiftCounter <= shiftCounter + '1';
elsif (enParalelLoad = '1') then --enParalelLoad is generated.
shiftCounter <= "0000"; --4bit counter is set to 0.
DATA <= temp(11 downto 0); --after the leading 4 zeros on the counter,
end if;
end if;
end process;
---------------------------------------------------------------------------------- The following process is the Finite State Machine (FSM)
-- There are three processes representing the FSM
--1. Idle state: The temporary registers will be assigned the updated value of the input "DATA".
--2. ShiftIn state: The 16-bits of data ADC are left shifted in the temp shift register.
--3. SyncData : This state will drive the output signal nCS high for 1 clock period maintainig
-- nCS high and also in the Idle state to to tell the ADC to mark the end of the conversion.
--*The data will change on the lower edge of the clock signal.
--The asynchronous reset will reset all signals to their original state.
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-------------------------------------------------------------------------------------SYNC_PROC process:
--The states in this process are changed synchronously.
--At reset the current state becomes Idle state.
-----------------------------------------------------------------------------------SYNC_PROC: process (clk_div, RST)
begin
if (clk_div'event and clk_div = '1') then -- on falling clock edge
if (rst = '1') then
current_state <= Idle;--return to idle state if reset =1
else
current_state <= next_state;--move on to next state
end if;
end if;
end process;
-------------------------------------------------------------------------------------OUTPUT_DECODE:
--In this process, the output signals are generated unsynchronously based on the
--state only (Moore State Machine).
-----------------------------------------------------------------------------------OUTPUT_DECODE: process (current_state)
begin
if current_state = Idle then
enShiftCounter <='0';
DONE <='1';
nCS <='1';
enParalelLoad <= '0';
elsif current_state = ShiftIn then
enShiftCounter <='1';
DONE <='0';
nCS <='0';
enParalelLoad <= '0';
elsif current_state = SyncData then --changes
enShiftCounter <='0';
DONE <='0';
nCS <='1';
enParalelLoad <= '1';
end if;
end process;
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------------------------------------------------------------------------------------NEXT_STATE_DECODE
--Finally, in the NEXT_STATE_DECODE process, the next state logic is
--generated depending on the current state and the input signals.
-----------------------------------------------------------------------------------NEXT_STATE_DECODE: process (current_state, START, shiftCounter)
begin
next_state <= current_state; -- by default is to stay in current state
case (current_state) is
when Idle =>
if START = '1' then
next_state <= ShiftIn;
end if;
when ShiftIn =>
if shiftCounter = x"F" then
next_state <= SyncData;
end if;
when SyncData =>
if START = '0' then
next_state <= Idle;
end if;
when others =>
next_state <= Idle;
end case;
end process;
end MIC;
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------------------------------------------------------------------------------------------------------------------------------------------------------ LCD_Controller_al.vhd---------------------------------------------------------------------------------------------------------------------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity lcd_control is
port (
-DATA : in std_logic_vector (11 downto 0);
ASCII_Values: in std_logic_vector (23 downto 0);
rst : in STD_LOGIC;
clk : in STD_LOGIC;
control : out std_logic_vector (2 downto 0); -- LCD_RS, LCD_RW, LCD_E
sf_d: out STD_LOGIC_VECTOR (7 downto 0)); --LCD data bus
end lcd_control;
architecture lcd_control_arch of lcd_control is
------------------------------------------------------------------Signals
signal a : std_logic_vector (11 downto 0);--??
----------------------------------------------------------------type state_type is (waiting, init1,init2,init3,init4,init5,init6,init7,
wordA,wordU,wordD,wordI,wordO,wordSPACE,wordM,wordE1,wordT,wordE2,wordR1,
wordR2_addr, wordR2, wordE3,wordA2,wordD2,wordI2,wordN,wordG,wordEQUAL,
word_d_addr , word_d, word_B_addr, word_B,dbSign_addr, dbSign_state, dbValue1_addr,
dbValue1_state, dbValue2_addr, dbValue2_state, donestate);
signal state,next_state : state_type;
signal sf_d_temp : std_logic_vector (7 downto 0) := "00000000";
signal count, count_temp : integer := 0;
signal state_flag : std_logic := '0';
signal dbSign : std_logic_vector (7 downto 0);
signal db_Value1 : std_logic_vector (7 downto 0);
signal db_Value2 : std_logic_vector (7 downto 0);
------------------------------------------------------------------Constants
signal a : std_logic_vector (11 downto 0);--??
----------------------------------------------------------------constant TIME1 : integer := 750000;
constant TIME2 : integer := 1;
constant TIME3 : integer := 210000;
constant TIME4 : integer := 420000;
begin
initialize : process (clk,state,count, ASCII_Values) is
begin
dbSign <= ASCII_Values (23 downto 16);
db_Value1 <= ASCII_Values (15 downto 8);
db_Value2 <= ASCII_Values (7 downto 0);
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case state is
------------- Initialization Starts -------------------------------when waiting =>
sf_d_temp <= "00000000";
control <= "000"; -- RS,RW, E --[RS(0=instruction, 1= DATA), RW(0=write (accept data),1= read
(present data), E (0= disabled, 1=read/write)]
if (count >= TIME1) then
next_state <= init1;
state_flag <= '1';
else next_state <= waiting; state_flag <= '0';
end if;
when init1 =>
sf_d_temp <= "00111100"; --Function set DL = 8bit, NL = 2, Font = 5x11
if (count = TIME4) then
next_state <= init2; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init1; control <= "000"; state_flag <= '0';
else next_state <= init1; control <= "001"; state_flag <= '0';
end if;
when init2 =>
sf_d_temp <= "00111100"; --Function set DL = 8bit, NL = 2, Font = 5x11
if (count = TIME4) then
next_state <= init3; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init2; control <= "000"; state_flag <= '0';
else next_state <= init2; control <= "001"; state_flag <= '0';
end if;
when init3 =>
sf_d_temp <= "00111100"; --Function set DL = 8bit, NL = 2, Font = 5x11
if (count = TIME4) then
next_state <= init4; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME4) then
next_state <= init3; control <= "000"; state_flag <= '0';
else next_state <= init3; control <= "001"; state_flag <= '0';
end if;
when init4 =>
sf_d_temp <= "00111100"; --Function set DL = 8bit, NL = 2, Font = 5x11-- "<"sign
if (count = TIME3) then
next_state <= init5; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init4; control <= "000"; state_flag <= '0';
else next_state <= init4; control <= "001"; state_flag <= '0';
end if;
when init5 =>
sf_d_temp <= "00001100"; --Set Display Display=on, Cursor=off, cursor_position=off
if (count = TIME3) then
next_state <= init6; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init5; control <= "000"; state_flag <= '0';
else next_state <= init5; control <= "001"; state_flag <= '0';
end if;
when init6 =>
sf_d_temp <= "00000001"; --Clear Display
-- set_timer_flag <= '0'; set_clock_flag <= '0'; --reset display flags
if (count = TIME3) then
next_state <= init7; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init6; control <= "000"; state_flag <= '0';
else next_state <= init6; control <= "001"; state_flag <= '0';
end if;
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when init7 =>
sf_d_temp <= "00000110"; --Entry Mode set ID=1, S=0
if (count = TIME3) then
next_state <= wordA; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= init7; control <= "000"; state_flag <= '0';
else next_state <= init7; control <= "001"; state_flag <= '0';
end if;
------------------------- Initialization Ends -----------------------------------------------------------Write out 'AUDIO'----------------------when wordA =>
sf_d_temp <= "01000001"; -- A
if (count = TIME3) then
next_state <= wordU; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordA; control <= "100"; state_flag <= '0';
else next_state <= wordA; control <= "101"; state_flag <= '0';
end if;
when wordU =>
sf_d_temp <= "01010101"; -- U
if (count = TIME3) then
next_state <= wordD; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordU; control <= "100"; state_flag <= '0';
else next_state <= wordU; control <= "101"; state_flag <= '0';
end if;
when wordD =>
sf_d_temp <= "01000100"; -- D
if (count = TIME3) then
next_state <= wordI; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordD; control <= "100"; state_flag <= '0';
else next_state <= wordD; control <= "101"; state_flag <= '0';
end if;
when wordI =>
sf_d_temp <= "01001001"; -- I
if (count = TIME3) then
next_state <= wordO; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordI; control <= "100"; state_flag <= '0';
else next_state <= wordI; control <= "101"; state_flag <= '0';
end if;
when wordO =>
sf_d_temp <="01001111"; -- O
if (count = TIME3) then
next_state <= wordSPACE; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordO; control <= "100"; state_flag <= '0';
else next_state <= wordO; control <= "101"; state_flag <= '0';
end if;
-------------------------Write out a space----------------------when wordSPACE =>
sf_d_temp <= "00100000"; -- SPACE
if (count = TIME3) then
next_state <= wordM; control <= "101"; state_flag <= '1';
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elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordSPACE; control <= "100"; state_flag <= '0';
else next_state <= wordSPACE; control <= "101"; state_flag <= '0';
end if;
-------------------------Write out 'METER'----------------------when wordM =>
sf_d_temp <= "01001101"; -- M
if (count = TIME3) then
next_state <= wordE1; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordM; control <= "100"; state_flag <= '0';
else next_state <= wordM; control <= "101"; state_flag <= '0';
end if;
when wordE1 =>
sf_d_temp <= "01000101"; -- E
if (count = TIME3) then
next_state <= wordT; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordE1; control <= "100"; state_flag <= '0';
else next_state <= wordE1; control <= "101"; state_flag <= '0';
end if;
-- when word_T_addr =>
-- sf_d_temp <= "10001000"; -- Set Address hx08
-- if (count = TIME3) then
-- next_state <= word10; control <= "001"; state_flag <= '1'; --control 001 is instruction, accept data,
enable
-- elsif (count > TIME2 AND count <= TIME3) then
-- next_state <= word_T_addr; control <= "000"; state_flag <= '0'; --control 000 is disable
-- else next_state <= word_T_addr; control <= "001"; state_flag <= '0';--control 001 is instruction,
accept data, enable
-- end if;
when wordT =>
sf_d_temp <= "01010100"; -- T
if (count = TIME3) then
next_state <= wordE2; control <= "101"; state_flag <= '1';--control 101 is Data, accept data, enable
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordT; control <= "100"; state_flag <= '0'; --control 100 is Data, accept data, disable
else next_state <= wordT; control <= "101"; state_flag <= '0'; --control 101 is Data, accept data, enable
end if;
when wordE2 =>
sf_d_temp <= "01000101"; -- E
if (count = TIME3) then
next_state <= wordR1; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordE2; control <= "100"; state_flag <= '0';
else next_state <= wordE2; control <= "101"; state_flag <= '0';
end if;
when wordR1 =>
sf_d_temp <= "01010010"; -- R
if (count = TIME3) then
next_state <= wordR2_addr; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordR1; control <= "100"; state_flag <= '0';
else next_state <= wordR1; control <= "101"; state_flag <= '0';
end if;
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-------------------------Write out 'READING'----------------------when wordR2_addr =>
sf_d_temp <= "11000000"; -- Set Address hx40
if (count = TIME3) then
next_state <= wordR2; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordR2_addr; control <= "000"; state_flag <= '0';
else next_state <= wordR2_addr; control <= "001"; state_flag <= '0';
end if;
when wordR2 =>
sf_d_temp <= "01010010"; -- R
if (count = TIME3) then
next_state <= wordE3; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordR2; control <= "100"; state_flag <= '0';
else next_state <= wordR2; control <= "101"; state_flag <= '0';
end if;
when wordE3 =>
sf_d_temp <= "01000101"; -- E
if (count = TIME3) then
next_state <= wordA2; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordE3; control <= "100"; state_flag <= '0';
else next_state <= wordE3; control <= "101"; state_flag <= '0';
end if;
when wordA2=>
sf_d_temp <= "01000001"; -- A
if (count = TIME3) then
next_state <= wordD2; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordA2; control <= "100"; state_flag <= '0';
else next_state <= wordA2; control <= "101"; state_flag <= '0';
end if;
when wordD2 =>
sf_d_temp <= "01000100"; -- D
if (count = TIME3) then
next_state <= wordI2; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordD2; control <= "100"; state_flag <= '0';
else next_state <= wordD2; control <= "101"; state_flag <= '0';
end if;
when wordI2 =>
sf_d_temp <= "01001001"; -- I
if (count = TIME3) then
next_state <= wordN; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordI2; control <= "100"; state_flag <= '0';
else next_state <= wordI2; control <= "101"; state_flag <= '0';
end if;
when wordN =>
sf_d_temp <= "01001110"; -- N
if (count = TIME3) then
next_state <= wordG; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordN; control <= "100"; state_flag <= '0';
else next_state <= wordN; control <= "101"; state_flag <= '0';
end if;
when wordG =>
sf_d_temp <= "01000111"; -- G
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if (count = TIME3) then
next_state <= wordEQUAL; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordG; control <= "100"; state_flag <= '0';
else next_state <= wordG; control <= "101"; state_flag <= '0';
end if;
-------------------------Write out '='----------------------when wordEQUAL =>
sf_d_temp <= "00111101"; -- '='
if (count = TIME3) then
next_state <= word_d_addr ; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= wordEQUAL; control <= "100"; state_flag <= '0';
else next_state <= wordEQUAL; control <= "101"; state_flag <= '0';
end if;
-----------------------Write out the d----------------------when word_d_addr =>
sf_d_temp <= "11001011"; -- Set Address hx4B
if (count = TIME3) then
next_state <= word_d; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_d_addr; control <= "000"; state_flag <= '0';
else next_state <= word_d_addr; control <= "001"; state_flag <= '0';
end if;
when word_d =>
sf_d_temp <= "01100100"; --"d"
if (count = TIME3) then
next_state <= word_B_addr; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_d; control <= "100"; state_flag <= '0';
else next_state <= word_d; control <= "101"; state_flag <= '0';
end if;
-----------------------Write out B----------------------when word_B_addr =>
sf_d_temp <= "11001100"; -- Set Address hx4C
if (count = TIME3) then
next_state <= word_B; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_B_addr; control <= "000"; state_flag <= '0';
else next_state <= word_B_addr; control <= "001"; state_flag <= '0';
end if;
when word_B =>
sf_d_temp <= "01000010"; --"B"
if (count = TIME3) then
next_state <= dbSign_addr; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= word_B; control <= "100"; state_flag <= '0';
else next_state <= word_B; control <= "101"; state_flag <= '0';
end if;
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-------------------------Write out 'space' for 0dB or '-' for others'----------------------when dbSign_addr =>
sf_d_temp <= "11001000"; -- Set Address hx48
if (count = TIME3) then
next_state <= dbSign_state ; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= dbSign_addr ; control <= "000"; state_flag <= '0';
else next_state <= dbSign_addr ; control <= "001"; state_flag <= '0';
end if;
when dbSign_state=> -- display either - or space
sf_d_temp <= dbSign;
if (count = TIME3) then
next_state <= dbValue1_addr; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= dbSign_state ; control <= "000"; state_flag <= '0';
else next_state <= dbSign_State; control <= "001"; state_flag <= '0';
end if;
------------------------------Write out the dB value1----------------------when dbValue1_addr =>
sf_d_temp <= "11001001"; -- Set Address hx49
if (count = TIME3) then
next_state <= dbValue1_state; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= dbValue1_addr ; control <= "000"; state_flag <= '0';
else next_state <= dbValue1_addr ; control <= "001"; state_flag <= '0';
end if;
when dbValue1_state =>
sf_d_temp <= db_Value1; -- 1st digit of dB value
if (count = TIME3) then
next_state <= dbValue2_addr; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= dbValue1_state ; control <= "100"; state_flag <= '0';
else next_state <= dbValue1_state ; control <= "101"; state_flag <= '0';
end if;
---------------------------Write out the dB value2----------------------when dbValue2_addr=>
sf_d_temp <= "11001010"; -- Set Address hx4A
if (count = TIME3) then
next_state <= dbValue2_addr; control <= "001"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= dbValue2_addr; control <= "000"; state_flag <= '0';
else next_state <= dbValue2_addr; control <= "001"; state_flag <= '0';
end if;
when dbValue2_state=>
sf_d_temp <= db_Value2; -- 2nd digit of dB value
if (count = TIME3) then
next_state <= donestate; control <= "101"; state_flag <= '1';
elsif (count > TIME2 AND count <= TIME3) then
next_state <= dbValue2_state; control<= "100"; state_flag <= '0';
else next_state <= dbValue2_state; control <= "101"; state_flag <= '0';
end if;
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-------------------------------DoneSate------------------------------------when donestate =>
control <= "100";
sf_d_temp <= "00000000";
if (count = TIME3) then
next_state <= donestate; state_flag <= '1';
else next_state <= donestate; state_flag <= '0';
end if;
end case;
end process initialize;
-----------------------------------------------------------------------------timing : process (rst, clk, count) is
begin
if (rising_edge(clk)) then
sf_d <= sf_d_temp;
count <= count_temp;
if (rst = '1') then
state <= waiting;
--mode_state <= '0';
count_temp <= 0;
elsif (state_flag = '1') then
state <= next_state;
--mode_state <= next_mode_state;
count_temp <= 0;
else
state <= next_state;
--mode_state <= next_mode_state;
count_temp <= count_temp + 1;
end if;
end if;
end process timing;
end lcd_control_arch;
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APPENDIX B: TEST BENCH CODES
-------------------------------------------------------------------------------------------------------------------------------------------------Spartan3A_MIC_tb.vhd---------------------------------------------------------------------------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY Spartan3A_MIC_tb2 IS
END Spartan3A_MIC_tb2;
ARCHITECTURE behavior OF Spartan3A_MIC_tb2 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MicComponent
PORT(
CLK : IN std_logic;
RST : IN std_logic;
START : IN std_logic;
SCLK : OUT std_logic;
DATA : OUT std_logic_vector(11 downto 0);
nCS : OUT std_logic;
DONE : OUT std_logic;
SDATA : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
signal START : std_logic := '0';
signal SDATA : std_logic := '0';
--Outputs
signal SCLK : std_logic;
signal DATA : std_logic_vector(11 downto 0);
signal nCS : std_logic;
signal DONE : std_logic;
--SImulation signals
--signal clock_counter : std_logic_vector(7 downto 0):="00000000";
--Constants
constant PERIOD : time := 20 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 10 ns;
BEGIN
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-- Instantiate the Unit Under Test (UUT)
uut: MicComponent PORT MAP (
CLK => CLK,
RST => RST,
START => START,
SCLK => SCLK,
DATA => DATA,
nCS => nCS,
DONE => DONE,
SDATA => SDATA
);
PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
CLK<= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
CLK <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
tb:PROCESS
BEGIN
--------------WAIT FOR 80 ns;--80ns
START <= '1';
-WAIT FOR 80 ns;--80ns
-START <= '0';
--1st set of data
--leading 4zeroes of 16bit per clock cycle
WAIT FOR 80 ns;--80ns
SDATA <= '0';--1cycle
WAIT FOR 80 ns;--160ns
SDATA <= '0';--2cycle
WAIT FOR 80 ns;--240ns
SDATA <= '0';--3cycle
WAIT FOR 80 ns;--320ns
SDATA <= '0';--4cycle
--next 12clock cycles consists of 12bit data "111111111111"
WAIT FOR 80 ns;--400ns
SDATA <= '1';--5cycle
WAIT FOR 80 ns;--480ns
SDATA <= '1';--6cycle
WAIT FOR 80 ns;--560ns
SDATA <= '1';--7cycle
WAIT FOR 80 ns;--640ns
SDATA <= '1';--8cycle
WAIT FOR 80 ns;--720ns
SDATA <= '1';--9cycle
WAIT FOR 80 ns;--800ns
SDATA <= '1';--10cycle
WAIT FOR 80 ns;--880ns
SDATA <= '1';--11cycle
WAIT FOR 80 ns;--960ns
SDATA <= '1';--12cycle
WAIT FOR 80 ns;--1040ns
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SDATA <= '1';--13cycle
WAIT FOR 80 ns;--1120ns
SDATA <= '1';--14cycle
WAIT FOR 80 ns;--1200ns
SDATA <= '1';--15cycle
WAIT FOR 80 ns;--1280ns
SDATA <= '1';--16cycles
WAIT FOR 80 ns;--1360ns
SDATA <= '1';--17cycles -- to trigger complete
-WAIT FOR 80 ns;--1440ns
-START <= '1';
-WAIT FOR 80 ns;--1440ns
-START <= '0';
--2nd set of data
--leading 4zeroes of 16bit per clock cycle
WAIT FOR 80 ns;--1440ns
SDATA <= '0';--1cycle
WAIT FOR 80 ns;--1520ns
SDATA <= '0';--2cycles
WAIT FOR 80 ns;--1600ns
SDATA <= '0';--3cycles
WAIT FOR 80 ns;--1680ns
SDATA <= '0';--4cycles
--next 12clock cycles consists of 12bitdata "000111111111"
WAIT FOR 80 ns;--1760ns
SDATA <= '0';--5cycles
WAIT FOR 80 ns;--1840ns
SDATA <= '0';--6cycle
WAIT FOR 80 ns;--1920ns
SDATA <= '0';--7cycle
WAIT FOR 80 ns;--2000ns
SDATA <= '0';--8cycle
WAIT FOR 80 ns;--2080ns
SDATA <= '1';--2160cycle
WAIT FOR 80 ns;--410ns
SDATA <= '1';--10cycle
WAIT FOR 80 ns;--2240ns
SDATA <= '1';--11cycle
WAIT FOR 80 ns;--2320ns
SDATA <= '1';--12cycle
WAIT FOR 80 ns;--2400ns
SDATA <= '1';--13cycle
WAIT FOR 80 ns;--2480ns
SDATA <= '1';--14cycle
WAIT FOR 80 ns;--2560ns
SDATA <= '1';--15cycle
WAIT FOR 80 ns;--2640ns
SDATA <= '1';--16cycle
WAIT FOR 80 ns;--2720ns
SDATA <= '1';--17cycles-- to trigger complete
-START <= '0';-- to stop decode
END PROCESS;
END;
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---------------------------------------------------------------------------------lcd_control_tb.vhd--------------------------------------------------------------------------------LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY lcd_control_tb IS
END lcd_control_tb;
ARCHITECTURE behavior OF lcd_control_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT lcd_control
PORT(
DATA : IN std_logic_vector(11 downto 0);
rst : IN std_logic;
clk : IN std_logic;
control : OUT std_logic_vector(2 downto 0);
sf_d : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
type state_type is (waiting, init1,init2,init3,init4,init5,init6,init7,
wordA,wordU,wordD,wordI,wordO,wordSPACE,wordM,wordE1,wordT,wordE2,wor
dR1, wordR2_addr, wordR2,
wordE3,wordA2,wordD2,wordI2,wordN,wordG,wordEQUAL,
word_d_addr , word_d, word_B_addr, word_B,dbSign_addr, dbSign_state,
dbValue1_addr, dbValue1_state, dbValue2_addr, dbValue2_state, donestate);
signal state,next_state : state_type;
signal sf_d_temp : std_logic_vector (7 downto 0) := "00000000";
signal count, count_temp : integer := 0;
signal state_flag
--Inputs
signal DATA : std_logic_vector(11 downto 0) := (others => '0');
signal rst : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal control : std_logic_vector(2 downto 0);
signal sf_d : std_logic_vector(7 downto 0);
signal iLoop : integer 0 to 4095;
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--Constants
constant PERIOD : time := 20 ns;
constant DUTY_CYCLE : real := 0.5;
constant OFFSET : time := 10 ns;
constant TIME1 : integer := 750000;
constant TIME2 : integer := 1;
constant TIME3 : integer := 210000;
constant TIME4 : integer := 420000;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: lcd_control PORT MAP (
DATA => DATA,
rst => rst,
clk => clk,
control => control,
sf_d => sf_d
);
-- Clock process definitions
clocking:PROCESS -- clock process for clk
BEGIN
WAIT for OFFSET;
CLOCK_LOOP : LOOP
clk<= '0';
WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
clk <= '1';
WAIT FOR (PERIOD * DUTY_CYCLE);
END LOOP CLOCK_LOOP;
END PROCESS;
sim: process --(state,count)
BEGIN
WAIT for 40ns;
count<=TIME1;
count<=TIME2;
count<=TIME3;
count<=TIME4;
-DATA<="000000000000";
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--state<= waiting;
--state<= WORD1;
WAIT;
-end process;
-END;
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APPENDIX C: User Constraints CODE
-------------------------------------------------------------------------------------------------------------------------------------------------------Audiometer_toplevel.ucf-------------------------------------------------------------------------------------------------------------------------------------------------####################################
#############clock UCF##############
####################################
NET "CLK" LOC = "E12"| IOSTANDARD = LVCMOS33 ; ##CLK_50MHZ
# Define clock period for 50 MHz oscillator
#>DISABLED<#NET "CLK" PERIOD = 20 ns HIGH 40%;
####################################
#####==== 6-pin header J18 ====#####
####################################
NET "nCS" LOC = "AA21" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE =
;##J18_IO<1>
#NET "J18_IO<2>" LOC = "AB21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE =
;##not connected
NET "SDATA" LOC = "AA19" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE =
;##J18_IO<3>
NET "SCLK" LOC = "AB19" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE =
;##J18_IO<4>
8
8
8
8
####################################
#########Discrete LED UCF ##########
####################################
NET "LED<7>" LOC = "W21" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
NET "LED<6>" LOC = "Y22" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
NET "LED<5>" LOC = "V20" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
NET "LED<4>" LOC = "V19" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
NET "LED<3>" LOC = "U19" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
NET "LED<2>" LOC = "U20" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
NET "LED<1>" LOC = "T19" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
NET "LED<0>" LOC = "R20" |IOSTANDARD = LVCMOS33 |SLEW = SLOW |DRIVE = 8 ;
#####################################
#######Push Button Switches UCF #######
####################################
NET "RST" LOC = "T16" |IOSTANDARD = LVCMOS33 |PULLDOWN ; ##BTN_EAST
NET "START" LOC = "T15" | IOSTANDARD = LVCMOS33 | PULLDOWN ;#"BTN_SOUTH"
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###################
#####LCD UCF #####
###################
###==CONTROLS== ###
NET "Control<0>" LOC = "AB4" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW ;
##LCD_E
NET "Control<2>" LOC = "Y14" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
;##LCD_RS
NET "Control<1>" LOC = "W13" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
;##LCD_RW
#####==DATA==#####
NET "sf_d<7>" LOC =
;#LCD_DB<7>
NET "sf_d<6>" LOC =
;#LCD_DB<6>
NET "sf_d<5>" LOC =
;#LCD_DB<5>
NET "sf_d<4>" LOC =
;#LCD_DB<4>
NET "sf_d<3>" LOC =
;#LCD_DB<3>
NET "sf_d<2>" LOC =
;#LCD_DB<2>
NET "sf_d<1>" LOC =
;#LCD_DB<1>
NET "sf_d<0>" LOC =
;#LCD_DB<0>
"Y15" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
"AB16" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
"Y16" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
"AA12" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
"AB12" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
"AB17" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
"AB18" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
"Y13" |IOSTANDARD = LVCMOS33 |DRIVE = 8 |SLEW = SLOW
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APPENDIX D: Decibel Calculations Worksheet.
Voltage dB Formula
Log (Vref/VDD)
20*(Log (Vref/VDD))
round off to nearest 10
0
0
0.0000000000
0.0000000000 No Sound
No Sound
-No Sound
1
0.5
0.0004028320
0.0001220703
-3.913389944
-78
-80
2
1.5
0.0012084961
0.0003662109
-3.436268689
-69
-70
3
2.5
0.0020141602
0.0006103516
-3.214419939
-64
-60
8
7.5
0.0060424805
0.0018310547
-2.737298685
-55
-60
9
8.5
0.0068481445
0.0020751953
-2.682941022
-54
-50
24
23.5
0.0189331055
0.0057373047
-2.241292086
-45
-50
25
24.5
0.0197387695
0.0059814453
-2.223193864
-44
-40
77
76.5
0.0616333008
0.0186767578
-1.728698513
-35
-40
78
77.5
0.0624389648
0.0189208984
-1.723058245
-34
-30
244
243.5
0.1961791992
0.0594482422
-1.225860982
-25
-30
245
244.5
0.1969848633
0.0596923828
-1.224081085
-24
-20
772
771.5
0.6215698242
0.1883544922
-0.725024018
-15
-10
773
772.5
0.6223754883
0.1885986328
-0.72446146
-14
-10
2440
2439.5
1.9654174805
0.5955810547
-0.225059126
-5
-10
2441
2440.5
1.9662231445
0.5958251953
-0.224881136
-4
0
4095
4094.5
3.2987915039
0.9996337891
-0.000159073
0
0
*The illustrated data above are a range of values with their matching colours. Not all 40956 values are shown.
ADC Code
LSB
VOLTS
Voltage Value:
VDD
3.3
1LSB
0.000805664
Scale Guide:
Range
0 to 4
5 to 14
Vref/VDD
v
v
Rounding off
0dB
10dB
APPENDIX E: Project Management
_____________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
86
Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
(E0605744 )
ENG499- Capstone Project Schedule (Design an Audio Meter Using FPGA)
Legend:
P
Planned
A
Actual
Month/Year
S/N
1
1.0
1.1
Aug'09
July'09
Task
Project Reasearch and Proposal
Meet Supervisor :Preliminary discussion with
Supervisor on Project Proposal and Direction
1.2
Project Research
1.3
Capstone Project Briefing
1.4
Meet Supervisor(Tutorial1): Project Proposal
Discussion
1.5
Meet Supervisor(Tutorial 2): Literature search –
preliminary work
1.6
Writing of Project Proposal
2.0
Project Design
Evaluation of project methods, user requirements,
literature review, design issues, etc
2
3
4
Sept'09
5
Oct'09
Nov'09
Dec'09
Jan'10
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
Study Week
23
24
25
Feb'10
26
27
28
29
P
P
P
P
30
Mar'10
31
32
33
34
Apr'10
35
36
37
38
39
May'10
40
41
42
43
44
45
P
P
P
P
P
P
P
A
A
P
A
A
A
A
A
P
P
P
P
A
2.1
2.2
Meet Supervisor(Tutorial 3): Feedback of Project
Proposal
2.3
Gather user requirements/system specifications.
2.4
Meet Supervisor(Tutorial4):
Progress Meeting
2.4
Selection and implementation of system development
methods and project management techniques.
2.5
Meet Supervisor(Tutorial5): Progress meeting &
discussion on Draft Chapter
3.0
P
P
P
P
P
P
P
P
A
A
A
A
Delay due to board
Complicated too
complicated
program (Revision1)
P
P
P
P
P
P
P
P
P
Project Design Testing and Results Gathering
Carry out design investigations.
3.2
Interim Report Submission
3.3
Testing, measurements and refinement of system/model.
3.4
Meet supervisor (Tutorial 6): Check on details in results
of project with supervisor
3.5
Meet supervisor (Tutorial 7):
Meeting
3.6
Evaluation of design and model test/measurement
results.
4.1
A
P
P
3.1
4.0
P
P
P
P
P
P
Delay due to board
Complicated too
complicated
program (Revision1)
P
Progress
P
P
P
P
P
P
Delay due to board
Complicated too
complicated
program (Revision1)
P
P
P
P
P
P
P
Finalization of Project, Report Writing & Poster
Design
Meet supervisor (Tutorial 8):
Finalizing of
Design & Discussion on Project Report Details
P
P
P
4.2
Writing Project Report
P
4.3
Project Report and Poster Design Briefing
P
4.4
Meet supervisor (Tutorial 9):
Project
Report and Poster Presentation discussion
4.5
Meet supervisor (Tutorial 10): Project report
amendments discussion.
P
4.6
Formatting and finalizing of contents in Project Report.
P
4.7
Send report for binding.
4.8
Prepare A1 sized poster for presentation. Portrait format
and follow template given.
4.9
Capstone Project Report submission
5.0
5.1
Project Poster Presentation
Poster presentation
_____________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
P
P
P
P
P
P
P
P
P
P
P
P
P
P
87
P
Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
(E0605744 )
APPENDIX F
Xilinx Spartan3A Starter Kit Specs:
The Xilinx Spartan®-3A Starter Kit delivers instant access to Spartan-3A FPGA device features such as SUSPEND power-saving
mode, high-speed I/O options, DDR2 SDRAM memory interface, commodity flash configuration support, and FPGA/IP protection
using Device DNA Security.
For Japan Customers Only,
please order part number: HW-SPAR3A-SK-UNI-G-J
through your local Japan distributor.
Buy online from:
Avnet
Local distributor
What's Included
Development board
Power supply 100-240V, 50/60 Hz with universal plug adaptors
Xilinx ISE® WebPACK™ or ISE Foundation™ evaluation software
Quickstart guide
Programming cable
Product collateral
Key Features
Xilinx Devices
Spartan-3A (XC3S700A-FG484)
Platform Flash (XCF04S-VOG20C)
Clocks
50 MHz crystal oscillator on-board
Open slot for optional user-installed clock
Memory
4 Mbit Platform Flash PROM
32M x 16 DDR2 SDRAM
32 Mbit parallel Flash
2-16 Mbit SPI Flash devices
Analog Interface Devices
4-channel D/A converter
2-channel A/D converter
Signal amplifier
Connectors and Interfaces
Ethernet 10/100 PHY
JTAG USB download port
Two 9-pin RS-232 serial port
_____________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
88
Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
(E0605744 )
PS/2-style mouse/keyboard port
15-pin VGA connector capable of 4,096 colors
One FX2 100-pin and two 6-pin expansion connectors
20 user I/O available on standard header pins
Stereo mini-jack for PWM audio
Rotary/push button function switch
Eight individual LED outputs
Four slider switches
Four push-button switches
Display
16 character, 2-Line LCD
Targeted Applications
Markets: Consumer, Telecom / Datacom, Servers, Storage
Applications: General Prototyping
_____________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
89
Design An Audio Meter Using FPGA
Alagenthiran S/O Nadeson
(E0605744 )
APPENDIX G
Xilinx Spartan3E Starter Kit Specs:
What's Included
Development board
Universal power supply 100-240V, 50/60 Hz
Evaluation software: Xilinx ISE® software and EDK CDs
Handbook: Introduction to Programmable Logic Design Quick Start
Starter Kit resource CD
USB cable
Key Features
Xilinx Devices:
Spartan-3E FPGA (XC3S500E-4FG320C)
CoolRunner™-II CPLD (XC2C64A-5VQ44C)
Platform Flash (XCF04S-VO20C)
Clocks: 50 MHz crystal clock oscillator
Memory:
128 Mbit Parallel Flash
16 Mbit SPI Flash
64 MByte DDR SDRAM
Connectors and Interfaces:
Ethernet 10/100 Phy
JTAG USB download
Two 9-pin RS-232 serial port
PS/2- style mouse/keyboard port, rotary encoder with push button
Four slide switches
Eight individual LED outputs
Four momentary-contact push buttons
100-Pin expansion connection ports
Three 6-pin expansion connectors
Display: 16 character - 2 Line LCD
_____________________________________________________________________________________________________
ENG499 CAPSTONE PROJECT REPORT
90