Reg. No. ________
Karunya University
(Karunya Institute of Technology and Sciences)
(Declared as Deemed to be University under Sec.3 of the UGC Act, 1956)
End Semester Examination – November/ December - 2012
Subject Title:
Subject Code:
DIGITAL PRINCIPLES AND SYSTEM DESIGN
09IT204
Time: 3 hours
Maximum Marks: 100
Answer ALL questions
PART – A (10 x 1 = 10 MARKS)
x + x’y = ____________.
Convert (BABA) 16 to binary.
Represent 3124 in Excess-3-code.
When two n bit numbers are added and if it resulted in n+1 bits then ____________ has
occurred.
5. How many address lines and input output data are needed for the 8K*16 memory unit?
6. A decoder with an enable input can function as a __________________.
7. The 4-bit shift register is initialized to 1011. What are the contents of the register after it is
shifted six times to the right, with the serial input being 101111?
8. ____________ is a level sensitive, one bit storage element.
9. What is a primitive flow table?
10. How to avoid critical races?
1.
2.
3.
4.
PART – B (5 x 3 = 15 MARKS)
11.
12.
13.
14.
15.
Prove that
Design a 3 bit odd parity generator circuit.
Differentiate PLA and PAL.
Explain the operation of JK latch.
What is a flow table? Give an example.
PART – C (5 x 15 = 75 MARKS)
16. Simplify the following Boolean functions using K map:
a. F=∑(0,5,7,13,15,16,21,23,25,29,31).
b. F=∑ (1,3,5,7,8,9,12,13).
(OR)
17. a. Express the following function using sum of minterms and product of maxterms:
F(A,B,C,D ) = B’D+A’D+BD
b. Find the complement of
(10)
(5)
(10)
(5)
18. What is carry propagation delay in Binary Adder? How can it be avoided using carry look
ahead generator?
(OR)
19. a. A majority circuit is a combinational circuit whose output is equal to 1 if the input
variables have more 1’s than 0’s.The output is 0 otherwise. Design a 3bit majority circuit.
(10)
b. Write an HDL for a Half Adder circuit.
(5)
[P.T.O.]
20. Design a four bit priority encoder with input D3 having the highest priority and D0 having
lowest priority.
(OR)
21. Implement the following function using PLA
a. F1=AB’+AC+A’BC’
b. F2=(AC+BC)’
22. Explain the Binary ripple counter using JK flip flop and T flip flop.
(OR)
23. a. Explain the operation of master slave D-flip flop.
(7)
b. Construct a JK flip flop using the following components: D flip flop, 2-to-1 multiplexers
and an inverter.
(8)
24. Explain the analysis and design procedure of an Asynchronous sequential circuit.
(OR)
25. Explain in detail about the Race free state assignments.