BLOCK DIAGRAM
Expt.No.:
GENERATION OF PN SEQUENCES
Date:
AIM:
APPARATUS REQUIRED:
S.NO
1.
2.
3.
APPARATUS NAME
IC 7495 & IC7486
LED
RESISTOR
TYPE / RANGE
330Ω
QUANTITY
1
4
4
THEORY:
In any communication system, the modulating techniques are more concerned about the
efficient utilization of bandwidth and transmitted power. There are other applications where it is
necessary for the system to resist external interference and to make it difficult for unauthorized
receivers to receive the message being transmitted. This type of communication is called secure
communication, such that noise interference and unwanted receivers should not detect the
message. Such communication is very important in Military applications where technique called
spread spectrum modulation is used. This is the technique in which a signal is transmitted on a
bandwidth considerably larger than the frequency content of the original information.
The pseudo-noise or pseudo random sequence is a noise like high frequency signal. This
signal is binary in nature. It looks like pulse. The sequence is not completely random but it is
generated by a well-defined logic. The same logic is used at the transmitter and receiver. Since
the sequence is generated by a well-defined logic it is rather ‘pseudo’ random. The pseudo-noise
sequence can be generated by a feedback shift register and the combinational logic. The shift
register consists of 4 flip flops. The data of one is given to the other whenever a clock pulse is
applied. The outputs of the flip flops are given to the logic circuit. Depending upon the output of
flip flops the output of the logic circuit is decided. The logic circuit output is given as input to the
first flip-flop of the register. At each clock pulse, the state of the flip flop is shifted to the next
flip flop and the logic circuit is shifted in the first flip flop.
PIN DIAGRAM:
IC 7495
IC 7495 FUNCTIONAL DIAGRAM:
Data Inputs
Outputs
PERIOD OF PN SEQUENCE:
The pseudo noise sequence generated at the output of the flip flop repeated after 2m
digits. This is because the shift register will have 2m states. Those states start repeating after 2m,
hence output sequence will also repeat after 2m bits. 2m is called period of the output sequence.
When the pseudo-noise sequence generated by linear feedback shift register has the length of 2m1, it is called maximum length sequence.
PROPERTIES:
Balance property:
The number of 1’s is always one more than the number of zeros in each period of a
maximum length sequence.
Run property:
The run means subsequence of identical symbols i.e., 1’s and 0’s within one period of the
sequence. The length of the run is equal to the length of the subsequence. When the maximum
length sequence is generated by feedback shift register of the length m, then the total number of
runs is 2m-1.
Correlation property:
The autocorrelation function of maximum length sequence is periodic and it is binary
valued.
TABULATION:
Properties of PN Sequences
Run Property
Balance Property
Correlation Property
PROCEDURE:
1. Connections are made as per the circuit diagram shown.
2. The input to the first shift register is set as binary ‘1’ so as to generate the PN
sequence.
3. The logic circuit output is given as input to the first register. The output of each shift
register is given to the other.
4. The output of the last stage shift register is taken as PN sequence. This generation of
PN sequence is repeated for every 2N - 1 period of clock pulse where N=4 as the
output of the XOR gate is based on some logic.
5. The properties of PN sequence are verified.
RESULT: