Homework 7
Note: propagation delays do not need to be included.
1) Complete the truth table and timing diagram for the latch circuit below. Note: the “n” after S
and R is used to tell the user the active level. It does not imply inversion. The “n” tells the user
that when S is low and R is high, the latch is “set” (Q = 1).
2) Complete the truth table and timing diagram for the latch circuit below.
3) Complete the timing diagram for the positive-edge triggered JK flip flop. Assume Q starts low.
4) Complete the timing diagram for the negative-edge triggered JK flip flop. Assume Q starts low.
The video at https://www.youtube.com/watch?v=-dpt62XaAQM&t=83s will introduce you to a flip-flop
reset and https://www.youtube.com/watch?v=X-DFxfwzUJ8 covers falling edge clocks.
5) Complete the timing diagram for the circuit with one positive-edge and one negative-edge
triggered D FF. Q1 and Q0 start a low (0) because CLRn starts low.
6) For each set of waveforms, create a D, T or J/K waveform that will generate the desired Q
output. Assume Q starts low. There are several right answers for the J and K inputs. To prevent
flip-flop instability, all changes to the D, T and J/K signals should be made near the falling edge
of the clock.