ELEC 301
Lab 2: Cadence Layout Tutorial (part a)
Version: 8.0
Objective
z To create the mask layout of the inverter defined in lab 2 by using the layout editor Virtuoso.
z To use DRC (Design Rule Checker) for detecting any layout design rule violations.
I. Creating a layout view for the inverter design
You created the schematic view and symbol view of your inverter in lab 1. You are going to create the
corresponding layout view.
1.1. By using the Library Manager, under your design library 301myLib, create the layout view of the
inv cell.
z In the Create New File Form, remember to select “Virtuoso” as the tool to be used.
1.2 With the help of the Layer Selection Window (LSW), you can draw and edit the mask layout.
You should always check for messages shown in the CIW.
Layout editing
window
LSW
CIW
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II. Use of the Layer Selection Window (LSW)
The Layer Selection Window (LSW) shows you which layout layer is being selected for drawing.
For example, if you want to draw poly gate, you have to highlight the “Poly (dg)” field in the LSW,
hence, what you draw then is for the poly mask.
It shows that the Poly (dg)
becomes the current entry
layer
Important Notes:
You have to read the design rules* before drawing anything.
The design rules are listed here
http://www.mosis.org/Technical/Designrules/scmos/ Æ look at the “Table 4: SCMOS Layer Map”.
The meanings of different layers :
Layers’ Name The corresponding names Description
used in LSW in design rule* file.
Nwell
N WELL
The layer to define the n-doped well area, e.g. used for
building PMOS transistors
Oxide
ACTIVE
This layer defines the area for devices e.g. transistor
(it is sometimes called active area/thin oxide layer)
Poly
POLY
Polysilicon layer.
Pimp
P PLUS SELECT
For P+ implantation / diffusion.
Nimp
N PLUS SELECT
For N+ implantation / diffusion.
Cont
CONTACT
Contact layer, for contacting 1st layer metal to polysilicon or
1st layer metal to substrate.
Metal1
METAL1
1st layer metal. e.g. for power and ground wiring.
Via1
VIA
For contacting the 1st layer metal (metal 1) to 2nd layer metal
(Metal2)
Metal2
METAL2
2nd layer metal
Via2
VIA2
For contacting the 2nd layer metal (metal 2) to 3rd layer metal
(Metal3)
Metal3
METAL3
3rd layer metal.
Via3
VIA3
For contacting the 3rd layer metal (metal 3) to 4th layer metal
(Metal4)
text
N.A.
To put text for labeling purpose.
Notes:
(drw)
For layout drawing.
(pin)
For I/O pin definition.
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III. The Virtuoso Layout Editing Window
Very important things on layout drawing,
1. We are using 0.25um technology, the description is ‘0.25u CMOS025 Deep, 6-metal, 1-poly,
silicided, n-well, 2.5/3.3V’.
2. Default unit for layout drawing dimension is micron meter, µm.
3. The design rules (design rule files in the link stated in P.2) and the lambda rule used;
the value of the lambda, λ = 0.12µm for our technology.
4. The resolution for mask making, the finest dimension it can achieve is 0.06µm.
Before drawing the first block in the editing window, you have to set the display option properly by
using the above information!!
• Check the display option and see whether they are appropriate or not.
Click on Options Æ Display
•
The X and Y snap spacing should not be smaller than the finest dimension (the resolution for
mask making) it allows.
.
0.12
0.12
0.06
0.06
These values are very important to your
layout drawing. If you failed to have correct
values above, you may need to redraw
everything then.
Note: we have set above values for you in the
system, it is now the defaults.
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IV. Creating PMOS Transistor Layout
We will guide you how to draw the layout of a PMOS transistor step by step below. In layout view we
use polygons to represent transistors and all device elements. The minimum allowable geometry dimensions
are all listed in Design Rules files (download the file yourself from the website stated in P.2). The value of
lambda (λ) is 0.12 um, and the smallest dimension you can draw is 0.06um. (Note: All drawings below are
not to scale)
n+
Active area
B
G
G
D
p+
G
S
p+
D
S
B
p+
n+
l = 0.24u
w = 3u
nwell
D
P substrate
S
B
nwell
Layout view
PMOS’s cross-section
Schematic view
Step 1. You will draw the PMOS layout in this sequence and the steps below will help you. Oxide (dg)
Nimp (dg)
Layer: Oxide (dg)
Pimp (dg)
S
G
D
S
p+
Layer: Poly (dg)
G
Nwell (dg)
D
S
G
D
p+
N well
1.1. The first thing to drawing is the polysilicon block; click on the ‘Poly (dg)’ box in the LSW first.
• Hence any geometry being drawn is on the polysilicon layer then.
1.2. Click on Create Æ Rectangle to draw the polysilicon gate in the layout editing window.
1.3 You are going to draw the active area (the Oxide layer),
click on ‘Oxide (dg)’ in the LSW first.
2λ (=0.24µm)
S
G
D
Oxide (dg)
25λ (=3µm)
1.4. Draw the blocks with the dimensions as shown in right
• You can use the Ruler to measure the dimension;
Poly (dg)
Click on Window Æ Create Ruler then press F3 for options.
3λ
• To remove the Ruler by Window Æ Delete All Rulers
6λ
• You can also use ‘Stretch’ to help you to extend blocks
in all directions by Edit Æ Stretch
• You can check/change the properties (the size, place & layer) of rectangles by Edit Æ Properties.
(this is a very useful command for drawing or editing shapes, try it out yourself!)
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Step 2. Similar to step 1, continue to draw the blocks with the dimensions as shown.
Nimp (dg)
size: 9λ x 9λ
6λ
Oxide (dg)
size: 5λ x 5λ
n+
Pimp (dg)
6λ
2λ
G
B
6λ
Nwell (dg)
p+
2λ
6λ
nwell
nwell
(Not to scale)
(Not to scale)
V. Design Rule Check (DRC)
In order to lower the probability of fabrication defects, the mask layout must conform to a set of
design rules. You should perform DRC frequently while you are drawing the layout. The tool called Design
Rule Checker, which is built into the layout editor, is used to detect any design rule violations.
Step 3. Use your current layout to run a DRC, Assura Æ Run DRC, the DRC form will appear
And change the settings as below, then click on ’OK’ to start the checking.
Type in ‘./drc’ there, hence all the DRC
related files will be stored under this directory.
To select the DRC rules files to use
Type in’ drc?’ there.
3.1 It may take some time to finish the checking. As it finished, windows will prompt out automatically,
then click on ‘Yes’ to see the result. If there is error, you have to correct it at once, and then do the
DRC again to verify. The DRC checker (the Error Layer Window) will tell you what the errors are,
and can help you to locate them. Please ask TA for help if necessary
3.2 If there is no error or you have fixed all the errors, you can proceed to the next part - wiring the
transistor.
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VI. Wiring the Transistor
You now have a PMOS transistor layout, which has passed DRC. Then we will wire the transistor with
Metal 1 and
contact.
1.5um
the corresponding
layout view
W=3u
L=240.00n
W=1.2u
L=240.00n
Metal 1;
Metal1 (dg)
contact;
Cont (dg)
1. Step 4.
In the layout use the first layer metal, Metal 1
for wiring ; draw some contacts (Cont (dg)) and then put
the Metal 1 (Metal1 (dg)) layer above them. In your layout, the width of Metal 1 for power rail
must be set to 1.5µm in height.
To draw the contacts and metal 1 wires as above, you have to determine their dimension/spacing
constraints by checking the design rules of contact layer and metal 1 layer yourself, then undergo
DRC to check for any errors, fix them for any. (The design rules of 5.4, 6.1, 6.2, 6.3 & 7.3 may
help)
VII. Creating NMOS Transistor Layout
You are going to draw the NMOS layout.
Step 5
Using the similar procedure as drawing PMOS, draw the NMOS transistor as shown below and
put it below the PMOS transistor. The gate width of NMOS should be 10λ (1.2µm).
•
Run the DRC, and fix errors if there is any.
Nimp ( dg)
W=3u
L=240.00n
Oxide (dg)
Pimp ( dg)
W=1.2u
L=240.00n
1.5um
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VIII. Connecting NMOS and PMOS Transistors Together
You have finished the NMOS and PMOS transistors of the inv cell. Make sure they are DRC pass. The
next step is to make the internal and the external connection for the inv layout view.
W=3u
L=240.00n
W=1.2u
L=240.00n
to be connected
connected
The connections for the transistors’ layout should match
with its schematic view as above.
Step 6
As above pictures, connect the two transistors’ Poly rectangles together (their Gate terminals are
then connected), and connect the two transistors’ Metal1 rectangles together (their Drain
terminals are then connected).
• To do so, we can use the Edit Æ Stretch to help.
Refer to the above pictures for correct connections.
6.1. To made connections for external circuit (for input pin A and output pin Out):
Make the interconnection as shown below, determine the dimensions by checking the design rules of
contact, via1, metal 1 and metal 2 layers yourself, then undergo DRC to check for any errors.
Poly.
Cross-section 1
Cross-section 2
Metal2
zoom in
Via1
Metal2
Via1
Metal1
Cross-section 2
Metal1
Cont (contact)
Poly
Cross-section 1
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These Design rules may be useful to you:
5.1, 5.2, 7.3, 8.1, 8.3 and 9.3.
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IX. Labeling
Step 7. Create Power, Ground and pin labels for identification purpose.
•
•
•
•
In LSW, select layer text (dg).
In layout window. Click on Create Æ Label.
Fill in ‘vdd!’ as the label’s name, then place it on the upper metal1 power rail as shown in the
figure below.
Place ‘gnd!’, ‘A’ and ‘Out’ with the same procedure.
Step 8. Run DRC again and check for any error, and correct them if there is any.
Power rail
n-well plug
Signal in
P-substrate contact
Ground rail
Signal out
label
Area of the Layout
To find the area of the layout, click on Design Æ Properties, the coordinates of the boundary box of
your layout will be shown. For example, in this case, the area of the layout = 3.12*11.051=34.479um2.
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X. Setting Layer Visibility and Selectivity using the LSW
You have basically finished the inv layout. However, you may want to check/look into the transistor
design layer by layer. The Layer Selection Window (LSW) allows you to set particular layers selectable
and visible.
Step 9. To make the layers invisible, click on the ‘Metal1 (drw)’ in the LSW. Then click on ‘NV’ button
at the top, then ‘Window’ Æ ‘Redraw’ in the layout editing window to refresh the screen.
• Note that except the Metal1 layer all other layers are hidden. To show the hidden layers,
click on ‘AV’ button and click on ‘Window’ Æ ‘Redraw’.
(AV : all visible; NV: Not visible)
Step 10. To make the layer unselectable (inactive), move the cursor over the ‘Metal1 (drw)’ in the LSW
then click the right mouse button. The function is very useful if there are too many layer
overlapping each other.
•
The right mouse button toggles layer selectivity, try it out! If ‘Metal1 (drw)’ field’s
background color grows grey, it means that the layer is now being unselectable (inactive) in
the layout window. If you right click on it one more time, it will become active again. These
functions can also be applied by clicking on the ‘NS’ and ‘AS’ buttons (AS : All selectable,
NS: Not selectable).
Step 11. Well done!! Please proceed to Lab2b!
The End of Lab2a
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ELEC 301
Lab 2: Cadence Layout Tutorial (part b)
Version: 6.1
Objective
• To complete the inverter’s layout by establishing inverter’s external connections (vdd!, gnd!, A &
Out) using Pins.
• To check any inconsistency between the inverter’s layout and its schematic views by LVS (Layout
verus Schematic Check).
• To create the layout view of your nand2 cell and perform DRC and LVS.
• To design a buffer, create its schematic, symbol, layout and perform LVS.
I. Creating Pins in Layout View
You finished the layout drawing in lab2a. In this part, pins will be defined and drawn, then the
layout design is completed. Pins locate where to connect from a cell/instance/block to the ‘outside world’
(external connections), and different names are given for pins of different purposes. There are total 4
pins in our inverter, the inv schematic view, they are vdd!, gnd!, A and Out.
W=3u
L=240.00n
W=1.2u
L=240.00n
The schematic view
pin :
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To create pins, open the layout view of the inv cell,
•
•
In LSW, select the layer ‘Metal 1 (pn)’ (this is a key step!) . ‘Metal 1 (pn)’ stands for pin
defining (pn : pin) on Metal 1 layer.
In the layout editing window, click on Create Æ Pin, and this form pops up,
Click on ‘shape pin’, then
this form pops up.
type in the pin’s name,
“vdd!” here.
click this button for
displaying the pin’s
name in the layout.
•
In the Create Shape Pin form, type in the pin’s name ‘vdd!’, and select the correct I/O
type ‘inputOutput’, then draw a pin-rectangle on the layout as shown in page 1.
•
The size of the pin-rectangle is NOT important, any size is alright. This rectangle is
only used to indicate where vdd! is connected to.
To create pin for gnd! in the same way, the I/O type is ‘inputOutput’.
To create pin for A and Out in the same way but the I/O type should be changed to
•
•
‘input’ and ‘output’ respectively, and the layer used should be “Metal 2 (pn)”
Well done!! You have finished the inverter layout design, then you have to run the DRC again to ensure
it passes the DRC. We are going to perform the Layout verus Schematic check (LVS), i.e. to ensure what
we draw in the layout is exactly the same as what we defined in the schematic view.
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II. Layout versus Schematic Check (LVS Check)
You are ready to carry out the Layout versus Schematic Check (LVS). It is an important step
because the layout drawing is based on its schematic, the devices’ dimensions and connection in the
layout should be consistent with that in the schematic. In order to ensure the layout design is matched
with its schematic view totally, the layout versus schematic check (LVS) must be performed.
The layout view represents the circuit topology, which consists of layers of rectangles only! How
can the system recognise devices and their connectivity in the layout view? While LVS is running,
Cadence will look for the technology file which contains the electrical rules. These rules define
structures, for example if there are overlapping of poly layer, Nimp layer and Oxide layer in some ways,
that will be considered as a NMOS transistor. Therefore, gates and electrical connections are traced out
and identify from its layout view. After all, the layout and schematic view can be compared then.
Step 3. To start the LVS, in the layout view, click on Assura Æ Run LVS. Use the settings as below.
Type in ‘./lvs’ there,
hence all the LVS related
files will be stored under
this directory.
Type in’ extract?’ here.
•
A debug window will prompt out automatically as the LVS check finished. As the schematic view
matched its layout view, the message “Schematic and
Layout Match” would showed,
otherwise, mismatches would be listed out.
This debug window would then guide you to
debug schematic and layout views. Ask for help if
necessary. Click on Assura Æ LVS Error Report to
have a summary on errors found, you may find them
useful.
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III. Creating the Layout of the 2-input NAND gate
You built the schematic view of the nand2 cell in lab 3. You can now start drawing the nand2
layout view. The nand2 layout may look like below (for your reference only!!).
Hint: you have finished a DRC passed inverter’s layout, modify that layout to nand2’s layout.
Read below messages carefully,
1. In your layout, the ground and power rails must be set to 1.5μm in height.
(as shown in the picture below).
2. You have to use Metal 1 for ground and power rails, and Metal 2 for connecting external circuit
at Pins A , B and Out.
Schematic view
Power rail
Layout view
μm
W=3u
L=240n
W=3u
L=240n
W=1.2u
L=240n
W=1.2u
L=240n
height
Ground rail
width
μm
Step 6: Perform LVS. Correct mismatches if there are any. The nand2’s layout must match its
schematic view. Ask for help if necessary.
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IV. Standard-cells based design
We have developed some commonly used logic cells; inverter, buffer and nand gate in our
301myLib library. All the cells’ layouts should be designed with a fixed height so that they can be
abutted side by side to forms rows for sharing a common power and ground bus. Moreover, these fixed
height cells can enable automated placement and routing of cells.
Step 1.
Readjust the layouts of inv cell and nand2 cell to the same height.
• Re-run DRC and LVS checks to make sure all views are correct and updated.
The End of Lab2 (part b)
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Appendix I: More about LVS
If the LVS checker reports that your schematic and layout do not match each other, you have to
find, check and correct those errors.
To know what are unmatched, you have to understand the terms used in the debug window:
Instance - The instance of devices in ‘layout’ and in ‘schematic’.
Unmatched instances - The instance of devices in ‘layout’ and in ‘schematic’ that unmatched
with each other.
Rewired instances - LVS recognizes that a better match can be made by switching the terminal
connection of an instance from one net to another. This is referred to as a rewired terminal. For
this to occur, many of the instances and nets in the local region must have already matched. This
kind of error occurs when two nets are cross-wired. The LVS program interchanges the
connection and continues processing.
Size errors – Size Difference in W & L values, LVS compares transistors’ W & L values only
when the instances are matched with each other in its schematic and layout. Any unmatched
instances will not be compared.
Pruned instances - You may ignore this error.
Nets – interconnection node.
Merged nets - A second class of unmatched nets is the merged nets. In some cases, LVS
recognizes that two nets need to be “shorted” together to improve the comparison. This occurs
when many of the instances attached to the nets have already matched. When two nets need to be
merged in the extracted representation, it indicates the possibility of an open. When two nets are
merged in the schematic representation, it indicates the possibility of a short in the layout.
Pruned nets - You may ignore this errors.
Terminals – pins for input, output and power.
Unmatched terminals - Terminals (Pins) that failed to match in layout as compared those in
schematic.
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