Microelectronics
LOGIC SYNTHESIS
OF
VLSI CIRCUITS
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Enabling and strategic technology.
Primary markets:
{ Information systems.
{ Telecommunications.
{ Consumer.
c Giovanni De Micheli
Stanford University
Secondary markets:
{ Systems (e.g., transportation).
{ Manufacturing (e.g., robots).
Computer-Aided Design
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Electronic market
Enabling design methodology.
Makes electronic design possible:
{ Large scale design management.
{ Design optimization.
{ Reduced design time.
Application of VSLI circuit technology.
Key strategic importance.
SYSTEMS
ELECTRONIC
SUB−SYSTEMS
INTEGRATED
CIRCUITS
EDA
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Moore's law
Trends in microelectronics
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Improvements in device technology:
{ Smaller circuits.
{ Higher performance.
{ More devices on a chip.
PENTIUM−II
7
10
PENTIUM
PENTIUM−III
P−PRO
D−AXP
I−486
6
10
I−386
M−68020
I−286
5
10
I−186
M−68000
10 4
I−8086
3
10
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Higher degree of integration.
10
I−8080
2
I−8008
10
{ More complex systems.
{ Lower cost of computation.
{ Higher reliability.
1
1960
1965
1970
1975
1980
1985
1990
1995
2000
Integration-scale limitations
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Intrinsic physical scaling limits.
Capital investment for fabrication.
Microelectronic design problems
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{ To be competitive in performance.
{ Use of appropriate design styles.
Large-scale design management.
Use most recent technologies.
Reduce design cost.
{ To be competitive in price.
{ Use of CAD design tools.
Speed-up design time.
{ Time-to-market is critical.
Microelectronic economics
Microelectronic circuits
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Design cost:
{ Design time and fabrication cost.
{ Large capital investment.
{ Near impossibility to repair.
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General-purpose processors:
{ High-volume sales.
{ High performance.
Application-Specic Integrated Circuits (ASICs):
{ Varying volumes and performances.
Recapture costs:
{ Large volume production is benecial.
{ Zero-defect designs are essential.
{ Follow market evolution.
Prototypes.
Special applications (e.g. space).
Microelectronic design styles
Semicustom design
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Adapt circuit design style to
market requirements:
SEMI−CUSTOM
Parameters:
{ Cost.
{ Performance.
{ Volume.
Custom and semi-custom design.
CELL−BASED
CELL−BASED
STANDARD−CELLS
Hierarchical cells
Hierarchical cells
ARRAY−BASED
MACRO−CELLS
PRE−DIFFUSED
PRE−WIRED
Memory generators
PLA generators
Sparse logic generators
Gate matrix generators
Gate arrays
Sea of gates
Compacted arrays
Anti−fuse based
Memory−based
Standard cells
Macro-cells
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Cell library:
Layout style:
MPGAs
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Pre-diused arrays:
{ Personalization by metalization/contacts.
{ Mask-Programmable Gate-Arrays.
Features:
{ Layout can be highly optimized.
{ Structured-custom design.
Compatible with macro-cells (e.g. RAMs).
Array-based design
Examples:
{ RAMs, ROMs, PLAs, general logic blocks.
{ Cells are placed in rows.
{ Channels are used for wiring.
Module generators:
{ Synthesized layout.
{ Variable area and aspect-ratio.
{ Cells are designed once.
{ Cells are highly optimized.
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Pre-wired arrays:
{ Personalization on the eld.
{ Field-Programmable Gate-Arrays.
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Array of sites:
{ Each site is a set of transistors.
Batches of wafers can be pre-fabricated.
Few masks to personalize chip.
Lower cost than cell-based design.
FPGAs
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Semi-custom style trade-o
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Array of cells:
{ Each cell performs a logic function.
Personalization:
Density
Performance
Flexibility
Design time
Man. time
Cost - lv
Cost - hv
{ Soft: memory cell (e.g. Xilinx).
{ Hard: Anti-fuse (e.g. Actel).
Immediate turn-around (for low volumes).
Inferior performances and density.
Good for prototyping.
Custom
Very High
Very High
Very High
Very Long
Medium
Very High
Low
Cell-based
High
High
High
Short
Medium
High
Low
Pre-di.
High
High
Medium
Short
Short
High
Low
Pre-wired
Medium-Low
Medium-Low
Low
Very Short
Very Short
Low
Medium-High
Microelectronic circuit design and
production
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Microelectronic circuit design
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DESIGN
TESTING
idea
MODELING
SYNTHESIS &
OPTIMIZATION
tester
FABRICATION
MASK
FABRICATION
WAFER
FABRICATION
{ Hardware Description Languages (HDLs).
10000
01001
11100
VALIDATION
Conceptualization and modeling:
Synthesis and optimization:
{ Model renement.
PACKAGING
SLICING
PACKAGING
Validation:
{ Check for correctness.
Modeling abstractions
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Modeling abstractions
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ARCHITECTURAL LEVEL
...
PC = PC + 1;
FETCH (PC);
DECODE (INST);
...
Architectural level:
{ Operations implemented by resources.
LOGIC LEVEL
Logic level:
{ Logic functions implemented by gates.
GEOMETRICAL LEVEL
{ Devices are geometrical objects.
Modeling views
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be
ha
w
ie
vi
v
al
or
al
vi
r
tu
Modeling views
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Behavioral view:
{ Abstract function.
c
ru
st
ew
Geometrical level:
Structural view:
physical view
{ An interconnection of parts.
Physical view:
{ Physical objects with size and positions.
Circuit synthesis
Modeling views and abstractions
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b−view
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Architectural-level synthesis:
{ Determine the macroscopic structure:
s−view
Interconnection of major building blocks.
a−level
Logic-level synthesis:
{ Determine the microscopic structure:
l−level
g−level
p−view
Interconnection of logic gates.
Geometrical-level synthesis:
(Physical design)
{ Determine positions and connections.
Modeling views
Microelectronic circuit optimization
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b−view
{ Delay and cycle-time.
{ Latency.
{ Throughput (for pipeline applications).
s−view
a−synthesis
a−level
l−synthesis
l−level
g−level
Performance:
Power consumption.
Area (yield and packaging cost).
Testability.
p−design
p−view
Design space and evaluation space
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Optimization trade-o in combinational
circuits
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Area
EVALUATION
FUNCTION
DESIGN
Cycle−time
SPACE
Area
Area
Max
Latency
Delay
Delay
Max
Optimization trade-o in sequential
circuits
Pareto points
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Area
Area
Cy
cl
e−
t
Multi-criteria optimization.
Multiple objectives.
Pareto point:
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e
im
Area
Area
Max
Cy
cl
t
e−
im
e
Latency
Latency
Latency
Latency
Max
{ A point of the design space is a Pareto
point if there is no other point with:
at least one inferior objectives.
all other objectives inferior or equal.
Example
design space
Example
design evaluation space
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Area
7
(a)
6
a
(c,d)
b
(b)
5
4
3
c
d
2
1
Delay
Implement f = p q r s with:
1
{ 2-input or 3-input AND gates.
Area and delay proportional to number of inputs.
Summary
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Computer-aided design methodology:
{ Capture design by HDL models.
{ Synthesize more detailed abstractions.
{ Optimize circuit parameters.
Logic synthesis and optimization:
{ Manipulate and optimize circuit models at
the logic abstraction levels.
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