VLSI Design
12. Design Styles
Logic Transistors per Chip (K)
• Last module:
– Floorplanning
– Sequential circuit design
– Clock skew
• This module
10,000,000
Logic Transistors/Chip
100,000,000
.10m 1,000,000
Transistor/Staff Month
10,000,000
100,000
.35m
1,000,000
58%/Yr. compound
Complexity growth rate
10,000
100,000
1,000
10,000
X
100
X x
2.5m
10
– Custom and semi-custom design
– Array-based implementations
X X
1,000
X
X
100
21%/Yr. compound
Productivity growth rate
P r o d
u vcti ti y
1
(T r n
a s /. S
t a f -M
Productivity (Trans./Staff-Month)
The Design Productivity Challenge
12. Design Styles
o n
t h )
2 0 0 7
2 0 0 9
2009
2 0 0 5
2007
2 0 0 1
2005
2003
1 9 9 9
2001
1999
1997
1 9 9 3
1995
1 9 9 1
1993
1 9 8 7
1991
1 9 8 5
1989
1987
1985
1983
1981
10
A growing gap between design complexity and design productivity
Source: sematech97
© Digital Integrated Circuits2nd
12. Design Styles 1
Impact of Implementation Choices
Configurable/Parameterizable
10-100
Hardwired custom
Energy Efficiency (in MOPS/mW)
100-1000
Embedded microprocessor
A System-on-a-Chip: Example
Courtesy: Philips
12. Design Styles 2
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Domain-specific processor
(e.g. DSP)
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1-10
0.1-1
Somewhat
flexible
None
Fully
flexible
Flexibility
(or application scope)
© Digital Integrated Circuits2nd
© Digital Integrated Circuits2nd
12. Design Styles 3
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12. Design Styles 4
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Design Methodology
Implementation Choices
Digital Circuit Implementation Approaches
Custom
Semicustom
Cell-based
Array-based
Source: Gajski
Standard Cells
Compiled Cells
• Design process traverses iteratively between three abstractions:
behavior, structure, and geometry
• More and more automation for each of these steps
© Digital Integrated Circuits2nd
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12. Design Styles 5
Macro Cells
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
© Digital Integrated Circuits2nd
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12. Design Styles 6
1
VLSI Design
12. Design Styles
The Custom Approach
Transition to Automation and Regular Structures
Intel 4004
Intel 4004 (‘
(‘71)
Intel 8080
Intel 8085
Intel 8286
© Digital Integrated Circuits2nd
Courtesy Intel
© Digital Integrated Circuits2nd
12. Design Styles 7
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Cell-based Design (or standard cells)
Rows of cells
Feedthrough cell
Courtesy Intel
Intel 8486
12. Design Styles 8
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Standard Cell — Example
Logic cell
Routing
channel
Functional
module
(RAM,
multiplier, …)
Routing channel
requirements are
reduced by presence
of more interconnect
layers
[Brodersen92]
© Digital Integrated Circuits2nd
© Digital Integrated Circuits2nd
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12. Design Styles 9
Standard Cell – The New Generation
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12. Design Styles 10
Standard Cell - Example
Cell-structure
hidden under
interconnect layers
3-input NAND cell
(from ST Microelectronics):
C = Load capacitance
T = input rise/fall time
© Digital Integrated Circuits2nd
© Digital Integrated Circuits2nd
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12. Design Styles 11
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12. Design Styles 12
2
VLSI Design
12. Design Styles
Automatic Cell Generation
Initial transistor
geometries
Placed
transistors
© Digital Integrated Circuits2nd
Routed
cell
Compacted
cell
MacroModules
Finished
cell
Courtesy Cadabra
© Digital Integrated Circuits2nd
12. Design Styles 13
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“Soft” MacroModules
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A Protocol Processor for Wireless
Synopsys DesignCompiler
© Digital Integrated Circuits2nd
12. Design Styles 15
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Semicustom Design Flow
Design Capture
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12. Design Styles 16
The “Design Closure” Problem
Behavioral
HDL
HDL
Pre-Layout
Pre-Layout
Simulation
Simulation
Structural
Logic
LogicSynthesis
Synthesis
Post-Layout
Post-Layout
Simulation
Simulation
Circuit
CircuitExtraction
Extraction
Floorplanning
Floorplanning
Placement
Placement
Physical
Routing
Routing
Iterative Removal of Timing Violations (white lines)
Tape-out
© Digital Integrated Circuits2nd
© Digital Integrated Circuits2nd
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12. Design Styles 14
“Intellectual Property” (IP) Cores
© Digital Integrated Circuits2nd
Design Iteration
256×32 (or 8192 bit) SRAM
Generated by hard-macro module generator
12. Design Styles 17
Courtesy Synopsys
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12. Design Styles 18
3
VLSI Design
12. Design Styles
Integrating Synthesis with
Physical Design
Late-Binding Implementation
RTL (Timing) Constraints
Physical
PhysicalSynthesis
Synthesis
Macromodules
Fixed netlists
Array-based
Netlist with
Place-and-Route Info
Pre-diffused
(Gate Arrays)
Pre-wired
(FPGA's)
Place-and-Route
Place-and-Route
Optimization
Optimization
Artwork
© Digital Integrated Circuits2nd
© Digital Integrated Circuits2nd
12. Design Styles 19
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Gate Array — Sea-of-gates
12. Design Styles 20
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Sea-of-gate Primitive Cells
polysilicon
Oxide-isolation
VD D
PMOS
metal
rows of
uncommitted
cells
possible
contact
GND
Uncommited
Cell
PMOS
NMOS
In 1 In2
In 3 In4
routing
channel
NMOS
NMOS
Committed
Cell
(4-input NOR)
Out
Using oxide-isolation
© Digital Integrated Circuits2nd
12. Design Styles 21
D. Z. Pan
Example: Base Cell of Gate-Isolated GA
VDD
continuous
p-diff strip
continuous
n-diff strip
contact for
isolator
GND
© Digital Integrated Circuits2nd
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3
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7
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9
10
11
12
13
14
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16
17
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21
12. Design Styles 22
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Example: Flip-Flop in Gate-Isolated GA
VDD
CLR
Q
CLK
n-well
p-well
n-diff
p-diff
poly
m1
m2
contact
Q
D
GND
From Smith97
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Using gate-isolation
© Digital Integrated Circuits2nd
© Digital Integrated Circuits2nd
12. Design Styles 23
From Smith97
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12. Design Styles 24
4
VLSI Design
12. Design Styles
Sea-of-gates
Prewired Arrays
Random Logic
Classification of prewired arrays (or fieldprogrammable devices):
• Based on Programming Technique
– Fuse-based (program-once)
– Non-volatile EPROM based
– RAM based
• Programmable Logic Style
– Array-Based
– Look-up Table
• Programmable Interconnect Style
Memory
Subsystem
– Channel-routing
– Mesh networks
LSI Logic LEA300K
(0.6 μm CMOS)
© Digital Integrated Circuits2nd
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© Digital Integrated Circuits2nd
Courtesy LSI Logic
12. Design Styles 25
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12. Design Styles 26
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