Special Feature
Increasing signal
visibility in
FPGA-based prototypes
By George Bakewell
y
l
n
O
t
n
i
r
P
e
l
g
n
i
S
r
o
F
rototyping complex ASIC systems with
emulation and FPGA prototypes requires
hardware and software operating in tandem
within embedded processor-based devices.
While these methods provide greater verification
bandwidth, their use creates issues with operational
debug and analysis that can be addressed through new
visibility enhancement techniques and tools.
Inherent in silicon is the extremely limited signal access that hinders
visibility into the internal workings of the device. FPGA debug
methods such as “multiplexing to outputs” require significant
resources to gain the smallest insight into the silicon. Internal
Logic Analyzers (ILA) are structured, but are more suitable for
understanding architectural registers rather than combinational
logic. These methods require a “trial and error” approach since the
engineer may not initially know what part of the design needs to be
examined. By contrast, visibility-enhanced debug flow approaches
such as those shown in Figure 1 automate the process of extracting
and analyzing data to provide full observability. These approaches
also ease FPGA debug through a series of steps:
» Implement Design for Debug (DFD) logic in the FPGA to
enhance the ability to retrieve crucial signal data.
» Retrieve data while the FPGA is operating in-situ.
» Map retrieved data to the RTL so the designer can
understand the behavior.
» Expand signal data by computing values that were not
captured from silicon to enable deep analysis techniques.
Optimal signal selection
The first step in the process is to decide which signals need to be
observed. Commercial ILA solutions – such as the ChipScope
analyzer from Xilinx – usually consist of mechanisms to access
internal signals and optional mechanisms for event triggering
when the FPGA is operationally executing. This provides a way
to bring out a limited set of internal signal values for observation,
but leaves it to the user to determine the best points to observe.
Visibility enhancement technology enables an analysis-driven
approach that guides the observability decision process:
» Determine the blocks and/or levels of hierarchy for
observation.
» Seed the process with a list the signals that must always
be observed.
Figure 1
www.DSP–FPGA.com
Programmable Logic
© 2007 OpenSystems Publishing
Not for distribution
Special Feature
»
Analyze the blocks to determine an optimal set of remaining
signals that should also be observed to provide full visibility
therein.
» Provide the combined list of signals to the ILA insertion
process.
Visibility-enhanced signal selection also introduces the concept
of “influence-ability” (the amount of downstream logic each
signal influences). The design description and related code is
analyzed in order to prioritize signal selection based on userprovided settings. The visibility-enhanced signal selection tool
will first automatically identify any registers, memory elements,
and primary I/Os that must be captured in order to observe the
specified internal signals, and then round out the list based on
available resources.
graph-matching algorithms to generate a file that maps the gatelevel signals to the RTL. The map file can then be used with the
RTL design and gate-level simulation results to correlate the
captured signal data from one domain to the other. In Figure 2, the
gates and values (shown on the left) are expanded and correlated
to the corresponding RTL (right). This example shows that the
ALU is performing an ADD function.
Viewing unobserved values – data expansion
Designers often want to display and analyze signals that were
not in the captured set, and the retrieved data is typically limited
to values from a set of registers. Data expansion techniques
interpolate missing data by populating the signals internal to
blocks of combinational logic that sit between registers whose
signals were captured for that time-span in a cycle-accurate
fashion. The expansion is done “on demand” only for the logic
under investigation rather than statically for all design logic to
maximize performance.
y
l
n
O
t
n
i
r
P
e
l
g
n
i
S
r
o
F
“Value” proposition
Retrieving signal values – data format
With the observability logic in place, information required by
downstream analysis and debug environments is automatically
recorded during the verification run, including logic values, the
full hierarchical instance name of the signal, and the relative
operational times of any data transitions. In the event that there
are not sufficient resources to capture all of the desired signals,
the selection will be based on those signals that are deemed to
have more influence as discussed above. The extracted data is then
written to a file using an industry standard format such as the Value
Change Dump (VCD) format or the popular Fast Signal Database
(FSDB) from Novas that captures results from simulators and
other verification tools through an open application programming
interface.
Viewing values at the RTL – mapping rules
Data from ILAs is usually associated with the gate-level view of
the FPGA, and not every signal in the gate-level representation will
have a corresponding signal in the RTL. Visibility-enhancement
techniques localize signal correspondence in order to represent
low-level data at the RTL. One such technique is to automatically
generate structural dependency graphs and employ approximate
Advanced analysis
Advanced debug techniques normally applied on software simulation results can also be applied to the FPGA results. For
example, if the target device contains internal buses, the expanded
data could be viewed at the transaction level, making it easier to
understand the actual operation. Careful integration of the data
expansion engine with the debug system could provide both time
and file size reductions and enable automated, guided debug with
its advanced analysis and tracing techniques (see Figure 3).
Conclusion
Visibility enhancement techniques for FPGA prototype and
emulation of ASIC systems apply automation to the process of
locating, isolating, and understanding the causes of errors. A
small amount of upfront logic implementation provides silicon
data access, while RTL mapping and data expansion enable full
visibility using just the essential signal data. Combined with
sophisticated debug engines, the net result of these techniques is
faster debug of functional errors and system verification.
George Bakewell is
Director of Product
and Technical
Marketing at Novas
Software, Inc. He
is responsible for
product management
and technical direction
of sophisticated design debug automation
systems, and works closely with R&D on
product specifications. He has presented
at technical conferences, industry standard
organizations, and personally conducted
in-depth tutorials and application workshops. George has 20 years of experience
in the EDA industry, and holds a BS in
Electronic Engineering and Computer
Science from the University of Colorado.
Figure 2
Novas
2025 Gateway Place, Suite 400
San Jose, CA 95110
408-467-7888
Website: www.novas.com
Figure 3
www.DSP–FPGA.com
Programmable Logic
© 2007 OpenSystems Publishing
Not for distribution