Presenter : Shao-Chieh Hou
In this paper we present a software/hardware co-debug
platform to deal with the various debug problems in multiplecore SOC systems with multiple-clock domains. This platform
allows designers to debug embedded processors, buses, IP
cores, as well as the application programs being developed. It
can be used at various design and manufacturing stages
including component development, hardware/software codesign, system prototyping, and post-silicon debugging. Three
major mechanisms are integrated into this platform, namely a
software debug mechanism for multi-core programming, an onchip hardware debug mechanism for various hardware IPs,
and a two-way cross trigger mechanism to synchronize the
debug processes of software and hardware. Experimental
results on a FPGA prototyping board demonstrate the
effectiveness and efficiency of this platform in identifying the
root causes of failures for multiple-core SOC systems with
multiple-clock domains.
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SoC become more and more complex
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SoC is not only hardware, but also software
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Many function IPs
homogeneous/heterogeneous core integrate
To find problem in HW or SW is waste time
Breakpoint is always in SW, not in HW
If the IP is Write-only, the coresight is no use
Simulation may be a solution, but
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Not all problem happened in simulation
Error happens in FPGA or real chip
3D Depth Map
App[10]
Bus information
Dump[9]
Processor
Debug[6]
Experiment environment
SoC Debug[2][3]
CoreSight[4]
Use Method
This paper
IP Phase
Debug[5][8]
Multi-Core
Multi Thread Program
Trigger at difference time
1500-base internal
Scan Chain Wrapper
HW Trace/Control
center
If IP is Write-only
=>Scan base debug
Multi-Cycle SoC
=>Break point should at “safe” time
SW-oriented
Input in SW, send by CTM through CTI0 to CTI1.
The signal input into TAM controller.
By BKT controller, the HW is also setup.
HW-oriented
Input in HW, send by CTM through CTI1 to CTI0.
The signal output into TAM controller.
By ICE, the SW is also setup.
4 ARM11 Core, 1video decoder, 2CTM and 5 CTI
3D depth map generator:
Add 3D depth to 2D video
Perform
3D depth
Perform
Video
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The paper proposed a SW/HW Co-debugger
platform for SoC
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Multi-core
Multi-clock
The Platform can be use in FPGA, and postsilicon test
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The architecture for the paper is useful for our
platform
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1500Wrapper->Wrapper ICE
ETM->Tracer and Program Trace or ICE
Cross Trigger
Unfortunately, the paper doesn’t give us
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Experiment result
Detail IP information
Detail mechanism for integrate
Calculated
address and
allows TAM
controller to
access
memory
Send enable
signal to
core while
TAM like a
slave
For scan
wrapper
setup and
output
Break-Point
Setup
Controller
Generate
1149.1 control
signal for scan