Issue 5 | July 2001
Business & Technical news
from Unaxis Semiconductors
■
China – the Rising Star
in Semiconductor Heaven
■
Turbocharged Silicon
SiGe Ready for Take-Off
Dr. Martin Bader, Executive Vice President, Unaxis Semiconductors
and President Unaxis North America
Dear Readers,
We welcome you again to a new edition of Chip, aiming – as always – to keep you
informed of market developments, new Unaxis products and process innovations.
The most exciting recent development is the accelerated interest in SiGe for
chip production. Having existed for decades as a niche segment, it is now poised
to take off – hand in hand with the demand for ever greater speed in new
telecommunications equipment and wireless networking. From signal testing equipment
to video-enabled mobile phones, from wearable electronics to a wireless network
server: the high chip performance rates have opened up boundless possibilities which
are only just beginning to be explored by product designers. In this issue we focus on
the SiGe market (page 21), related technologies and research both from within Unaxis
and our industry partners (pages 24 to 31).
Unaxis Semiconductors has considerably increased its activities in China, therefore
we have decided to dedicate a special feature to this region (page 8). For the next five to
seven years we believe this to become one of the most important semiconductor
markets in the world. Besides the existing Hong Kong office we are currently in the
process of establishing our new China headquarters in Shanghai and a sales and
service office in Beijing until October 2001. A full demonstration facility in Shanghai will
be ready by mid 2002. Our customers in China can look forward to even better field
process support and spare parts availability.
However accurately we may try to forecast our business activities, there is always an
element of uncertainty. In just one area we, as a global company, have the possibility to
determine the future: in our care for the environment. We are conscious of our
responsibility towards society and the future, which is why our commitment to Business
Excellence goes beyond office walls. Environmental issues are an integral part of the
Unaxis quality policy (page 4).
We hope to meet you personally in the coming weeks and months and wish you
an enjoyable time reading this edition of Chip.
Dr. Martin Bader
Unaxis Chip
7
Unaxis Insights
From ISO 9001 to Business Excellence
Philips Supplier Audit at Maarssen
Grand Opening
in St. Petersburg
The new Customer
Resource Center
was officially opened:
a good reason to
celebrate together
with customers,
suppliers, Unaxis
employees and
senior management
from around the world.
8
China – the
Rising Star in
Semiconductor
Heaven
The fastest growing
economy in Asia
is an increasingly
important player
on the international
semiconductor stage.
14
Successful
Partnership in China
Chip talked to
Mr. Gao Jian Feng,
Senior Engineer
and Deputy Director
of the Nanjing Electronic
Devices Institut (NEDI).
Chip Unaxis
4
An interview with Chris Bezer, who is responsible for supplier
quality at Philips Semiconductors in Hazel Grove, England
5
Unaxis – on the Way to a
“World Class Supplier”
Grand Opening in St.Petersburg
6
7
China – the Rising Star
in Semiconductor Heaven
Successful Partnership in China
Events
8
14
45
21
Compound Semiconductor
Formation of Backside Vias in GaAs
for Advanced MMIC Devices
GaAs based devices are becoming more
common in high frequency circuit designs
Turbocharged Silicon
“Silicon Germanium
(SiGe) is the fastest
growing process
technology of all time”
Electronic Engineering
Times.
16
High Power Productivity
LLS EVO innovations and product enhancements
on a batch sputtering tool
18
Challenging the Manufacturing
on Modern SAW Devices
Unaxis SPTec looks at the processes required
to keep ahead of the pack as an SAW manufacturer
High Speed Silicon
Turbocharged Silicon
Low Energy Plasma Processing
21
There is a tendecy in the semiconductor industry to avoid
plasma processing wherever possible. But LEPP is especially
suitable for applications related to epitaxial growth and
damage free cleaning.
24
UHV-CVD for Low Temperature Epitaxy
of Silicon Germanium
The idea to use SiGe to improve the performance of Silicon
has been around for decades. It has taken until now to gain
ground and to be turned into production scale.
32
19
Magneto Electronics
World Premiere
Dr. Roland Mattheis from
the Institute for Physical
High Technology in Jena,
Germany, writes about
the first C Y B E R I T E 10
target sputtering
machine worldwide
and the symposium
on Magneto Electronics
where the system was
introduced.
27
Virtual SiGe Substrates
High Electron Mobility Transistors on
LEPCVD Grown Virtual SiGe Substrates
Thomas Hackbarth (DaimlerChrysler) and Hans von Känel
(ETH Zürich) have researched how the combination
of different growth technologies like LEPECVD and MBE
enable the realization of SiGe device structures with
excellent performance.
Magneto Electronics
Magneto Electronics World Premiere
Advanced Packaging
How do Wafer Level Packaging
and 300 mm get along?
300 mm wafer level packaging moves out of the shadow
of the 300 mm front end
29
Photomask
New St.Petersburg Research Laboratory
Comes On-Line
The new R&D lab is superbly equipped, featuring
a brand new cleanroom and much more…
32
34
38
Silicon Front End
Electrostatic Chuck to Boost Your Yield
Tight control over substrate contact to the pedestal
is the key to a cluster tool’s process reliability
39
Thin is In
Thinner substrates will win the race for
component performance improvement
44
Unaxis Chip
From ISO 9001
to Business Excellence
Hans Ruedy Wyss,
Business Excellence Manager,
Unaxis Balzers AG
In the 1980s and ’90s the buzzword
in most companies was “ISO 9000”
(International Organization for
Standardization). By now the ISO 9000
certificate as a basic standard has
become a matter of course for any
internationally active manufacturer.
Time moves on and so does the concept
of quality. As the standards and
expectations of our customers were
raised, so was the awareness within the
industry that real, sustainable excellence
can only be achieved through a total
change of heart. Quality can’t be just
managed by a quality department – it
has to become a way of life. Our aim is
to achieve excellence, to be a leader,
to be “Best in Class”. To achieve this goal,
the Unaxis Business Excellence Model
has been developed.
All companies regardless of size,
structure or sector need not only
appropriate management systems to
empower their organization, they also
4 | Chip Unaxis
require the appropriate tools for
measuring and judging every element
of the organization. Practical guidelines
and instruments help measure where
we are at any given time on the path
to excellence. They offer not only the
possibility to measure and judge, but also
help us understand any weakness and
thereby stimulate appropriate solutions.
Excellence is dependent upon
balancing and satisfying the needs of
all relevant stakeholders. This includes
employees, customers, suppliers,
investors and society in general. Through
clarity of communication and unity of
purpose within Unaxis we will achieve
a common orientation and total
commitment to quality. Within this culture
of continuous learning, innovation and
improvement the relationships to our
customers and suppliers will deepen the
mutual trust and prove prosperous for
all stakeholders.
The Unaxis Excellence Model
Following the guidelines of the EFQM
(European Foundation for Quality
Management), the Unaxis model assumes
an all-inclusive approach which considers
all aspects of business management.
A global corporation like Unaxis needs to
consider all sorts of different quality
standards and regulations in order to
become a certified supplier.
In Europe the above mentioned EFQM
defines the basic standards, in the
United States it is the Baldridge National
Quality Program and in Japan the Deming
Prize. On top of these requirements the
individual customers also place demands
on their suppliers, like for instance
Motorola with its QSR or Philips with
the SQS-System.
In order to be able to fulfill these many
demands, we at Unaxis have developed
our own “Business Excellence Model”.
Based on the EFQM requirements,
the Unaxis model has nine key areas
(criteria) which are split between
“Enablers” and “Results”. The “Enablers”
represent what an organization does;
the “Results” represent the achievements
of an organization.
The application of the model
The Unaxis Excellence Model is
primarily a measurement tool for
controlling the process on the path to
Business Excellence. It is an assessment
system which helps to determine a
position and to continuously improve
business processes. The model creates
a common understanding and a common
language within Unaxis for the future
development of the business. This creates
a common awareness about any
necessary action or need for change.
The Unaxis Excellence Model can be
applied to self-assessment, third-party
assessment, benchmarking or as a basis
for the European Quality Award.
Assessments help us to improve our
working relationships and cooperation and
to define areas that need to be addressed
in our continuous improvement process.
They take place during workshops which
incorporate representatives of all groups
and departments involved. These
workshops are an important
communications platform for the
exchange of experience between all
employees as well as different units of the
organization, departments and locations.
Philips Supplier Audit
at Unaxis Maarssen
Interview with Chris Bezer,
Philips Semiconductors
Chris Bezer is responsible for supplier
quality at Philips Semiconductors Hazel
Grove. He carried out the audit according
to the Philips Supplier Quality System
(SQS). Beyond the bare facts of the audit
report we asked him about the auditor’s
view and his personal impressions on the
audit at Unaxis.
What are the Philips objectives in
auditing the suppliers?
Philips SQS audits are an essential tool
in the selection and qualification process
of our suppliers, they encourage the
development of long term mutually
supportive relationships. More effective and
efficient systems result in better quality and
lower defect levels, which in turn reduce
incoming inspection, inventory, lead times
and last, but not least, operational costs.
In a rapidly advancing industry like ours it
is important that all those involved in
the supply chain understand the needs of
each other and the end customer. Audits
help us to work together in better ways and
to continuously improve, reducing the
cost of ownership of the materials and
equipment used.
What is the difference between
ISO 9001 and the requirements of
the Philips SQS system?
Philips SQS is a more rigorous system than
ISO 9001 and investigates the integrity of
both business & manufacturing processes
together with other aspects including a
supplier’s environmental management
system.
Besides ISO 9001 requirements the
SQS contains detailed information on using
statistical tools, process control, defect
prevention, problem solving, customer
complaint handling and some end user
specific requirements for which evidence
of continuous improvement is essential.
The SQS includes elements of QS 9000
which is widely used in the automotive
industry and a requirement for customers
such as Philips.
What does the supplier have to achieve
in order to get certified?
Within the Philips SQS standard a
quantitative scoring system for each of
the 20 elements of the quality system
is defined. A supplier is required to
demonstrate an overall score in excess
of 75% with no outstanding corrective
actions from the audit, and to have a high
level of achievement in seven key areas
which include management responsibility,
process control and process design,
manufacturing and the handling of failures.
How did Unaxis fare in comparison
to other Philips Semiconductors
suppliers?
The visit to Maarssen in January 2001 was
the first time a Philips SQS audit had been
conducted there. Such a first visit is the
start of a learning process during which
the Philips requirements are clarified and
a first assessment is made as to the gaps
between the supplier’s systems and Philips
requirements. The audit resulted in some
areas where improvements are required.
For a first visit the results were very good
and we expect that upon completion of
the items identified Unaxis Maarssen
will be able to join our many other
certified suppliers.
Were there any
outstandingly good
points about the Unaxis audit?
Unaxis make extensive use of the intranet
to ensure consistent service to all
customers. The intranet also gives support
to the many service & sales organizations
around the world. It is an excellent tool
to provide access to a centrally controlled
source of procedures and data that can be
accessed anywhere in the world. This
together with the process mapping being
carried out are two points I would like
to highlight.
Which particular areas need to be
improved and what should Unaxis
focus on in the future?
ISO 9000 is used in the central office but
benefits would be obtained by its more
widespread implementation within the
regional offices such as Maarssen. The
new SAP system has the capability to
gather useful information from all sites
worldwide, and there is an opportunity to
make greater use of this information.
What are the next goals that Philips
will set its suppliers and how will
the relationship between Philips and
Unaxis continue?
Unaxis should work to ensure all its
manufacturing and sales facilities meet
the requirements of ISO 9001, this is
a significant step towards achieving
SQS requirements. We use our Supplier
Rating System (SRS) on an ongoing
basis to monitor, measure and recognize
improvement in performance, with
SQS being a part of this.
Unaxis Chip | 5
Unaxis – on the Way
to a “World Class Supplier”
Helmut Ritter, Quality Manager
January 2001 was not the first time for Unaxis to be audited by Philips.
BPS (Balzers Process Systems) has been certified according to the
Philips Quality Standard SNW-SQ-003A since March 1997.
BPS Headquarters were the first to be audited and the technology
centers were to follow at a later date. In September 2000 we started
the self-assessment process for Maarssen, in January 2001 the audit
through Philips Semiconductors Hazel Grove took place.
Unaxis Maarssen is a sales and service
center of the divisions Semiconductors
and Data Storage. The responsibilities of
the site in Maarssen are systems and
parts sales, field service and customer
care. It is situated in The Netherlands and
services Great Britain, Scandinavia, Italy
and of course The Netherlands.
The Philips Supplier Quality System
as well as the ISO 9001 requirements
are stringent and the audit covered
20 business areas, from “Management
Responsibility” to the “Application of
Statistical Methods”. Out of 10 maximum
points per area the supplier has to score
a minimum of 7 to pass the audit.
The required overall score of 7,5 was
exceeded slightly with 7,8 points, which is
a good result for a first audit. We are
looking forward to improving on that score
next time.
Today we focus on two major areas:
J establishing a better review mechanism
between site quality management and
corporate headquarters and
J alignment of local quality targets and
the global corporate goals.
6 | Chip Unaxis
Unaxis Maarssen has always
had an internal system of quality control,
but it was not a documented quality
management system and consequently
did not conform to the international
ISO standard. Now, in the course
of global reorganization, a new quality
management program, the Unaxis
Business Excellence Model, will be
implemented for all sites worldwide.
The next steps
The Unaxis goal: all sites worldwide
will be ISO 9001 (quality) and ISO 14001
(environment) certified. The results of
the audit at the site in Maarssen will serve
as a valuable lesson and be the basis
for successful audits in other Unaxis sales
and customer care sites.
And it will hopefully lead to equally
happy customers around the world.
The Philips auditors must have been
impressed by the quality products and
processes at Unaxis Maarssen: Only the
day after the audit Philips Semiconductors
Hazel Grove confirmed that in the near
future all spare parts would be ordered
from Unaxis.
Unaxis has been honoured
by VLSE Research Inc. as one
of this year’s 10 Best Chip
Making Equipment Suppliers.
“It is pleasing to see Unaxis
customers select it as an
outstanding supplier. This placement
demonstrates an unsurpassed
recognition reserved for a select few.
I wish you luck in your ongoing
pursuit of excellence”
G. Dan Hutchson,
President VLSE Research Inc.
Grand Opening in St.Petersburg
Jürg Steinmann, Global Communications Manager,
Unaxis Semiconductors
Just about a year after the merger with Unaxis,
on March 27 th 2001 the new Customer Resource Center
in St. Petersburg was officially opened.
It has been quite an achievement to build
the new site and still keep up the level of
service our customers had come to expect
– and this certainly was a reason to
celebrate. Customers, suppliers, Unaxis
employees and senior management from
around the world came to St.Petersburg
to take part in the festivities.
Heinz Kundert, Dr. Martin Bader and
Ed Richards together cut the ribbon
to officially declare the new facility open.
It covers 4.500 m2 and includes an
impressive 1.700m2 state-of-the-art
class 100 clean room laboratory. “This
gives us the opportunity to demonstrate
the superior quality of our equipment and
process technologies under production
clean room conditions” explained Ed
Richards. “A staff of over 200 people will
be employed at this location in the design
and manufacture of semiconductor
processing equipment and in the
development of new technologies.”
The United States is the largest
IT-market in the world, and as such
extremely important for a leading
advanced systems and services provider
like Unaxis. Our business is to design for
future possibilities. Long before product
designers and marketing experts conceive
of the next hype we have to provide the
means to realize those dreams. Our site in
St.Petersburg is one step closer to some
of our most important customers and
one step ahead in our mission to “making
IT possible”.
For more information please also see
the article on page 38.
Inside the clean room
Left to right: Heinz Kundert
(COO Unaxis), Dr. Martin Bader
(Executive Vice President
Unaxis Semiconductors) and
Ed Richards (Vice President
and St.Petersburg Site
Manager) cutting the ribbon.
“Why does Unaxis
expand in Florida
whilst tech stocks
are tumbling? …
We have learned to
live in a cyclical and
almost unpredictable
market environment.
One success factor
is to be ready once
the market takes
off again.”
Dr. Martin Bader
Unaxis Chip | 7
Regional Focus China
China – the Rising Star
in Semiconductor Heaven
Marcel Kessler, Sales Manager China
Veronika Schreyer, Managing Editor Chip
Only a few decades ago the picture that China presents today would have been a vision of utopia. China
has been venerated as a civilization with 5000 years of documented history, it has been feared as a
powerful enemy – and now it is being courted as the nation with the fastest growing economy in Asia.
50°
R U S S I A
KAZAKHSTAN
Ulaanbaatar
KYR.
Harbin
Changchun
Population
(est. July 2000):
1.261.832.482
40°
Shenyang
TAJ.
AFG.
Beijing
PAK.
N. KOREA
Tianjin
Seoul
S. KOREA
Shijazhuang
Taiyuan
C H I N A
Lanzhou
Xi’an
INDIA
Nanjing
Hangzhou
Chongqing
Changsha
Gulyang
Kumming
T’aipei
Nanning
VIET.
MYANMAR
LAOS
100°
THAI.
China’s transformation into a market
economy has been under way since 1978
when the era of Mao Tse Tung came to
an end. Slowly the new government
allowed a changeover to take place: from
a rigid, centrally planned economy of
collectivization to a system of greater
household responsibility. The authority
of local officials and plant managers in
industry was increased, a wide variety of
8 | Chip Unaxis
Total area:
9.596.960 km2
Land:
35°
9.326.410 km2
Water:
270.550 km2
Land boundaries:
30°
22.143 km
Nanchang
BHU.
90°
Shanghai
Wuhan
Lhasa
NEP.
45°
M O N G O L I A
Ürümqi
Guangzhou
TAIWAN
(Canton)
Victoria
Hanoi
110°
0
0
250
500 mi
250 500 km
120°
small-scale enterprises in services and
light manufacturing were permitted, and
the economy opened up to increased
foreign trade and investment. The result
has been a quadrupling of the GDP (Gross
Domestic Product) since 1978. In 1999,
with its 1,25 billion people and a GDP
of 3.800 US-Dollars per capita, China
became the second largest economy
in the world after the U.S.
Coastline:
14.500 km
25°
Capital:
Beijing
Independence:
쐍 221 BC, unification
20°
under the Qin or
Ch’in Dynasty
쐍 12 February 1912,
Republic of China
쐍 1 October 1949,
People’s Republic
of China
Why is China such an attractive place
for foreign investment?
Instead of radical liberalization, China
went for a step-by-step, carefully
controlled path towards a more liberal
“socialist economy”. Its success proves
the point: During the process of
transformation China experienced no
major economic downturn and far less
social unrest than any of the postcommunist countries in Eastern Europe
and Soviet Russia.
The necessary reforms involve both
state-owned and non-state businesses;
they encompass a wide range of
individual policies to bolster financial
performances, improve behavior and
provide supporting institutions and
infrastructure essential to a modern
economy. China is well on its way: The
economy grew by 8,1% in the year
to the first quarter of 2001 (Figure 1),
exceeding previous forecasts. It
weathered the slump in the Asian
economies earlier this year, but the US
market downturn will be felt after all:
economic growth is now projected to
fall to 7,3% later in 2001 but to slightly
rise again to 7,5% in 2002 (Asian
Development Bank). China still attracts
nearly four fifths of foreign direct
investment (FDI) to the region which
makes it the largest recipient of FDI
amongst the developing countries. In
the year 2000 FDI again increased by 4%,
contracted investment rose by 51%.
This dynamic climate of change is fertile
ground for new technologies. Science
and technology are playing an important
role in boosting China’s economic growth.
The amazing scientific progress is also
due to central government policy: In
the past five years 582,83 billion yuan
GDP
Industrial production
China
+ 8.1%
+ 12.1
Hong Kong
+ 6.8%
- 0.2
India
+ 6.0%
+ 0.6
Indonesia
+ 5.2%
+ 4.5
Malaysia
+ 6.5%
+ 4.3
Philippines
+ 3.6%
- 2.4
Singapore
+ 4.6%
+ 13.3
South Korea
+ 4.6%
+ 8.6
Taiwan
+ 4.1%
+ 9.1
Thailand
+ 3.1%
+ 2.4
(70,22 billion US dollars) were invested
into scientific development. Electronics
and communications, bio-engineering,
aerospace and nano-technology – the
achievements speak for themselves:
During the Ninth Five-Year-Plan
period (1996-2000) the output value
of electronics and communication
equipment manufacturing rose by 160%,
the foreign trade of high tech goods is
nearly five times higher than that of the
previous Five-Year-Plan. The output of
pharmaceuticals increased by 71,3%, the
total industry growth of the same period
was 41%.
The IT-industry in particular experiences
an unprecedented boost that is only just
beginning. It is the largest industry in
China, the third largest in the world and
the projections for market capacity are
staggering: 250 billion US Dollars in 2005
and 500 billion US Dollars by 2010 – a
yearly growth rate of 20%!
Foreign investment may be the fuel for
the Chinese economy – the motor is the
Chinese people. With a high educational
Figure 1:
Percent change
since previous year.
(Source: Asian
Development Bank)
standard, especially in the coastal
industrial regions, China has an
abundance of skilled workers and highly
qualified scientific personnel. Students
are encouraged to go abroad: during
the past two decades 320.000 Chinese
have studied abroad – 100.000 of them
have returned to China. More people
speak English in China than in America.
Unaxis Chip | 9
Regional Focus China
we supplied turnkey solutions for the
chromium blanks production to
customers in Xian and Chang Sha
and for pump production technology in
Beijing – and the systems are still running.
So the previous company name
of “Balzers and Leybold” has been well
established in China over the past
decades. Now the challenge is to
communicate the changes that took
place over the past few years, the new
brand name of Unaxis and the new
services we can now offer our customers.
To “be in the market”, rather than just
“producing for the market” – this is the
main reason for the major semiconductor
producers to build up production capacity
in China. And for Unaxis, being close
to the customer in China is as crucial for
success as anywhere else.
The Unaxis Hong
Kong offices will be
moving into this
brand new building.
Our new office in
Shanghai will also
be opened later
this year.
The formerly feared empire is now a
prospective member of the World Trade
Organization (WTO) with commitments to
cut tariffs, liberalize trade and investment
and open domestic sectors to foreign
participation. China will further establish
itself as a reliable and stable partner with
a more calculable domestic and foreign
policy and certainly go on to being one of
the most influential countries in the
21st century.
Unaxis in China
Unaxis (formerly Balzers and Leybold) has
been active in the Chinese market for
about 50 years. In the early days Unaxis
sold equipment for evaporation and
sputtering applications, 20 years ago
10 | Chip Unaxis
Process integration and
know-how transfer
Unaxis in China is focusing on providing
complete production and process
technology for the expanding
telecommunications market and
other IC productions, in particular
for Surface Acoustic Wave (SAW)
devices. Equipment, technical expertise
and process know-how: Unaxis can
confidently provide exactly what the
customer needs: one-stop-shop,
customized integrated solutions.
True to our strategy to be a partner,
not merely a system supplier, Unaxis is
committed to substantially increase
the service and support provided to its
customers and prospects in China and
will therefore also increase local staff
for sales, service and after sales care.
Thus we ensure that high service levels
will be maintained also in the future.
“New Shanghai – the Rocky Rebirth
of China’s Legendary City” is a
fascinating account of China’s
legendary city, its fall, its miraculous
rebirth, and the challenges it faces.
It is an excellent, wide-ranging
coverage – from finance and vice
to foreign business, culture and
state enterprise reform.
Author Pamela Yatsko is a writer
based in Hong Kong. From 1995-98
she was Shanghai Correspondent
and Bureau Chief for the Far Eastern
Economic Review. She also worked
as the Managing Editor of Business
China – an Economist Group
publication – and was a writer of
business case studies for Harvard
Business School.
Published December 2000
by John Wiley & Sons (Asia) Pte Ltd.
If you are interested
in modern China we
would like to recommend
this book to you.
Unaxis Chip | 11
Regional Focus China
12 | Chip Unaxis
Unaxis Chip | 13
Regional Focus Ð China
Digital Imagery © copyright 2001 PhotoDisc, Inc.
Successful Partnership in China
Unaxis and Nanjing Electronic Devices Institute (NEDI)
During the past decades the Asia-Pacific region has developed into a booming market
for the IT industry. Among the countries in the region, China is regarded as the outstanding
future star. In the “Tenth 5-year National Development Plan” the Chinese Government
focuses on the IT industry as the “Core of Strategic Industry” with the goal to further
increase growth in China and the Asia-Pacific region. In this strongly growing and
challenging market, Unaxis as a Total IT Solution Provider aims to be a moving
power behind this growth.
14 | Chip Unaxis
Sunday Huang, Sales Assistant, Semiconductors, Unaxis China
Wingo Lu, Service Manager Semiconductors, Unaxis China and Sunday Huang,
Sales Assistant Semiconductors, Unaxis China, talked to Mr. Gao Jian Feng, Sr. Engineer
& Deputy Director of the Nanjing Electronic Devices Institute (NEDI)
A historical connection
In the beginning NEDI used to purchase
US systems from Plasma Therm (who are
now Unaxis branded) for photomask and
compound semiconductor applications.
But also the cooperation between NEDI
and Unaxis already goes back a few
years. NEDI started to do business with
Unaxis Nextral in 1994 in compound
semiconductor applications and has
been the major partner of Unaxis China
ever since. Unaxis IT solutions surely
contributed to NEDI’s success in the IT
Industry in China.
Nanjing
Nanjing is situated in the
eastern part of China, on the
lower reaches of the Yangtse
River, and is the capital city
of the Jiangsu Province.
It has jurisdiction over 10
districts and 5 counties,
covering an area of 6.516 km2
with a population of 5,2 million
people.
Nanjing has developed into
an important industrial base,
the main industries being
electronics, automobiles and
chemicals. Situated about
250 km west of Shanghai it is
a major international commercial
port for the Yangtse delta region.
Nanjing is also one of China’s
foremost scientific research and
educational cities.
Partnership and customer
satisfaction
Besides the excellent system
performance, NEDI was and is particularly
impressed with the outstanding service
organization provided by Unaxis.
The speed of response, the solution
of a particular task or the continuous
system maintenance – the Unaxis
commitment to customer satisfaction
has always been highly appreciated.
With this excellent track record for
providing systems and services in China,
NEDI would be happy to continue and
further develop this proven long-term
partnership.
Mr. Gao Jian Feng particularly
mentioned the efforts of Wingo Lu,
the Unaxis Service Manager, and
his excellent contribution to customer
service in China.
Looking to the future
So far Unaxis could always fulfill all
customers’ needs in China, but this
market is growing fast and the territory
to be covered is huge. Therefore NEDI
has suggested that Unaxis should set
up a service hotline for China and keep
larger stocks of parts in order to be able
to maintain the level of service that Unaxis
currently gives its Chinese partners.
Thinking about possible future activities,
NEDI would also be happy to cooperate
with Unaxis by hosting activities such
as a conference, seminar or forum on
new industry developments to share
information and experiences with
new technologies. Such an event
would further improve and deepen the
relationship between Unaxis and its
Chinese customers.
The semiconductors market in China
is about to really take off and Unaxis has
already had a good “start up” with NEDI.
Based on this success story, we believe
that Unaxis China can look forward to a
promising future and possibly enter the
record books of Unaxis history.
Unaxis Chip | 15
Compound Semiconductor
Formation of Backside Vias in GaAs
for Advanced MMIC Devices
Russ Westerman, Principal Process Engineer, Unaxis USA
Dave Johnson, Director of R & D, Unaxis USA
Carrier
With the recent emergence of the
wireless telecommunications industry,
GaAs based devices are becoming
increasingly common in high frequency
circuit designs. Due to its high electron
mobility GaAs is well suited for these
low noise, high gain applications.
While GaAs has favourable electrical
properties it is a relatively poor thermal
conductor making it difficult to remove
heat from power devices. The formation
of backside vias is a common strategy
to overcome the thermal problems
associated with GaAs, as well as
providing a low impedance ground for
radio frequency (RF) devices (Figure 1).
Figure 1: Schematic
of MMIC device with
backside vias
Figure 2: Process
flow for backside
via formation prior
to plasma etch
Technology discussion
Backside via formation is one of the final
steps in monolithic microwave integrated
circuit (MMIC) fabrication. Once the
frontside processing has been completed,
the wafer is mounted face down on a
carrier wafer and mechanically thinned to
approximately 0.004" (100 microns) –
about the thickness of a piece of paper
(Figure 2). After patterning, the vias are
plasma etched through the thinned
substrate exposing the frontside metal.
Once the wafer has been etched and
cleaned, the vias are metallized. A gold
seed layer is deposited, typically by
sputtering, followed by an electroless
gold plating to act as the heat sink/ground
connection (Figure 3).
The ideal backside via etch process:
쐍 Short process time – the etch process
is required to etch vias 60 microns in
diameter by 100 microns deep. A typical
via etch rate of 3 µm/min results in etch
times of 30 minute per wafer.
쐍 High GaAs:Frontside metal etch
selectivity – since the thinning process
can result in thickness variations of
several microns, it is imperative that the
via etch process does not damage/etch
the underlying frontside metal contact.
16 | Chip Unaxis
Figure 3: Process
flow for backside via
formation – plasma
etch and metallization
쐍 High GaAs:Resist etch selectivity –
the via etch process is typically required
to etch through a 100 micron GaAs
layer. GaAs:Resist selectivities greater
than 10:1 are necessary to keep the
required photoresist thicknesses under
14 microns – the maximum resist
thickness typically achievable in a
single spin.
쐍 Excellent etch rate uniformity –
a highly uniform etch reduces the need
for extensive overetch reducing the
overall process time.
쐍 Results in a via with good electrical
properties – in order to achieve good
electrical properties, the resulting via
must be compatible with the customer’s
metallization capabilities. Sloping the
via profile during the etch process
reduces the effective aspect ratio of
the via which facilitates metallization.
쐍 Robust process – the via etch should
be insensitive to upstream (grind &
lithography) process variations.
The VERSALOCK ® platform provides the
high density inductively coupled plasma
(ICP) needed for fast GaAs etch rates.
The ICP plasma uses low pressures in a
single wafer processing mode for a highly
uniform etch. An RF biased cathode
Figure 4: Formation of sloped
backside via by resist profile
erosion. As the via etch
proceeds, the sloped resist
recedes , enlarging the CD
at the top of the via.
GaAs Etch Rate
GaAs: PR Selectivity
10.1 : 1
Via Profile
Sloped*
GaAs Rate Uniformity
provides independent control of the
ion energy needed to control the
GaAs:Resist etch selectivity.
In order to exhibit good electrical
properties the etched via requires
쐍 tight critical dimension (CD) control of
the via diameter
쐍 easy metallization (prograde feature
profiles preferred)
쐍 no post etch residues to inhibit metal
adhesion
While an anisotropic via offers the best CD
control, in practice this profile is somewhat
difficult to metallize. Through adjustments
in the lithography and etch processes, it is
possible to obtain a via profile that exhibits
a controllable slope to ease metallization
while maintaining the required CD at the
frontside interface. By sloping the resist
prior to etch and precisely controlling the
GaAs:Resist etch selectivity, it is possible
to define a sloped via profile (Figure 4).
Process results
Here we present results from an
ongoing process improvement program
with an existing customer that has
resulted in a number of process and
hardware improvements to the GaAs
via etch platform.
Plasma etch processes for GaAs
typically utilize a chlorine-based
chemistry. Though a Cl2 plasma alone
is sufficient to etch GaAs, additional
reactants are typically added to the
process to ensure a clean anisotropic
etch. The production proven Unaxis
process is based on a BCl3 / Cl2
chemistry.
During the etch process, GaAs is
converted to volatile etch products,
primarily GaCl3 and AsCl3, which are
6.1/min
Morphology
Figure 5: 150 mm high rate GaAs
via process capability of Unaxis
Versalock etch platform
< 5%
Specular
* using sloped PR mask
pumped out of the reactor. The
photoresist mask however tends to form
a number of polymeric etch products that
are redeposited. This redeposition is a
major contributor to the sidewall passivant
formed during the process, allowing
the etch to proceed at a high rate while
maintaining vertical sidewalls.
As well as condensing on feature
sidewalls, some polymer is redeposited
on the reactor surfaces. In order to reduce
deposition on reactor surfaces and
facilitate chamber cleaning to increase
tool productivity, Unaxis has redesigned
the GaAs via etch reactor. These
changes include:
쐍 Easy maintenance ICP source
– quick change lid
– quick change dielectric insert
쐍 Reusable chamber liners
쐍 90 degree lid hinges for easy access
쐍 Heated vacuum manifolds
쐍 Integration of Mag-Lev turbo pumps
쐍 Heated turbo foreline
point of the design resulted in a GaAs
etch rate of over 6 microns per minute
(compared to the customer’s current
3 µm /min process of record). Etch times
were reduced by over a factor of two with
superior profile control and morphology
(Figure 5).
The designed experiment also shows
that GaAs: Resist etch selectivity is solely
a function of RIE power over the range
of parameters investigated, while GaAs
etch rate is a function of pressure and
ICP power. This allows the RIE power to
be used to independently adjust the via
profile without affecting the GaAs etch
rate when a sloped resist is used.
Once installed, these components reduce
polymer deposition on reactor surfaces
which results in decreased cleaning times.
Cleaning times have been further reduced
through the use of “hot swap” kits for
critical parts that are then cleaned off-line.
In conjunction with reduced
maintenance & cleaning times, additional
hardware and process development was
focused on reducing the wafer cycle time
by increasing the GaAs etch rate.
The results of a designed experiment
(DOE) on the final hardware configuration
are shown below (Figure 6). The center
Summary
Through an ongoing process
improvement program with a current
customer, a number of hardware and
process improvements have been applied
to the GaAs via etch platform. These
changes have resulted in a 150 mm
proven production process capable of:
쐍 GaAs etch rates centered at 6 µm /min
쐍 Improved surface morphology
쐍 Adjustable via profiles to accommodate
metallization
쐍 2x reduction in wafer cycle time
쐍 Reduced maintenance /cleaning times
Figure 6: Designed
experiment results
for 150 mm GaAs
backside via etch.
process centered at
6.0 microns /minute
etch rate
Unaxis Chip | 17
Compound Semiconductor
High Power Productivity
LLS EVO Innovations and Product Enhancements
on a Batch Sputtering Tool
Alex Nef, Product Manager,
Batch Systems Sputtering
The past two years saw a multitude of
new applications in advanced packaging,
MMIC and optical component production,
which have hugely increased the demand
for LLS EVO sputtering systems. The LLS
EVO is a well-established production tool,
but its high flexibility for processes and
substrates make it also ideal for pilot
production and R&D.
Several innovations which improved the
system’s performance are now available
to our customers in the shape of product
enhancements which provide benefits
in yield, cost reduction, productivity,
maintainability and extended lifetime of
the system.
Recent innovations for the LLS are:
J The new magnet system doubles the
target life
J Special coatings extend shield life
many times and improve yield through
particle reduction
J High performance target cooling
doubles the sputter rate and cuts the
deposition time in half
J Asymmetrically pulsed DC power
supplies improve reactive sputtered
film properties
J The application of specific substrate
tooling improves the temperature
management of substrates
J H2 clean etching for advanced packing
applications
J Miscellaneous process optimizations
for advanced packaging and III-V
applications
18 | Chip Unaxis
In this issue we focus on the sputter
source innovations, the new magnet
system, the high performance target
cooling and the coated shields. The
application of each new feature depends
on the sputtered material, but all of them
can result in huge cost savings with a
return on investment in just a few months.
Double target life
An advanced permanent magnet system
increases the usual target life and
utilization by approximately 100 %. The
prime focus was put on precious metals
(Pt, Au, Ag, Pd) and other more costly
materials like WTi; typical film parameters
remain within the well-known LLS
specifications. The new magnet system
also doubles the amount of wafers
processed between target changes which
results in less maintenance downtime
and lower cost of ownership. The retrofit
is available for all installed LLS EVO and
502 systems.
The benefits of the new magnet:
J double target life
J lower cost per wafer, big savings for
some materials, for example WTi
J less maintenance to replace the target
J direct 1:1 replacement
Double sputter power
Advanced cooling technology for the
target allows twice the power to be
applied to the sputter source AKQ515.
Throughput for many applications is
increased and some materials show
even better film parameters at the high
power levels, for example lower film
stress. Higher power levels increase
the substrate temperature and each
application must be checked whether
the high power levels are applicable. The
installation kit requires modifications to
the cooling circuit.
Benefits of the advanced cooling solution:
J more than twice the power of a
standard cooling plate
J higher throughput
J better film properties
(depends on material)
J reduced costs per wafer
J no water to vacuum seal
J compatible to most of the current
AKQ515 target materials
Particle reduction kit
Modern surface coatings are applied to
the shields. The time between cleans has
increased dramatically, whilst yield was
improved. Flaking materials with frequent
cleaning intervals like SiO2, WTi / WTiN
showed excellent test results and seem
to gain most from the coating. It is applied
to all shield parts in front of the sputter
source including the shutter and must be
reapplied after each cleaning cycle. This
kit is available for all installed systems.
Benefits of the particle reduction kit:
J longer production periods
between cleaning
J longer lifespan of shields
J reduced particle
E
levels, higher yields
J reduced maintenance
J reduced cost per wafer
Figure 1: The erosion of
aluminum targets with
the current B magnet
and the new E magnet.
B
Compound Semiconductor
Challenging the Manufacturing
of Modern SAW Devices
Philippe Jacot, Managing Director, Unaxis SPTec
There is an increasing demand for SAW devices in the GHz-range
with a large variety of patterns, linewidths and metals. As the operating
frequency of these devices climbs from the 900 MHz range to
1.8/1.9 GHz for PCS and even 2.1 GHz for the 3G mobile phone
standards, flexible, highly reliable and low cost fabrication processes
are required to enable SAW manufacturers to remain competitive.
Phone Type
Duplexer
RF Receiver
RF Transmitter
IF Receiver
IF Transmitter
CDMA (IS-95)
Dual-band / Dual-mode
2
2
2
2
0
CDMA (IS-95) Tri-mode
2
2
2
2
0
GSM Dual-band
0
2
0
1 to 0
0
GSM Tri-band
0
3
0
1 to 0
0
TDMA (IS136) Tri-mode
1
2
2
1
0
WCDMA (3G)
Tri-band / Dual-mode
1
3
1
2 to 0
0
CDMA2000 (3G)
Tri-band / Dual-mode
3
3
3
2 to 0
0
GPS
0
1
0
0
0
Bluetooth
0
1
0
0
0
Figure 1: Number of
SAW devices in
cellular handsets
and other systems
Process
Cost of Ownership Index
Cost of Engineering Index
Yield Index
Lift Off
16.2
5
89
Dry Etch
25
6
80
Figure 2: Key Metrics comparing
metal lift-off process versus
metal dry etch process
Today, two main techniques are used
to produce high frequency SAW devices.
Both are based on i-line lithography
technology. One is a subtractive patterning
technique, referred to as dry etch, and the
other is an additive patterning technique,
referred to as lift-off.
The challenge in processing high
frequency SAW devices is to keep the
process variation as low as possible
in order to get acceptable manufacturing
yield.
In the past metal lift-off processing has
been hampered by the fact that there was
no easy, highly reproducible process to
generate the required re-entrant slopes or
overhangs. Many of the major players
have then chosen the dry etch approach,
taking benefit from all the lastest
developments done for IC manufacturing.
However, the progress made in single
resist layer 3-dimensional lithography and
the availability of high performance long
throw distance e-beam evaporators have
enabled lift-off processes to exceed dry
etch process in terms of process
capability, engineering cost and cost of
ownership (COO). This is mainly due to
the fact that in the lift-off technique there
is less physical and chemical attack of the
substrate, less residue and corrosion
issues and more possibility to re-work
the wafers during the process flow.
Looking to the cost of ownership of the
lift-off compared to the dry etch process,
the lift-off process shows significant
advantages.
Figure 2 represents the key metrics
for the metal lift-off and the metal dry etch
processes. The equipment cost
for the metal lift-off process is 70% as
compared to metal dry etch for an
equivalent capacity of 40 wafers per hour.
The estimate of the cost of ownership,
COO Index, is defined as follows:
COOI =
EQ
C · UT · AHO · 5 · Y
Where COOI is the Cost Of Ownership
Index, EQ is the Equipment Cost, C is the
Hourly Capacity, UT is the Utilization, AHO
is the Annual Hours of Operation, 5 is five
years of amortization period and Y is
the Yield.
The metal lift-off process has a cost
of ownership of 65% compared to the
metal dry etch process.
The Cost of Engineering Index, COE
Index, is estimated based on the degree
of difficulty to maintain the processes and
Unaxis Chip | 19
equipment. A scale of 1 to 10 was utilized
with 10 being the most difficult. The lift-off
process is slightly easier to operate from
an engineering perspective. The yield
for the lift-off process is estimated to
be 9% higher, mainly due to reduced
breakage of pyroelectric wafers, improved
metal uniformity, reduced residues
and defects, and reduced impact of
particulates.
The next technology node for the
SAW players is the success of 1.9 GHz
SAW duplexers for cellular handset.
This technology requires highly durable
and repeatable metallizations. In general,
to achieve the high power durability,
multi-layered and alloyed metal systems
are required. This raises numerous
additional process issues since these
advanced metal layers cannot be
properly etched with the present dry
etch technology.
Total commitment on SAW technology
Unaxis Semiconductors has adopted a
“total product support” approach to its
SAW customers and has redefined its role
to that of a “solution provider.”
This new model is based on a working
partnership with our customers. Together,
we jointly determine methods to
streamline solutions matching product
performance, fab capability, cost
efficiency and productivity goals.
Through our competencies across
hardware development, product and
process development and manufacturing
expertise, our customers benefit from
a wide range of technical skills meeting
their expectations from feasibility studies
to the creation of innovative customized
solutions to support their high-tech
businesses.
20 | Chip Unaxis
Lift-off
Dry Etch
Electrode Thickness
Long throw distance, uniformity
shaper and integrated end point
detection system enables thickness
control better than 1.5% 3 sigma.
Sputter target wear and time based
process control limit both uniformity
and repeatability to 2%, 3 sigma best
case.
Metal Density
Integrated Quartz Crystal
Microbalance control compensate
eventual metal variation.
No integrated control system
possible due to magnetron sputter.
Linewidth
Low reflectivity substrates allows
avoidance of bottom or top
antireflective coatings.
Unaxis metal lift-off process enables
more accurate control of the
electrode linewidth at the SAW
propagation plane.
Highly reflective Aluminum surface
demands anti-reflective coating
requiring a very high temperature
bake process which induces cracking
problems with pyroelectric wafers.
Variation in linewidth loss is induced
in the Reactive Ion Etcher with filter
products requiring different metal
thickness, area coverage and
substrate type.
Metal corrosion,
residue and particles
Avoidance of highly corrosive etching
gases eliminates Aluminum corrosion
and polymer residue issue.
Sensitivity of lift-off process to
particles is 3 to 10 times lower than
dry etch.
Aluminum Reactive Ion Etching
requires delicate passivation process.
A particle creates a short circuit in dry
etch process versus an open circuit
for lift-off process.
Overetch
Not an issue.
Highly aggressive etch process
induces possible substrate surface
attack and subsequent frequency
shift.
To support our high-performance
metallization equipment, we have
developed a simple high performance low
cost of ownership metal lift-off process
for mass production of high frequency
SAW devices. The process is suitable for
the manufacturing of Low Loss SAW
devices up to 2.5 GHz, i.e. meeting the
specifications of all existing and foreseen
mobile telecom standards. The
lithographic process uses a single layer
resist and produces highly repeatable
customized overhangs. Coupled
with Unaxis BAK SAW or SAMSON
Evaporators, the process control and
the cost of ownership are unbeatable
for the manufacturing of high
performance SAW devices.
Additionally we use our process
approach to develop technology solution
for 900 MHz and 1.9 GHz SAW duplexers.
Figure 3: Comparison of critical
parameters affecting SAW filter
performance
0,5 µm
0,5 µm
1,0 µm
1842.5 MHz /LiTaO3
Figure 4: Metal lift-off process steps
High Speed Silicon
Turbocharged Silicon
Valerie Thomson, Msc.,
Freelance Technical Journalist
A recent feature appearing in the
Electronic Engineering Times claims that
Silicon Germanium (SiGe) is the fastest
growing process technology of all time.
Indeed, hyperbole aside, the industry
acceptance of SiGe picked up momentum
propelling this turbocharged silicon
process from niche to mainstream
semiconductor market segment. But
the process is no “overnight success”.
It has taken more than thirteen years since
the idea to dope Silicon with Germanium
in a new UHVCVD (Ultra High Vacuum
Chemical Vapour Deposition) process
was first patented by IBM back in 1987.
The computer manufacturing giant has
since poured more than $5 billion into
development. Since those early days,
Unaxis has been the chosen partner of
IBM to develop SiGe production
equipment. Emerging out of this
cooperation was the SIRIUS, the only
production proven system for SiGe
HBT (Heterojunction Bipolar Transistor)
manufacturing.
Now that IBM has made the important
strategic decision to license the patents
available to competitors, as well as
customers, the use of SiGe is growing
rapidly. The first to commercialize SiGe
products after IBM were Maxim and
Atmel (formerly Temic).
More recently, innovative start-ups
like SiGe Semiconductors Inc. are rapidly
moving into the new market segments
for SiGe chips, such as Bluetooth, the
short range radio system and wireless
networking. The Canadian company has
a Bluetooth USB, which it has recently
licensed to Cambridge Silicon Radio in
the United Kingdom.
Market researchers say read channel
devices, fibre channel, and storage
area networks applications are strong
drivers of the demand for SiGe circuits.
The demand for optical devices used
in telecommunication equipment in
broadband networks is what has driven
the market for SiGe processes up
until now, especially the SONET high
speed physical layers. The top
telecommunications equipment
manufacturers are competing with
start-ups to deliver 10 and 40 Gbps
(Giga bits per second) optical networking
chips based on SiGe. Agere, Nortel
Networks Microsystems, Infineon, and
IBM are working on 40 Gbps optical
networking chips, with IBM already
having demonstrated product through
its work with Alcatel.
One of the things that have slowed
down the market acceptance by a wider
set of users is the fact that IBM was
the sole foundry supplier. Established
manufacturers do not like to be dependent
Siemens UMTS SX45
A Siemens prototype
of a 3G consumer
product is shown here.
Dubbed the UMTS
SX-45, it is a highly
integrated system,
incorporating a digital
camera, fingerprint
recognition to do away
with PIN codes, and
large, colour display.
To become a reality, it
will require a high level
of silicon integration,
with resulting
miniaturization and
extremely low power
consumption.
Ericsson Internet Radio
Ercisson’s Cordless
Internet Radio H100 is
linked via Bluetooth
to a broadband Internet
connection. It’s a
breakthrough in
entertainment value
with its ability to offer
thousands of radio
stations and Internet
broadcasts from
around the world.
Unaxis Chip | 21
on a single foundry for the supply of
essential technology. A new venturebacked foundry (in part financed by Intel
Capital) called Communicant will be
the first pure play communications SiGe
chip foundry and it will be built in eastern
Germany.
Its announcement earlier this year
spurred the major Taiwanese foundries,
UMC and Taiwan Semiconductor, into
action. Both have announced SiGe
process support. As more and more
foundries decide to supply SiGe wafers
and chips, there will be greater
acceptance. Announcements from these
foundries suggest that there will be
multiple suppliers with volume production
by late 2003, many oriented towards the
telecommunications market segment.
Wireless applications demand
begins ramp up
The physical properties of SiGe make
it a strong contender for RFICs (Radio
Frequency ICs). In this market it will
compete head to head with GaAs
semiconductors. SiGe doesn’t necessarily
process signals better or more reliably
than GaAs, but it is vastly cheaper.
In addition, its ease of integration with
CMOS (Complementary Metal Oxide
Semiconductors) will be a big driver
of the next phase of SiGe growth.
In an environment where the cost of
components is constantly being shaved,
and the cost of assembly is also critical,
if SiGe can offer greater integration
and fewer chips – with the resulting
design and assembly efficiencies wireless
equipment manufacturers will stand
up and take notice.
All of the major suppliers to the mobile
telecommunications equipment suppliers
22 | Chip Unaxis
Ericsson Future Tool
High-level integration enabled by new
semiconductor processes, as well as
advanced display technologies are required
to make this prototype a reality. Ericsson’s
aesthetically pleasing vision of a future tool
for road warriors and people who work
in small spaces includes a digital camera,
detachable keyboard, and smartpen,
connected with Bluetooth. Allready, Palm Inc,
the folks who created the market for PDAs,
which is not the same as inventing the PDA,
is selling Bluetooth enabled versions of its
flagship product. Many new Bluetooth ICs rely
on SiGe power amplifiers.
have announced SiGe product pipelines.
Texas Instruments is working to integrate
its technology in high performance SiGe
products. Motorola's decision to use
SiGe BiCMOS (Bipolar CMOS) in all new
phones, as well as the licensing of the
SiGe Carbon process is a good indicator
that the market is picking up steam.
The Japanese semiconductor
manufacturers – Hitachi, Mitsubishi
and NEC – have made product
announcements. NEC, for example,
began shipping samples of highperformance SiGe power amplifiers for
use in the wideband cellular technology
for next generation mobile phones and
multimedia devices, ready for volume
by the end of 2001.
The European semiconductor vendors –
Infineon, Philips, STMicroelectronics
and Communicant – are focused on
communications applications with a recent
increased interest in using SiGe for a
range of wireless applications, from close
range Bluetooth devices to longer range
cellular and satellite circuits.
Analysts say that although the current
demand for handset chips is depressed
(due to manufacturer inventory build-ups),
devices for the core network market
remain robust.
The applications discussed to this point
position SiGe as a viable competitor to
GaAs chips on functionality, price and
performance. But what sets SiGe apart
is its compatibility with CMOS, the most
ubiquitous silicon technology.
A major driver in the semiconductor
industry is the goal of integration, which
has driven System on a Chip (SOC)
research. Since CMOS has dominated
the semiconductor market in the past,
it is popular because it offers lowest cost,
lowest power, highest integration
technology available. But it is limited by
speed, and since SiGe combines the
integration and cost benefits of CMOS
with the high speed/low power benefits of
Bipolar technology, researchers are hard at
work to develop and commercialize SiGe
HCMOS (Heterostructure CMOS).
University researchers, as well as major
vendors such as Agere, IBM and IMEC
are making rapid progress developing the
technology to enable HCMOS design
and production.
Recent new products from Unaxis
will also help to drive growth in the SiGe
market. Unaxis is already delivering its
SIRIUS system for SiGe HBT production.
Foundries acquiring its new wafer
processing tools for CMOS will be able
to deliver SiGe faster and more reliably
than before. To produce SiGe CMOS,
special buffer layers have to be added in
order to adopt high concentration of
Germanium but until now for growing
thick CMOS buffers, no rapid throughput
High Speed Silicon
Selected Recent Products from SiGe Vendors
Tektronix
Designers rely on Tektronix’
real-time oscilloscopes
to evaluate dynamic
performance and identify
transient problems in their designs.
But memory system clock speeds now include
266-MHz DDRAM and 400-MHz Rambus rates,
with rise times on the order of 150 ps with clock
jitter less than 50 pspp required to sustain
adequate timing margins and backplane designs
implement Fibre Channel running at multi-gigabit
rates. In addition, data communication rates
of 1- to 2.5-gigabits per second data streams are
becoming common. Performance rates such
as these put enormous pressure of test equipment
suppliers to stay ahead of the industry. Tektronix
says it can stay ahead by utilizing SiGe technology
to address these extreme signal requirements.
process was available. LPCVD (Low
Pressure CVD) systems require a process
time of days for only one wafer and even
the conventional UHVCVD batch process
may have limitations for higher Germanium
concentration.
The news is, according to Unaxis
scientists, they have recently found the
solution with their LEPECVD (Low energy
Plasma Enhanced CVD) process. This
revolutionary new Unaxis process for
CMOS can grow the typically microns
thick buffer layer at low temperatures
in just a couple of minutes enabling 24 /7
production rates. The low temperature
is required to keep quality high, both in
terms of morphology and maintenance
of uniformity.
Valerie Thompson
MSc. has been a
freelance business and
high-tech writer for more
than 10 years.
A Canadian based
in Zurich, she tracks
the trends and
developments of
Europe’s purveyors of
advanced technology.
Vendor
Product
Segment
Applied Micro
Circuits Corp.
40 Gbps transimpedance amplifier, 3.3V, 2.5 Gbps
OC-48 WDM solution, as well as the first TIA on the
market capable of addressing both WDM and TDM
applications.
Wireless and
Broadband
Short to long haul networking; transimpedance amplifier
device for 40 Gbps on 0.18 micron 7HP SiGe
Broadband IC
Agere (former Lucent
division)
Three integrated circuits (ICs) for 10 Gbps optical
networking systems, including SONET OC-192, SDH
STM-64 and 10 Gigabit Ethernet applications
Broadband IC
Atmel
LNA cellular 1800 MHz+ (samples available now)
Wireless IC
Conexant
50 GHz for 3.3-V transistors and 70-GHz for
2.5-V devices
Wireless and
Broadband
Harris /GEC Plessey
2.4 GHz ISM band and Wireless LAN ICs
Wireless ICs
HRL (former Hughes
Research )
Process technology
Chip production
IBM
Range of products
Wireless and
Broadband apps
Infineon
Phase locked loop (PLL) IC operating at 10 GHz and
40 Gbps multiplexer/demultiplexer chipset
Wireless and
Broadband ICs
Intersil
Power amplifiers
Wireless ICs
Maxim
Range of line noise amplifiers
Wireless and
Broadband
Mitsubishi
3G RFICs via a design deal with SiGe Microsystems
Wireless and
Broadband ICs
Motorola
RF BiCMOS based line noise amplifier with an on-chip
bypass switch clock driver chips (samples avail. 3Q2001)
Wireless and
Broadband ICs
NEC
Power amp for 3G (Sample price is 27 cents, and the
company will launch production at 2.5 million units per
month in April, ramping to 30 million units per month by
the end of 2001.)
Wireless ICs
Nortel
Amplifiers and complex power
Broadband ICs
ON Semiconductor
2.5 to 3.3Vdc SiGe differential receiver/driver for
10 Gigabit Ethernet speeds
Wireless and
Broadband ICs
Parthus
Using ST's proprietary BiCMOS6 for Bluetooth RFICs
Wireless ICs
SiGe Microsystems
Bluetooth power amplifiers, tuners
Wireless and
Broadband ICs
Stanford Microdevices
Direct Quadrature Modulator and HBT MMIC amplifiers
Wireless and
Broadband IC
Tektronix
Real Time Oscilloscope
Testing and
measuring
Texas Instruments
Emitter bipolar devices with drawn transistor gate lengths
of 0.25µm, and achieves 3V CMOS with 0.35µm drawn
transistor gate-lengths.
Wireless ICs
Unaxis Chip | 23
High Speed Silicon
Low Energy Plasma Processing
for Hetero CMOS in a 300 mm Single Wafer Cluster Tool
Dr. Jürgen Ramm, R&D Manager,
High Speed Silicon
The Concept of Low Energy Plasma
Processing (LEPP)
The utilization of low pressure plasma in
thin film technology is motivated mainly
by two reasons:
쐍 lowering the thermal budget during
processing and
쐍 increasing the reactivity of the processes
for cleaning, deposition and etching.
Shrinking device dimensions presuppose
stable doping profiles. Temperaturedriven segregation of dopants and alloy
components has to be suppressed. The
interfaces between the layers must be
abrupt and smooth. To fulfill all these
demands, reduced thermal budgets
have to be realized. Additionally, low
processing temperatures are necessary
for prestructured/patterned substrates
and important for material compatibility
issues, especially in SiGe and classical
compound semiconductors technology.
The activation of precursors
(excitation, ionization, dissociation) and
the enhancement of chemical reactions
Figure 1: Typical
potential scheme of
a low energy plasma
discharge. The ion
energy in this case
is 9 eV and below the
sputtering threshold.
24 | Chip Unaxis
U/Volt
Plasma potential
1V
0V
Anode = Ground
-8 V
Floating potential
-15 V
≈ Sputter threshold
-25 V
Cathode potential
right at the substrate surface allow the
development of new processes for material
deposition with outstanding properties
and processes for the efficient removal of
material during etching and cleaning.
However, there is a tendency in the
semiconductor industry to avoid plasma
processing wherever possible. The reason
for this is that conventional plasma
generates energetic particles which may
add damage to substrate surfaces and
to prefabricated device structures. The
bombardment with these energetic
particles may result in an amorphization
of single crystalline surface layers,
redeposition effects in prestructured
substrates (like contact-holes), and
intermixing and implantation in the
uppermost surface layers. In contrast to
conventional plasma, the energies of the
particles in LEPP are restricted to energies
below the sputtering threshold. A typical
potential scheme in Figure 1 characterizes
the ions generated in a low energy
plasma1. The difference in plasma and
floating potential (here 9 V) is well below the
sputtering threshold. This is the important
feature of LEPP: despite the direct
exposure of the substrate to the intense
plasma, only chemical processes are active. This feature is also the reason that
LEPP is especially suitable for
applications related to epitaxial growth
and damage free cleaning.
Low Energy Plasma Cleaning (LEPC)
The standard process to remove carbon
and oxygen contamination from the
surface of silicon wafers before epitaxy
is a high temperature bake at about
900 °C in hydrogen atmosphere. At this
temperature, molecular hydrogen is
dissociated and reacts with carbon and
oxygen to form volatile compounds. A high
hydrogen pressure or large hydrogen flows
help to increase the efficiency of this
cleaning procedure.
In LEPC, the plasma dissociates
molecular hydrogen and replaces the high
temperature. This dissociation and the
moderate energies of the plasma particles
Figure 2: SIMS depth profiles of the substrateepilayer interface. The interface in sample (a)
is clearly marked by the peak in the O and C
concentration at a depth of 200 nm. The
interface in sample (b) shows much lower
O and C concentration resulting from a lower
partial pressure during LEPC.
8
10
12
1
9
2
6
-CuLMM
CuLMM
-C 1s
s
50
20
0
1000 900 800
700 600 500 400 300 200 100
Binding Energy (eV)
0
0
1000
800
600
400
-Si2s
s
-Cu3s
s
-Si2p
S
-Cu3p
C 3p
-O KLL
L
c/s
-C 1s
s
-CuLMM
M
-O 1s
s
Figure 4: XPS spectra
from the surface of a
copper pad before (a)
and after (b) hydrogen
plasma treatment.
The absence of the
F 1s and the F KLL
peaks after LEPC
in spectrum (b)
demonstrates the
capability of LEPC
to remove fluorine.
b
100
-Si2s
s
-Si2p
p
40
200
150
-N 1s
s
60
a
-F KLL
L
80
-F 1s
s
-O KLL
L
100
-Cu2p3
3
double-wall water cooled all metal-sealed
process chamber (1) which is pumped by
a dry pumping system (2, not shown). A
slit valve (3) connects the module with a
central handling system. The wafers are
transferred from the handler to substrate
pins (4). A susceptor (5) lifts the wafer (6)
in process position with the help of a
wafer lift mechanism (7). A plasma source
(8) is attached to the chamber, which
generates a low voltage high current DC
discharge (9), the «low energy plasma».
The working gas for this discharge is
argon, which is fed directly into the source
(10). The reactive gas inlet (11) is placed
near the substrate.
To initiate the discharge, the filament
(12) is heated and a voltage between
filament and ground is applied. At voltages
of about 25 V, discharge currents of about
100 A are achieved. Based on plasma
-Pd3d5
5
7
Figure 3: Schematic of the 300 mm LEPC
single wafer module.
-O 1s
s
4
-CuLMM
M
5
characteristics as described in Figure 1,
only the nature of the reactive gases
defines the chemical reactions, which
proceed at the substrate surface. The
preferred gas for cleaning silicon wafer
surfaces is hydrogen. The activated
hydrogen reacts with surface atoms to
form hydrogen volatile compounds. These
chemical reactions are utilized to remove
carbon as well as oxygen and other
hydrogen volatile compounds from the
wafer surface. There is no simultaneous
removal of materials, which do not form
hydrogen volatile compounds (for instance
aluminum or copper) like it is the case in
a conventional plasma by sputtering. The
wafer is usually unheated during cleaning
and its temperature will not exceed 150 °C
during plasma exposure.
As mentioned above, material
compatibility issues will play an ever
increasing role in process developments.
Therefore, we tested the LEPC also for
the removal of flourine containing residues
from the copper pad of wafers with
copper metallization. In Figure 4, the XPS
measurements before (a) and after (b)
hydrogen plasma treatment of a copper
surface is shown.
-Cu2p
-Cu2p3
11
3
c/s
make LEPC ideally suited for applications
in SiGe technology.
The excellent properties of SiGe
devices like HBT and Hetero-MOSFET
result from «band gap engineering» based
on strained heteroepitaxial layers. A clean
single crystalline surface is a prerequisite
for this growth.
The SIMS depth profiles in Figure 2
show a comparison of the quality for two
cleaning processes. In both processes,
silicon wafers were exposed to the
hydrogen plasma for 5 minutes. No wet
chemical cleaning of the wafers (neither
RCA clean nor HF dip) was performed
before this plasma treatment! After LEPC
in hydrogen, homoepitaxial layers of
200 nm thickness were grown on both
samples. In sample (a), the interface is
clearly marked by peaks in the carbon
and oxygen profile. These peaks are
much smaller for sample (b). There is
also a correlation between interface
contamination and defect densities.
Defect densities of 10 7/cm2 were
measured for sample (a). Sample (b) was
below the detection limit of our optical
microscope (< 10 4/cm2). The only
difference in the cleaning processes was
the background pressure in the module.
This shows the importance of limiting the
residual gas pressure of oxygen and
carbon containing gases to values below
10 -9 mbar during LEPC to achieve
defect-free epitaxial growth.
Based on this and other experiences
during the process development for this
cleaning process, a single wafer-cleaning
module was developed which fits to
standard cluster tool configurations.
The LEPC single wafer module for
300 mm substrate size is shown
schematically in Figure 3. It consists of a
200
0
Binding Energy (eV)
Unaxis Chip | 25
High Speed Silicon
Pro
mo cess
dule
LEP
EC
200 mm wafer
open cassette
VD
Load port modules
LPMs
VD
EC
26 | Chip Unaxis
300 mm cluster tool for LEPP
in the Unaxis laboratory
As already mentioned, the high epitaxial
growth rates make LEPECVD well suited
for the growth of thick graded relaxed
buffers and virtual substrates – the
conversion of the silicon wafer to a SiGe
wafer with germanium concentrations of
up to 100%. The combination of LEPC
and LEPECVD, moreover, opens up a
s
ces
Pro dule
mo
VD
LEP
Low Energy Plasma Enhanced
Chemical Vapor Deposition (LEPECVD)
Plasma enhanced epitaxial growth is
a relatively new approach for deposition
processes. Very promising results were
obtained during the Swiss national project
MINAST with Unaxis partners, the Federal
Institute of Technology in Zurich and the
Interstate University for Applied Science
in Buchs. In this project, the concept
of low energy plasma was investigated
for the deposition of SiGe layers, with a
special emphasis to grow thick graded
relaxed buffer layers for virtual substrates.
Outstanding growth rates up to 10 nm/s
were obtained for epitaxial growth and
the electrical quality of the layers is
comparable to MBE and UHVCVD
grown layers. In cooperation with the
DaimlerChrysler Research group,
p-MOSFETs were manufactured with
record hole mobilities2/3. Recent
investigations by the same group for
high electron mobility transistors
(HEMT) again confirm the excellent
quality of LEPECVD grown layers4.
In analogy to LEPC, the ion energies in
LEPECVD are of crucial importance for the
quality of the epilayers. This is illustrated
in Figure 5. In this figure TEM cross-
300 mm wafer
FOUP
EC
s
ces
Pro dule
mo
A flourine peak in the spectrum illustrates
the presence of this compound after the
contact pad etch. A short LEPC treatment
removes flourine from the pad. For this
process the substrate temperature was
below 100°C and in contrast to other
flourine removal procedures, neither
removal of copper (no sputtering) nor an
oxidation of the copper surface occured.
sections for silicon epitaxial growth for
different substrate bias are compared.
All the other growth parameters were kept
constant for the two processes (growth
rate, discharge current, substrate
temperature). Neither hydrogen plasma
cleaning nor a high temperature bake in
hydrogen was performed. Therefore, the
interface between substrate and epilayer is
clearly seen and helps to distinguish the
epilayer from the wafer. In 5(a) a substrate
bias of -14 V was selected, and the TEM
cross section at this magnification did not
show any defects. In contrast, a substrate
bias of -16 V in 5(b) result in a high density
of stacking faults. This illustrates the
importance of low ion energies for
defect-free growth5.
The 300 mm single wafer LEPECVD
module is similar to the LEPC module in
Fig. 3. A substrate heater (only an option
for LEPP) is added to the module for
substrate temperatures up to about
800 °C. With this module, Unaxis is
realizing the first plasma-enhanced
epireactor for production. Although the
process seems to be dedicated to
SiGe technology, especially to future
SiGe-CMOS processes, it has the
potential for the production of many
other materials which are difficult to
realize in conventional processes.
LEP
C
LEP
LEP
C
Pro
mo cess
dule
radical new approach for such a process:
the wafers may be realized in a completely
dry process sequence consisting of only
two process steps. To investigate this new
approach, we shall install such a cluster
tool configuration in our laboratory and
start the process development this
summer. The 300 mm (200 mm is also
possible) cluster tool has one module for
LEPC and one module for LEPECVD.
The wafer handling is based on a GX 8000
handler (Brooks). A fully equipped cluster
tool may have two cleaning modules and
four growth chambers (Fig. 6). It is the
intention of Unaxis Semiconductors to
support with this new development the
CMOS technology during the transition
from silicon to SiGe.
References
1 N. Korner, E. Beck, A. Dommann, N. Onda,
and J. Ramm, Surf. Coat. Technol. 76-77,
731 (1995)
2 C. Rosenblad, LEPECVD – Breaking all records
in SiGe epitaxy, in Chip (Business & Technical
news from Unaxis Semiconductors), Issue 4,
February 2001
3 G. Hoeck, E. Kohn, C. Rosenblad, H. von Känel,
H.-J. Herzog, and U. König, Appl. Phys. Lett.
76, 3920 (2000)
4 Th. Hackbarth, High Electron Mobility Transistors
on LEPECVD Grown Virtual SiGe Substrates,
in Chip (Business & Technical news from Unaxis
Semiconductors), Issue 5 (this issue), July 2001
5 C. Rosenblad, H. R. Deller, A. Dommann, T.
Meyer, P. Schroeter, and H. von Känel, J. Vac.
Sci. Technol. A 16(5), 2785 (1998)
VD
EC
LEP
Pro
mo cess
dule
Figure 5: The ion
energy determines
the transition from
defect-free growth
in (a) for ion energies
of 14 eV and below
to a growth with high
defect densities in
(b) for 16 eV and
above.
s
ces
Pro dule
mo
Figure 6: The 300 mm
LEPP cluster tool
which combines
LEPC and LEPECVD
modules. One
possible application
of this configuration
is the complete dry
processing of thick
relaxed linearly
graded buffers for
virtual substrates.
High Speed Silicon
UHV-CVD for Low Temperature
Epitaxy of Silicon Germanium
A Well Established Technology with Unbeatable Advantages
The idea to use Silicon Germanium (SiGe)
to improve the performance of Silicon
has been around for decades. However,
for high frequency applications like
the Hetero Bipolar Transistor (HBT)
III-V systems, GaAs have been most
commonly used.
Finally in the 1980s scientists have gone
for the low temperature epitaxy process
(LTE) run in an UHVCVD reactor, in order
to first test a method to economically grow
epitaxial SiGe films. The pre epitaxial
cleaning was one of the challenges to be
overcome before this technique was ready
for production allowing the
implementation of SiGe into devices.
It has taken more than 10 years for
SiGe to gain ground and be turned into
production scale. IBM was the pioneer and
is still producing most of the SiGe devices
worldwide.
The first SiGe application which was
turned into mass production is the HBT.
Products have now been available
for about five years. The market leader
in SiGe HBT uses the LTE UHVCVD
technology successfully for the growth
of the base.
Low temperature epitaxy with
a low thermal budget
One of the main advantages of the LTE
technique is the low thermal budget which
is used for both the deposition and the
precleaning. An effective precleaning at
low temperature prevents the destruction
of already patterned structures which
might be affected by high annealing
temperatures of i.e. 800 °C. But why is
low temperature growth so interesting?
First of all a low growth temperature
for a CVD process is challenging. Growing
at a lower temperature of i.e. 525 °C
needs a better control of contaminants
and therefore UHV conditions. And low
growth temperature causes a smaller
growth rate.
On the contrary a low growth rate
allows very precise control of the epitaxial
growth and guarantees better uniformity.
Parallel growth in a batch is possible and
can therefore more than compensate the
lower growth rate.
If the growth takes place at a lower
temperature the risk of islanding is much
smaller than for growth at higher
temperatures. Therefore homogeneity
and uniformity are much better. A smooth
growth for higher Germanium
concentrations of 30 % at 650 °C
growth temperature is probably an
impossibility (Figure 1).
For an effective band gap engineering
a high Ge content is needed. The higher
Ge content and growth temperature are,
the higher is the risk of relaxation. The
LTE growth helps to minimize this risk
because less thermal energy, which could
possibly cause relaxation, is available.
The chart (Figure 2) shows that the higher
the concentration of Ge, the lower the
growth temperature must be.
Low temperature growth has one more
advantage: Because of the reduced
thermal energy during film growth the
dopants Boron and Germanium have
reduced mobility and segregation.
Therefore steep profiles are possible.
The segregation is negligible and the
dopant stays where it is.
Steep dopant profiles are necessary to
realize thin layers. They allow for example
higher concentrations of Ge.
GeXSi1–X Morphology
800
Growth Temperature (°C)
Dr. Hans Martin Buschbeck,
General Manager, High Speed Silicon
700
Three dimensional growth
(islanding)
600
500
Two dimensional growth
(planar)
400
0.1 0.2
0.3 0.4 0.5
0.6 0.7 0.8 0.9
1.0
Germanium Fraction (X)
Source: after J. Bean et al., J.Vac. Sci. Technol. A, 2, 436, 1984
Figure 1: Conditions for Smooth
Continuous Growth Si1– XGeX on Si
Unaxis Chip | 27
High Speed Silicon
Thin unrelaxed SiGe films
SiGe films must be as thin as possible. The
thinner the films are, the higher is the strain
in the layer and the higher is the possible
Germanium concentration (Figure 2) which
again helps to increase the strain.
Critical Thickness for Si1-XGeXLayers
100.000
Critical thicknesses (A)
Figure 2:
Critical thickness
for relaxation
10.000
1000
100
900 °C
650 °C
750 °C
10
0
20
40
550 °C
60
80
100
Ge content (%)
Source: after People and Bean (550 °C), Appl. Phys. Lett.47 (3) 1985
Figure 3: Strained
(pseudomorphic) and
unstrained (relaxed)
heteroepitaxial
growth due to
lattice mismatch
of Si and Ge
Relaxation (unstrained films)
UNSTRAINED
EPITAXIAL LAYER
STRAINED
SUBSTRATE CRYSTAL
Source: after J.C. Bean, Silicon-Molecular Beam Epitaxy,
CRC Press, 1988, vol. 2, p.76
28 | Chip Unaxis
Strained layers with high Ge content
are best for increasing performance
indicators for the HBT like carrier mobility,
energy consumption and noise.
Relaxation which might take place at
higher growth temperatures will create
defects in the epitaxial structure and
make the films useless for later device
processing (Figure 3).
Nokia Call
Nokia’s display and
semiconductor
suppliers are working
hard to deliver the
radical improvements
on existing integrated
circuits processes
and design to
become even more
highly integrated,
offering reliable, low
power performance
to make the Finnish
phone manufacturer’s
innovative prototypes
an affordable reality.
High throughput / low cost
of ownership
Beside the advantageous low temperature
growth the SIRIUS low temperature
epitaxy reactor also allows parallel
processing of up to 25 200 mm wafers
with growth rates for SiGe of typically
3 nm/min. This leads to excellent
throughput numbers in the production
process.
High throughput is not the only feature
of the SIRIUS system which helps to
reduce the cost of ownership for our
customers.
Other advantages are:
쐍 Low gas consumption
(therefore no scrubber necessary)
쐍 No chamber self-cleaning necessary
쐍 Low maintenance
쐍 Long life-time
The SIRIUS system has been production
qualified for years.
Anyone interested in our well
established UHV-CVD process is invited
to test the capability of the Unaxis SIRIUS
system. We offer sampling in our
technology lab in Switzerland for epitaxial
Si /SiGe films (undoped or Boron doped)
for all wafer sizes up to 200 mm.
Anoto Pen
Bluetooth may be seen
by some as a cable
replacement technology.
But the folks at Anoto
need Bluetooth to realize
their vision for the future
of the pen, shown here.
This digital pen contains
a tiny digital camera
and image processor
(custom CMOS sensor
100 FPS), an ARM ASIC
processor at 70 MHz
and a Bluetooth radio
transceiver. It also
contains an ink cartridge
so that users can see
what they have written
or drawn.
It communicates with
personal computers,
databases, the Internet
and e-commerce.
High Speed Silicon
Virtual SiGe Substrates
High Electron Mobility Transistors on LEPECVD Grown Virtual SiGe Substrates
Dr. Thomas Hackbarth, DaimlerChrysler Research Center Ulm, Germany
Dr. Hans von Känel, Solid State Physics Laboratory, ETH Zürich, Switzerland
The increasing need for higher frequencies and reduced costs predestine
the Si based High Electron Mobility Transistor (HEMT) as a superior
device for coming generations of high frequency electronics. The
combination of different growth technologies like LEPECVD and MBE
enables the realization of SiGe device structures with excellent
performance.
Analogue high frequency electronics in
the range between 1 GHz (wireless
communication) and 100 GHz (RADAR)
are still dominated by GaAs based
devices like HEMTs and HBTs
(heterostructure bipolar transistors).
Forced by cost restrictions especially in
the cellular phone market, SiGe HBTs
emerged as a new technology in recent
years, whereas SiGe HEMTs are still at
research status. Unlike to AlGaAs on
GaAs, SiGe on Si is a highly lattice
mismatched material system, suffering
from defect generation during growth
but opening the possibility of strain
engineering. Key element for the
realization of a strained Si channel with
high electron mobility is the so-called
virtual substrate which is produced by
epitaxy of a strain relieved SiGe alloy
layer on a Si standard wafer. Presently,
the preparation of a high quality virtual
substrate with low defect density requires
a very thick (several µm) epitaxial layer.
For sufficient process throughput a high
growth rate is essential which is in sharp
contrast to the requirements for the
deposition of the active HEMT layers
(i. e. low growth rate) to get interface
abruptness and precise thickness control
on a nm scale. The challenge of these
widely spaced process parameters can
be overcome through a combination
of different growth technologies like
molecular beam epitaxy (MBE) and low
energy plasma enhanced chemical
vapour deposition (LEPECVD).
SiGe HEMT basics
In an electronic device the charge
carrier transport properties decisively
determine the device functionality and
performance. Impurity scattering in
doped semiconductors is the main
limiting factor for the carrier mobility.
A proper heterostructure stack permits
the separation of a doped layer (which
supplies the carriers) from the carrier
transport layer (the channel). The
prerequisite for this effect is a lower band
edge of the undoped channel material
compared to the surrounding doped
layers which enables the transfer and
confinement of the carriers into/within the
channel. As a result the carriers can move
collision-free as a «two-dimensional
electron gas» (2DEG) without being
affected by the dopant impurities. This
is illustrated in Figure 1. The conductivity
of the channel is strongly depending on
the amount of doping in the supply layers
and the distance between them and
the channel (spacer thickness) which
influences the carrier transfer and mobility.
In the case of SiGe n-type transistors,
supply
layer
spacer
channel
spacer
supply
layer
dopant atom
matrix atoms
electron
Figure 1: Carrier transport in homogeneously doped semiconductors (left) and in modulation
doped high electron mobility structures (right)
Unaxis Chip | 29
n+-SiGe
i-SiGe spacer
Si channel
i-SiGe spacer
n+-SiGe
n-SiGe
i-SiGe spacer
Si channel
SiGe constant composition layer
2DEG conditions with high mobility can
only be achieved by creating a tensile
strained Si channel embedded between
unstrained SiGe layers.
The relaxation of the strain in SiGe on
Si substrates is accomplished by the
formation of misfit dislocations parallel to
the interface. As a detrimental side-effect,
additional threading dislocations occur
which pierce the transistor channel and
deteriorate the mobility of the carriers.
Up to now virtual substrates with lowest
threading dislocation density have been
Figure 3: TEM image
of a complete HEMT
structure (left) and
details of the regrown
active layer stack
Si channel
regrowth
interface
Si ... SiGe graded
30 | Chip Unaxis
MBE reference
MBE on LEPECVD buffer
80000
30 K
60000
40000
77 K
20000
300 K
0
0
10
20
20
40
inv. temperature [1000/K]
Si substrate
Figure 2: Schematic
diagrams of single
sided doped (left)
and double sided
doped (right) SiGe
HEMT structures on
virtual substrates
Figure 4: Carrier
mobility of mixed
technology and
reference samples
as a function of
temperature
100000
electron mobility [cm2/ Vs]
Si cap
LEPECVD or
MBE grown
virtual substrate
Si cap
MBE grown
active layer stack
High Speed Silicon
achieved by growing thick SiGe layers
with a shallow composition grading.
Doing this with MBE ends up with
unreasonably long growth times (several
hours) and an unacceptably high
consumption of source material (10 to
20% of the source charge).
Mixed technology approach
The low energy plasma enhanced CVD
(LEPECVD) system is based on an Unaxis
UHV reactor primarily developed for dry
cleaning of semiconductor surfaces. The
low discharge voltage (< 25 V) and the
high ion current (up to 70 A) enable an
efficient cracking of the source gases
(Silane and Germane) without generating
ion defects. Focussing the plasma onto
the wafer results in a high surface energy
and enables extremely large growth rates
– up to 20 times higher compared to
MBE /see CHIP 1 (1999). At the Solid
State Physics Laboratory, ETH Zürich /
Switzerland, relaxed buffers with a SiGe
composition grading of 10%/µm and a
1 µm thick constant composition layer
have been prepared by LEPECVD. These
virtual substrates have been overgrown
with n-type SiGe HEMT structures at the
DaimlerChrysler Research Center in
Ulm/Germany by MBE (Unaxis UMS 620).
Two versions were realized (Figure 2):
쐍 a one-sided doped high mobility
structure with a thick spacer on a
relaxed buffer with a Ge content of 30%
for carrier transport investigations and
쐍 a double-sided doped layer stack
with thin spacers on a virtual substrate
with a composition of 40% for device
preparation.
For comparison, reference structures
were grown entirely by MBE but with a
gradient of 20 % /µm and a constant
composition layer only 0.5 µm thick to
reduce growth time and material
consumption.
Results
Transmission electron microscopy in cross
section shows the typical defect structure
for these types of relaxed buffers with
a high density of misfit and threading
dislocations in the compositionally
graded region and a defect free constant
composition part above (Figure 3). Even
the LEPECVD/MBE regrowth interface
appears free of crystal defects. This
excellent structural quality results in very
high room temperature electron mobility
of about 2.000 cm2/ Vs at a sheet carrier
concentration of 1 ҂ 1012 cm-2 for both
versions. At low temperatures the mixed
technology sample shows an outstanding
mobility of more than 88.000 cm2/Vs
compared to 86.000 cm2/ Vs for the
Figure 5: SEM pictures of a SiGe HEMT with Pi-gate
configuration and details of the T-shaped gate
10000
MBE reference
MBE + LEPECVD
1000
100
Rs
I max
gm
[Ohm/sq.] [mA/mm] [mS/mm]
ft
[GHz]
f max
[GHz]
Figure 6: HEMT figures of merit: sheet resistance R s,
maximum drain current I max, maximum transconductance
g m, gain cutoff frequency f t, and maximum oscillation
frequency f max.
reference structure (Figure 4). This
is probably due to a lower defect
density achieved in this type of large
thickness buffer.
For high frequency application,
transistor devices have been produced
at the DaimlerChrysler AG by using a
T-shaped gate with a footprint of about
100 nm (Figure 5). Comparing the figures
of merit of both technologies shows 10%
to 20% better device results for the mixed
technology in all cases (Figure 6). This
is all the more surprising because in this
case the wafers had to ride out storage in
ambient atmosphere, transportation and
additional wet cleaning before regrowth.
Outlook
Even better results could be expected
by combining LEPECVD with a low-rate
growth system like MBE or UHVCVD in
a cluster tool, thereby enabling wafer
transfer under UHV conditions between
buffer and active layer preparation.
In this configuration, the processing
time per HEMT structure growth (including
in situ surface conditioning etc.) could
be reduced to 60 min compared to
180 min necessary for entire MBE growth.
Moreover, the quantity of wafers prepared
with one source charge of the MBE system
can be enhanced by a factor of 40,
enabling a tremendous reduction of the
epitaxy costs. Shorter running time and
less down time result in an enhancement
potential in throughput of about a factor
of 4 (single shift operation) to 8 (double
shift operation). In conclusion, it can be
assumed that a proper combination of
these two growth techniques, exploiting
the respective strength of each, will
lead to fully advantageous processes
and products.
Dr. Ing.
Thomas Hackbarth
received the Diploma in
Electrical Engineering/
Electronics at the
Technical University
Braunschweig in 1985,
1991 he completed
a habilitation on the
topic of surface emitting
lasers. Since 1991
he has been a scientific
member of the
DaimlerChrysler
(formerly Daimler-Benz)
Research Center in
Ulm/Germany. His
thematic research has
been in the areas of:
쐍 III-V and IV-IV
molecular beam
epitaxy
쐍 III-V semiconductor
lasers
쐍 III-V high frequency
transistors
쐍 SiGe high frequency
electronics
Dr. Hans von Känel
received the Diploma
in Physics and the Ph.D.
degree in Natural
Sciences at the ETH
Zürich, Switzerland,
in 1974 and 1978,
respectively. From 1979
to 1981 he was a
post-doctoral associate
at the Physics
Department of the
Massachusetts Institute
of Technology in
Cambridge, USA. Since
1981 he has been a
member of the Research
Staff of the Solid State
Physics Laboratory, ETH
Zürich. In 1982 he was
a visit-ing scientist at
the Fritz-Haber-Institut
of theMax-PlanckGesellschaft,Berlin. In
1990 he completed a
habilitation on Epitaxial
metal silicides on Si (111)
at the ETH Zürich.
He has been the
scientific leader of a
research group on
Si-heterostructures at
the ETH from 1985
up to now. His current
interests are scanning
tunneling microscopy
and spectroscopy
on low-dimensional
systems, ballisticelectron-emission
microscopy, and new
epitaxial deposition
techniques. He was
awarded the Latis prize
of the ETH Zürich in
1988. He is co-author of
more than 200 scientific
publications, most of
them on the structural
and electronic properties
of interfaces and
surfaces of epitaxial
heterostructures.
Unaxis Chip | 31
Magneto Electronics
Magneto Electronics
World Premiere
The first CYBERITE 10 target UHV sputtering machine worldwide is now operating at the Institute for Physical High Technology (IPHT) in Jena, Germany. A symposium on Magneto Electronics took place to mark the occasion.
Dr. Roland Mattheis, Institute for Physical
High Technology, Jena, Germany
The IPHT has a long tradition in
magnetism and thin-film deposition and
characterization and is a unique center
for concurrent research and engineering
on magneto electronics. The CYBERITE
10 system development was financed
through a German federal project together
with contributions from several German
industrial partners.
The equipment will be used for
extensive research and development of
multilayers and devices based on giant
magneto resistance (GMR). In the future
research will also be carried out on
tunneling magneto resistance (TMR),
mostly for publicly funded projects.
The institute has also established
close working relationships with the
co-investors Infineon, Robert-Bosch,
Unaxis Alzenau, Micro Hybrid Electronic
Hermsdorf (MHE), and HL Planartechnik
Dortmund, who utilize the system within
their own development process and
production of smaller quantities of wafers.
Scientific as well as strategic highlights
were presented to about 100 guests.
Representatives from Siemens, Infineon,
MHE, HL Planartechnik, Sensitec
Wetzlar, OnStream Eindhoven/NL joined
colleagues from several German
universities and research institutes.
The first address by Joachim Wecker
(Siemens Erlangen) dealt with the great
innovation potential of magneto
32 | Chip Unaxis
Talks given by
Stefan Mengel,
BMBF Bonn
(above)
Joachim Wecker,
Siemens Erlangen
(far left)
Burkhard Hillebrands,
University of
Kaiserslautern
(left)
electronics in different applications for
sensors and for electronics. Linear and
angle positioning sensors are expected
to play a prominent role in the automotive
sector. The concept of a non-volatile
Magnetoresistive Random Access
Memory (MRAM) is preparing to replace
DRAMs. Many new applications and
opportunities are envisaged in the field of
ultra high-density storage with random
access. Field Programmable Logic Gate
Arrays (FPLGA’s) as well as magnetic
couplers integrated on CMOS-chips
open up a wide variety of new and highly
innovative application opportunities for
the semiconductor industry.
Burkhard Hillebrands (University of
Kaiserslautern) gave a marvelous insight
into the dynamics of the magnetization
reversal in MRAM storage cells.
He illustrated the intrinsic processes
during magnetization reversal on a ps to
ns time scale and outlined the complexity
of processes taking place during
reorientation of the magnetization in
a memory cell.
Stefan Mengel (now BMBF Bonn)
looked back to the roots and at the
flourishing research on GMR in Germany,
which has been publicly funded from
an early stage and proved extremely
successful.
Roland Mattheis (IPHT) gave a review
of the long road leading up to the current
event. The idea in 1999 was to create a
center for magneto electronics in Germany,
which was open to all interested parties.
Until its successful realization at the
institute in Jena towards the end of 2000
a lot of obstacles had to be overcome.
Load lock of
the CYBERITE
The German Ministry of Education and
Research (BMBF) contributed – within the
framework of the magneto electronics
program – the biggest support of nearly
3.7 Million DM (75 % of the project costs)
towards this highly sophisticated
sputtering machine. The remaining 25 %
(about 1.25 Million DM) had to be raised
from cooperate partners within Germany.
The project can now boast a fully
equipped machine which is configured
with 9 of the maximum 10 targets of
300 mm in diameter each, with different
materials for buffer and capping layers
(Ta, Ru, Cr), pinning layers (NiMn, FeMn,
NiO and in the near future also precious
metals containing antiferromagnetic
targets), conduction layers (Cu and Al) and
magnetic layers (Fe, Co, CoFe and NiFe).
The load lock of the CYBERITE 10 and
equipment for the MR characterization on
wafer scale have been set up in a class
100 clean room.
Four different BMBF projects within
the magneto electronics program, direct
contracts with five partners from the
industry and three research labs from
outside Germany are in progress at
the moment.
All cooperating parties celebrated the
official launch of the machine on January
26, 2001. During the symposium a
Cr/Fe/Cr deposition process was started
on the CYBERITE by remote control and
finished during the lab visit of the first
visitors group 10 minutes later.
Dr. Roland Mattheis
received the Diploma in
Physics at the University of
Jena, Germany, in 1977 and
a Ph.D. in Physics at the
Physical Technical Institute
of the Academy of Sciences
Jena in 1984. From 1977 to
1991 he was a member of
the research staff of the
Physical Technical Institute
Jena. As a research group
leader and later as a lab
leader he worked mainly
in the field of applied solid
state physics. Since
1991 he has been a
research group leader at
the Institute for Physical
High Technology Jena
working on the preparation,
characterization and
application of ultra-thin
multilayers, mainly of
metallic materials. His
current interests are
magnetic and structural
properties of multilayers
with perpendicular
anisotropy and giant
magneto-resistance effect,
their physical connections
and applicability.
Since 2000 he has been
head of the magnetoelectronics department. His
emphasis is on magnetoresistive thin films, sensors
and memories, on Ti- and
Hg-based high temperature
superconducting thin films
and on microstructural
analysis.
He is co-author of more
than 100 scientific
publications and holds
numerous patents, most
of them in the fields of
the magnetic and structural
properties of multilayers
and of magnetic sensors.
Unaxis Chip | 33
Advanced Packaging
How Do Wafer Level Packaging
and 300 mm Get Along?
300 mm Wafer Level Packaging Moves Out of the Shadow of the 300 mm Front End.
Hans Auer, General Manager,
Advanced Packaging
System integration and packaging are responsible for the functionality, quality and economy
of microelectronic products. This is why advanced packaging technologies are now no
longer the niche technologies they used to be. Packaging moved from simple IC housing
to one of the critical enabling technologies for future IC generations.
34 | Chip Unaxis
The technology of Wafer Level
Packaging
In the last couple of years a new basic
packaging concept became one of the
most challenging back-end topics:
Wafer Level Packaging (WLP). In this
technology die and package are
manufactured and tested on the wafer,
then singulated for the assembly either
as a flip chip or directly as a surface
mount device. The unique feature of the
wafer level approach for Chip Scale
Packagings (CSP) is the absence of a
bonding technique inside the package.
The impact of 300 mm on
Wafer Level Packaging
In recent years several wafer level
packaging and wafer bumping
technologies have been established.
The most common technologies are
electroplated solder bumping,
electroplated gold bumping, photo
stenciling and classical C4 by
evaporation. Apart from the classical
C4 all of these technologies will be
transferable to 300 mm while the gold
bumping process migrates from 150
to 200 mm at the moment. Therefore
the main focus for 300 mm will be on
solder bumping and redistribution
technology based on electroplating or
photo stenciling. A seamless process
flow is the key to all semiconductor
production facilities. Due to the much
higher thicknesses of the metals, WLP
presents new challenges in lithography
and metallization compared to the
classic front end. One was the availability
of precision 14" photomasks for full-field
exposure of 300 mm wafers together
with sufficient exposure intensity and CD
control in the lithography step. Another
was achieving uniform UBM layers
by sputtering as well as uniform bump
heights by electroplating across a
300 mm wafer. This asks for a new set
of equipment specifications to address
the wafer level packaging needs and
each process step needs to be optimized
for the requirements of the total wafer
level process sequence.
start production. The demand for 300 mm
wafers will increase from 1% in 2000 to
over 17% in 2005 according to Gartner
Dataquest. The industry’s transition to
300 mm technology was heavily focused
on front-end equipment and automation
issues so far. Together with the growing
need for wafer bumping and wafer level
packaging, back end processes also
need to be performed at the wafer level.
Advanced packaging technologies for
300 mm are mostly developed for high
volume devices like DRAMs. However,
due to the much better utilization of the
silicon real estate, large logic die or high
performance ASICs may benefit even
more from 300 mm.
The number of I/Os is a prime mover
for the selection of the most cost effective
and reliable packaging technology.
For the year 2005 the International
Technology Roadmap for Semiconductors
(1999) is proposing 120 – 600 I/Os for low
cost and hand-held applications and up
to 1400 and 3200 for cost-performance
Why is Wafer Level Packaging
needed for 300 mm?
In 2001 six and in 2002 fourteen 300 mm
manufacturing sites are scheduled to
500
0,3 mm (Ball Pitch)
0,4 mm (Ball Pitch)
400
Figure 1: Range of
WLP for different
ball pitches (Source:
Electronic Trend
Publication 1999)
ASIC
I/O Count
It must satisfy the increasing demand
for higher electrical performance, further
miniaturization, highest reliability and
thermal and power management at
steadily decreasing cost. Therefore
packaging design tradeoffs can no
longer be made independently of the
chip, the board, the assembly process,
environmental aspects and the whole
microelectronic system to be built.
300
0,5 mm (Ball Pitch)
System LSI
RAM &
LOGIC
ASSP
200
100
0,8 mm (Ball Pitch)
DRAM
Micom
Flash
0
2
3
4
5
6
7
8
9
10
11
Chip Size (mm2)
Unaxis Chip | 35
Advanced Packaging
CLUSTERLINE® 300
300 mm single wafer
sputtering tool to cover
all WLP needs
and high performance applications
coupled with an on-chip performance
of up to 2 GHz. The number of bumps
for FC technology will increase due to
the electromigration limits of the solder
interconnects.
This increasing density of I/Os on the
chips has already reduced the pitch of
peripheral pads down to 70 µm, which
is within the capability of wire bonding
tools. The issue of wire bonding lies
in the nature of the sequential process.
Not the feasibility is the problem but
Figure 2: Wafer Level CSP
36 | Chip Unaxis
the interconnecting speed between all
chips from one wafer. Bumping is done
on wafer level, therefore all chips from one
wafer are bumped in the same process
step. Wafer level process steps are
independent of the number of dies and
the corresponding number of bondpads
on the wafer.
A redistribution process which enlarges
the pad pitch of the ICs is a common step
for all wafer level CSPs. An example is
given in Figure 2.
Process requirements for 300 mm
Now the question arises whether 300 mm
implies basic technology limits for WLP.
Many wafer bumping and wafer level
packaging technologies use
electroplating at the moment, but for
higher pitch and lower cost devices often
the photo stenciling process is used.
Whichever technology a company starts
out with, it is probably wise to decide on
highly flexible tools, which allow switching
or altering the processes after the initial
start with one particular technology.
Whether it requires a full field
plating base with metal
coverage all the way to the
edge or a full stack 3 to 4 metal
UBM for consecutive patterning
in a wet etching process, the
CLUSTERLINE® 300 with
its high flexibility for different
processes delivers the required
performance.
The CLUSTERLINE® is
based on the field proven
CLUSTERLINE® 200. Excellent
film uniformity, low damage soft
etch, low contamination, high
throughput, high uptime and
high yield have successfully
been transferred to the 300 mm
platform. The 300 mm
CLUSTERLINE® uses the latest
atmospheric robot design
including flexibility for 300 mm
FOUP automation and 200 mm
open cassette interfaces in
the same tool, the so called
“bridge” capability. And even
though vacuum integrity, sheet
resistivity, film stress control,
wafer temperature management
and other important process
parameters are up there with
front end requirements, its cost
of ownership is substantially
lower than the one for front end
tools – exactly where the cost
driven packaging industry
needs it.
300 mm wafer
after sputtering
of platingbase
and lithography
Electroplating as well as the photo
stencil process use sputtering for the
UBM or redistribution deposition. For
electroplating a current is passed through
a full, thin metal layer on the wafer which
acts as the seed layer or plating base for
the electro deposition. The requirements
for the under bump metallization (UBM)
are high homogeneity and good adhesion
to the die metallization and /or passivation
that guarantees high reliability. All metal
oxides of the wafer metallization have to
be removed before metal deposition to
guarantee a good electrical contact. This
is achieved by back sputtering or ICP etch
in the sputtering tool, just before the UBM
metals are deposited. To prevent
interdiffusion of the UBM or redistribution
of metals into the die-metallization a
barrier is deposited underneath the seed
layer. The basic reliability of a bump
depends on the UBM. With sputtering
tools all these layers can be deposited
on 300 mm wafers with high yield and
excellent uniformity. Cluster tools have
enough flexibility to deposit different metal
stacks and at the same time guarantee
low cost at short process times.
Plating bases need to cover the entire
wafer to allow for the plating contacts
to be placed as little as one mm from the
wafer edge. These contacts are arranged
around the full perimeter of the wafer
to guarantee a homogeneous current
distribution thereby gaining uniform
bump heights.
In the case of photo stenciling, the full
metal stack is sputtered and then etched
to form the UBM pads or redistribution
traces. High uniformity requirements are
placed upon these films in order to have
good control of consecutive etching steps.
At this stage, synergies between
the sputtering, photolithography,
electroplating and etching processes
is an essential factor in guaranteeing
the success of a high yield process.
In April this year the SECAP consortium
could successfully demonstrate that
demanding WLP applications are feasible
on 300 mm wafers. The first 300 mm
wafers were run for both bumping and
redistribution processes through the tools
of the member companies and were
validated by the Fraunhofer Institute for
Reliability and Microintegration (IZM) in
Berlin. The institute acts as the application
center for the companies’ various
advanced packaging equipment. The
first plated (not optimized) wafers were
produced across a wafer bump uniformity
of <10% or +/- 2µm (3 sigma).
A group of leading global semiconductor
equipment suppliers have joined forces
with the Fraunhofer Institute for Reliability
and Microintegration (IZM) to form a new
consortium with the goal to optimize
equipment for wafer bumping and wafer
level packaging technologies (see also story
in Chip 4, February 2001).
Operating under the name of Semiconductor
Equipment Consortium for Advanced
Packaging (SECAP), the group addresses
current challenges in semiconductor
packaging, considered one of the major
roadblocks in the microelectronic industry’s
current five-year technology roadmap.
The consortium seeks to offer a new and
powerful kind of partnership to customers
because wafer level packaging is a new
technology requiring a strong coherent
infrastructure. On the other hand all
companies within this consortium remain
independent, marketing their own
solutions in their established
business environment.
The SECAP 300 mm Initiative
As one of its first actions SECAP initiated
a 300 mm bumping project. The goal was to
develop and validate 300 mm wafer process
equipment for the industry’s conversion to
high density interconnect technologies.
For an economical production of future
microelectronic systems a packaging
strategy has to be developed in close
conjunction to the progress in the front end.
In the past months SECAP demonstrated
that no fundamental barriers exist for the
move to 300 mm. First bumped wafers
based on an electroplating process with
bump sizes down to 20 µm were presented
in April this year at the Wafer Level
Packaging Conference in Munich.
The conference gave an overview of
current market and technological trends
and introduced different technological
approaches to wafer level CSP.
For more information on SECAP please
check out the website:
www.secap.cc
Unaxis Chip | 37
Photomask
New St.Petersburg Research
Laboratory Comes On-Line!
Photomask lab in the
Class 10 clean room
Chris Constantine, Ph. D.,Principal Scientist,
Unaxis, St.Petersburg, Florida
Early this spring, the new Customer
Resource Center was opened with great
anticipation. For five years, the
St.Petersburg group has utilized the single
existing building for all manufacturing
functions including research and
development, applications support,
assembly and final test. This existing
6.000 m2 building has become very
crowded due to the strong growth seen
within the Unaxis-SP Business Units, and
our Manufacturing Group was bursting at
the seams.
38 | Chip Unaxis
Surface analysis in
the metrology lab
The new research facility incorporates
a state-of-the-art Class 100 clean room
and a large Class 10 area dedicated to
photomask applications and research.
This R&D expansion is not just a building.
It also includes several brand new
measurement tools along with eight
Unaxis production systems – critically
important for applications support and
keeping our research edge. This clean
room is one of the best I have ever seen in
a research facility; it is larger and cleaner
than the Semiconductor Fab I was
manager of earlier in my career and is of a
quality where making actual state-of-theart CMOS devices is possible.
Central to our clean room is a group of
several specialized analysis instruments,
including a new Critical Dimension
Scanning Electron Microscope (CD-SEM).
A CD-SEM is a highly specialized form of
high power microscope where electrons
are scattered across the surface of an
object and collected to form an image.
Typically, SEM’s are important to study
the small features created by the Unaxis
plasma etch and deposition systems. The
CD-SEM, however, has a unique and
different purpose. This type of microscope
is used to precisely measure the small
patterns created onto the surface of
photomasks and will be used almost
exclusively by the Photomask SBU to
check the etching accuracy of automated
photomask etch systems.
Other equipment available includes an
Atomic Force Microscope for measuring
very small etched steps in a surface, an
FT-IR (Fourier Transform InfraRed
Spectrometer) instrument to analyze the
chemical composition of a substrate or
film, three Nanospec instruments which
measure the very thin films we create on
wafers, electrical probing equipment,
optical photomask measurement systems
and optical microscopes.
We are very proud of this facility
and convinced, that this exceptional
investment will play a crucial role in
reinforcing our leading position in
photomask technology.
Please contact us for more information:
chris.constantine@unaxis.com
Silicon Front End
Electrostatic Chuck
to Boost Your Yield
Dr. Hans Hirscher, Manager Process
Development Application Systems
Figure 1: Wafer
heating during the
sputter process
with a "good”
(upper curve)
and a "bad”
(lower curve)
contact of the
wafer to the chuck
500
450
Thermal input and loss to the
substrate
Reliable temperature control of the
wafer is a key factor when looking at all
the different treatments during the
processing of a substrate. For most of
the applications it isn’t necessary to know
the exact temperature of the wafer. It is
much more important to keep it in a
defined range across the wafer.
Some processes require a certain
temperature limit, e.g. etching of wafers
with photo resist. Other processes require
certain temperature steps to be followed
(hot aluminum process typically involves
two steps) and some need to apply the
coating at a certain temperature value,
e.g. alloying and coating simultaneously.
During the experimental phase in the
lab it is necessary to measure all the
temperatures and process parameters
in combination with their temperature
influence. Finally the process sequence
must run reliably without a closed loop
temperature control. This is the case
because temperature effects are relatively
slow to adjust in the region between room
temperature to about 500 °C, where
radiation cooling effects are less dominant
than heat conductivity.
400
temperature [c]
350
300
250
200
150
100
50
0
0
5
10
15
20
25
30
35
40
45
50
55
60
time [sec]
Figure 2: Influence
of wafer contact
on heating process
with different initial
temperatures
500
450
400
350
temperature [c]
Tight control over substrate contact
to the pedestal is the key to a
cluster tool’s process reliability.
300
250
200
150
100
50
0
0
5
10
15
20
25
30
35
40
45
50
55
60
time [sec]
The thermal budget of the wafer is
affected by:
쐍 initial temperature (starting temperature
is influenced by the preceding process)
쐍 heat of condensation
쐍 radiation input from the sputter plasma
쐍 backside heater chuck
(some applications require cooling)
쐍 radiation loss from substrate to
surroundings (strongly depends on the
emissivity of the wafer or the coating
on the wafer)
The heat conduction from the wafer
to the chuck and the combination of the
above effects lead to the actual wafer
temperature.
Improving the thermal transfer
Figure 1 shows the effect of a very loose
and a relatively tight contact of the wafer
to the pedestal. With a chuck temperature
of 400 °C, the same starting temperature
at 25 °C and identical radiation parameters
of the wafer, the only difference is in the
thermal transfer. The upper curve has
Unaxis Chip | 39
Silicon Front End
a k-value of 200 W/(m2·K) while the lower
one represents a contact with a value of
10 W/(m2·K). The incident heat load due
to the coating process of 40 seconds is
0.5 W/cm2.
A heat-up phase of about 15 seconds
lifts the wafer in a temperature band of
± 5 % at 400 °C for the remaining process
time. Not so for the lower curve: here
we have a linear heat-up rate of about
6 °C/sec during the whole process time.
An additional advantage of an excellent
thermal transfer is demonstrated in
Figure 3: Cooling
process with a
“good” and a “bad”
coupling to the
pedestal
Figure 2. The situation is identical to
Figure 1 but includes two additional
curves. Besides the starting temperature
of 25 °C a starting point of 150 °C is
added. Only a slight difference is
noticeable in the good coupling, and
only within the first 10 seconds. But
in case of bad coupling an offset of
80 °C occurs.
Even more drastic is the situation
concerning cooling necessities of the
wafer. The only difference to Figure 1
is the chuck temperature at – 20 °C
300
275
250
225
temperature [c]
200
175
150
125
100
75
50
25
0
0
5
10
15
20
25
30
35
40
45
50
55
60
35
40
45
50
55
60
time [sec]
500
450
400
350
temperature [c]
Figure 4: Two step
process for hot
aluminum via filling /
heating process
with good and bad
coupling and the use
of backside gas.
300
250
200
150
100
50
0
0
5
10
15
20
25
30
time [sec]
40 | Chip Unaxis
instead of 400 °C. With the low value
coupling of 10 W/(m2·K) it still shows a
heat-up rate of 1.5 °C/sec, whereas the
lower curve very obviously demonstrates
the cooling effect.
The two examples in Figure 3 show
the influence of constant coupling
during process time. Looking at the
“two step process” for via hole filling and
the increasing surface mobility of the
deposited aluminum, the advantage
of a switchable coupling by injecting
backside gas between wafer and pedestal
can be easily demonstrated. This
backside gas – at a defined gas pressure
and at a certain gap of the wafer to the
pedestal – improves the heat transfer
dramatically. The big advantage in using
the backside gas is the possibility to inject
it, adjust the pressure or pump it off.
Just by injecting the backside gas the
thermal coupling is improved immediately.
Figure 4 shows the temperature ramping
of the “hot aluminum process”. Because
of the bad coupling to the pedestal even
the process-input energy is insufficient to
raise the wafer temperature to the 400 °C
aimed for.
Thinking of a typical process sequence
done in a cluster tool (like degassing,
etching and coating), several temperature
levels have to be controlled. One process
requires cooling of the wafer, whereas
a sputter process needs heating. As
explained above, the only reliable solution
for this is the mechanical coupling by
clamping on the edge of the wafer or by
using an electrostatic chuck.
Figure 5: Electrostatic chuck installed
Electrostatic chucks (ESC), the
solution for reliable temperature
control, full face deposition and
handling of thin wafers.
The benefits of ESCs are particularly
noticeable in dry etching applications.
There were mainly two reasons to employ
such an instrument: it requires no
mechanical clamping of the substrate
and cooling of the substrate is greatly
improved through backgas coupling.
Any need to use fixing fingers on the
wafer means that they would be etched
as well, thereby creating contamination
and particles. As no clamping items
are allowed to fix the wafer, the usual way
is just to place the substrate onto a
pedestal. The disadvantage in doing so
is the unreliable mechanical contact
of the substrate with the cooled pedestal.
Worst case would be a “three point
contact” giving bad thermal and electrical
transfer and finally an unreliable etch
result – both within the wafer and from
wafer to wafer.
The ESC is not only of interest in
etching, but also in PVD processes.
There are two main reasons: the need
of full-face deposition and the chucking
of thin wafers. The ESC has the
unique advantage of chucking the
wafer across its total area without
any mechanical fixing.
Unaxis Chip | 41
Silicon Front End
Figure 7:
Bipolar
type ESC
Wafer
Dielectric
body
Function and types of ESC
The fundamental principle of electrostatic
chucking lies in the attraction of opposite
electrical charges. There is a kind of
fundamental experiment to measure this
force: “Kirchhoff’s Potential Scale”.
Any ESC can be thought of as a
parallel plate capacitor. Having a parallel
plate capacitor on one side of a pair of
balances and a scale with weight loads on
the other, you can deduce and prove the
formula:
F = m · g = ε0 · εr · A · U2 / d2 → p = ε0 · εr · U2 / d2
Plasma
Figure 6: Unipolar
type ESC
42 | Chip Unaxis
The pressure through which a
substrate is attracted is p = F / A, and this
formula demonstrates that voltage and
distance are the crucial parameters for
obtaining high attraction.
Chuck
electrode
Technical realization
There are two basic solutions:
a. Coulomb type – unipolar and bipolar
or multipolar
b. Johnsen Rahbek type – unipolar
and bipolar
Bipolar type
The two electrodes are embedded in the
dielectric and no longer opposed, but
in the same level aside. It is the electrical
stray field that influences the opposite
charge in the substrate.
a. Coulomb type
Unipolar type
This type represents the capacitor
type with two facing electrodes, where
the plasma itself acts as one electrode.
Alternatively a direct contact wiring to
the wafer is possible. To activate the ESC
it needs to be charged up. Once this
capacitor is charged only a small leakage
current (few mA) has to be supplied. To
unchuck the wafer an electrical dechucking
sequence has to be performed that
decharges the capacitor.
Advantages:
쐍 No electrical contact to the
wafer necessary
쐍 No charge-up current across the wafer
(avoiding of possible electrical damages)
쐍 Alternating polarity is possible (reducing
the electrete effect in the dielectric)
쐍 Chucking of the wafer before deposition
process starts
Advantages:
쐍 High chucking force
쐍 Easy contacting
쐍 No problems with balancing
the electrode areas
쐍 Simple set up
Disadvantages:
쐍 Charge-up current runs vertically
through the substrate (this may
create damage to sensitive substrates
or structures)
쐍 Instabilities in the plasma have a
direct impact on chucking
쐍 Chucking only works as long
as the plasma is on
Disadvantages:
쐍 Weaker chucking force compared to
the unipolar version
쐍 More complex electrical contacting
쐍 Balancing and shaping of the
embedded electrodes is critical.
b. Johnsen Rahbek type
This type is a chuck where the charge
no longer sits on top of the electrode,
but migrates to the surface of the chuck.
The dielectric material is slightly doped
to become semiconducting especially
at elevated temperatures (more than
200 °C). Much higher chucking forces are
developed, as the effective plate spacing
is very small. The lateral spacing between
the electrodes (bipolar type) measures in
“mm”, the thickness of the dielectric upon
the electrodes measures in “µm”.
Different to the Coulomb type a certain
continuous charging current is needed to
supply the “leakage current” in the wafer –
the ESC circuit. This current comes into
the mA-region.
Again both types, unipolar and bipolar
are possible.
Check for electrical damages
Chucking a substrate means separating
electrical charges in the substrate – given
a certain current stimulated by the applied
voltage – during charge-up of the
capacitor. So it seems obvious that only
substrates with free, movable charges
or dipole orientation capability can be
attracted. But even semiconducting
wafers do have sufficient electrical
conductivity to allow a current to flow.
Nevertheless, one certainly has to keep
this charge-up situation in the substrate
in mind. Due to this charge it is absolutely
necessary to check that there is no
electrical damage to the substrate or the
existing electronic structures on the wafer.
Before using an ESC for production this
test has to be successfully completed.
Improved heat transfer
The intimate mechanical contact of the
substrate to the pedestal is the first goal
of using an ESC. As mentioned before
the thermal transfer can be significantly
improved by filling the gap between wafer
and pedestal with gas. The formula above
gives the dimension in chucking forces
or pressure (p = F/A) of the ESC which
is in balance with the pressure of the
backside gas. Typical backgas pressure
ranges from 5 to 20 mbar.
Figure 8 shows the heat conductivity
as a function of backgas pressure at
different gaps.
Figure 8: Heat
conductivity as
function of backgas
pressure at different
gaps substrate to
chuck
k-value [W/m2·K]
1000
100
g = 10 m
=
m
= 50 m
=
µm
10
0,1
1
10
100
pressure [mbar]
Detection of misalignment
Holding against the backgas pressure
there is a chance to detect:
쐍 wafer misalignment (on the chuck),
쐍 wafer breakage or chipping at the
edge and to
쐍 avoid coating (or etching) of ESC
Misalignment or breakage is immediately
detected by the rise of backgas flow. This
is checked before starting the coating
process. Especially with thinned wafers
this is a very effective method to prevent
coating of the chuck and rejects.
Unfortunately a standard chuck does
not work because thin wafers will bend
or crack when applying a gas pressure
as the pressure dependent bending
increases with 1/t 3 (t = thickness of the
wafer). For this reason a unique ESC
solution has been developed for the
CLUSTERLINE ® NRG, the Unaxis
clustertool dedicated to thin wafer
processing.
For further information please see
article “Thin is In” on page 44.
Handling of thin wafers
Reliable coupling becomes a key issue
when processing thin wafers (thickness
< 200 µm) since the temperature change
is inversely proportional to the thermal
mass and the thickness of the wafer. An
ESC with steady backgas pressure to
maintaining a steady heat transfer seems
to be the only solution today.
Unaxis Chip | 43
Silicon Front End
“Thin is In”
CLUSTERLINE® NRG – the Solution for Thin Wafer
Backside Metallization
Dr. Reinhard Benz, Product Manager,
Silicon Front End,
Unaxis Semiconductors
The CLUSTERLINE® NRG
Higher speed, more functionality, superior electrical quality plus
significant cost reduction – thinner substrates will win the race for
component performance improvement.
Figure 1: 100 µm
wafers – the bow
is not a critical
issue for Unaxis
44 | Chip Unaxis
Thinner substrates – especially for IGBTs,
(Insulated Gate Bipolar Transistors) but
also for other bipolar transistors and
diodes – enable a huge reduction of
switching losses at almost the same
current carrying capabilities. However,
decreasing the thickness down to 100 µm
on 6" and 8" silicon wafers is the main
challenge in improving the performance,
particularly of discrete ICs.
For cost reduction one major advantage
of going down to a wafer thickness of
about 100 µm is that the need for the
very expensive epitaxial process steps no
longer exists.
These extremely thin wafer products
generally show superior electrical
qualities, which results in rugged and
highly efficient components: high
breakdown voltage, lowest possible
power dissipation and narrow tolerances
of all dynamic parameters.
Thin wafer processing – the challenge
for Unaxis
To fulfill the above requirements, Unaxis
has responded with the CLUSTERLINE®
NRG without the use of additional carrier
substrates. Our technology roadmap for
future developments strongly depends on
our customers’ main objectives:
쐍 Larger wafer sizes, which require single
substrate tools for increased throughput
쐍 Thinner wafers, which are more brittle
and require reliable processes and
automated handling systems to improve
yields
쐍 Integration of pre and post treatments
like cleaning and annealing steps to
minimize manual operations
Thin wafer processing means
reduction of process complexity
Decreasing the wafer thickness also
reduces the losses associated with the
on-state voltage drop of the device.
So there is no longer a need for a thick
substrate wafer as the “mechanical
carrier”.
The CLUSTERLINE® NRG enables
all handling and different process
technologies down to the desired wafer
thickness of 100 µm.
Most of the backside processes
(Ti-Ni-Ag or similar applications) prefer
an actively cooled deposition of the
thin wafers to control stress and bow of
the wafer, using electrostatic clamping
with an active gas conduction backside
cooling.
Besides our ongoing advanced process
development for liner/barrier and
interconnect metals, we focus on the
optimization of electrostatic clamping
(ESC) for hot backside metals on thin
wafers.
Typically used for silicide processes,
the CLUSTERLINE® NRG realizes in situ
annealing steps to form a thin silicide
(e.g. Al or Au) which results in excellent
contact resistance values. Additionally,
by saving the extra oven step the manual
wafer handling steps are reduced to a
minimum. Integrating pre- and post
treatment steps together with the reliable
handling and process capabilities,
customers of the CLUSTERLINE® NRG
achieve a higher throughput and a
better yield.
To make sure that we remain the leader
in Thin Wafer Processing, we continue
to work on integrated solutions for Thin
Wafer Processing which also includes
the passivation layers as well as high rate
etching for wafer thinning.
Please find more information about
electrostatic chuck in this issue of Chip
on page 39.
For further information please contact
reinhard.benz @unaxis.com
North America
Unaxis USA Inc., St. Petersburg
sales.semi.pq@unaxis.com
Tel +1 727 577 4999
Fax +1 727 577 7035
Europe
Unaxis Balzers Ltd., Liechtenstein
sales.semi.tr@unaxis.com
Tel +423 388 52 12
Fax +423 388 54 02
China
Unaxis China Ltd., Hong Kong
sales.semi.hk@unaxis.com
Tel +852 28 76 31 80
Fax +852 28 66 61 10
Singapore
Unaxis IT Pte. Ltd.
sales.semi.sg@unaxis.com
Tel +65 890 62 88
Fax +65 890 62 90
Korea
Unaxis Korea Ltd., Seoul
sales.semi.se@unaxis.com
Tel +82 31 708 86 66
Fax +82 31 708 76 66
Asia Pacific
Unaxis Taiwan Ltd., Hsin Chu
sales.semi.hc@unaxis.com
Tel +886 35 97 77 71
Fax +886 35 98 63 63
Japan
Unaxis Japan Co. Ltd., Tokyo
sales.semi.tk@unaxis.com
Tel +81 3 32 25 90 20
Fax +81 3 32 25 90 43
Emerging Markets
Unaxis Balzers AG
sales.semi.tr@unaxis.com
Tel +41 81 784 4706
Fax +41 81 784 5402
www.semiconductors.unaxis.com