HUMBOLDT-UNIVERSITÄT ZU BERLIN
INSTITUT FÜR INFORMATIK
COMPUTER ARCHITECTURE
Lecture 4
DATA AND INSTRUCTION FORMATS,
ADDRESSING METHODS
AND MACHINE PROGRAMMING CONCEPTS
Sommersemester 2002
Leitung: Prof. Dr. Miroslaw Malek
www.informatik.hu-berlin.de/rok/ca
CA - IV - D&IF - 1
TYPES OF INFORMATION, DATA AND INSTRUCTION
FORMATS, ADDRESSING METHODS,
AND MACHINE PROGRAMMING CONCEPTS
INFORMATION TYPES
FORMATS (PDP-11, PowerPC, MOTOROLA 68000, Pentium
examples)
ADDRESSES
ADDRESSING MODES
SIMPLE I/O PROGRAMMING
PUSHDOWN STACK vs. REGISTER ORGANIZATION
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SOME BASIC INFORMATION TYPES
Information
Data
Instructions
Nonnumeric Data
Numbers
Fixed-point
Binary
Floating-point
Decimal
Binary
CA - IV - D&IF - 3
Decimal
DATA FORMATS
In selecting the number representation the following factors should be taken into
account.
1. TYPES of NUMBERS to be represented e.g., integers, real
numbers, complex numbers
2. The RANGE of VALUES to be encountered
3. The PRECISION of the NUMBER
4. THE COST of HARDWARE required to store and process the
numbers
ASCII – American Standard Committee on Information Interchange (7
bits)
EBCDIC – Extended Binary-Coded Decimal Interchange Code (8 bits)
CA - IV - D&IF - 4
INSTRUCTION FORMATS
In selecting the instruction format(s) the following factors should be
considered.
1. The number of instructions to be represented.
2. The addressability and addressing modes.
3. The ease of decoding.
4. Type of instruction field (fixed or variable)
5. The cost of hardware required to decode
and execute instructions.
OP-CODE
ADDRESS(ES)
0-, 1-, 2- or 3-addressable instruction formats
CA - IV - D&IF - 5
INSTRUCTION AND DATA FORMATS FOR PDP - 11
INSTRUCTION FORMATS
1-ADDRESS
4 BITS
Rn
3 BITS 3 BITS
Mode
Rn
3 BITS 3 BITS
DST
SRC
BRANCH
Rn
3 BITS 3 BITS
Mode
OP-CODE
2-ADDRESS
Mode
OP-CODE
10 BITS
OP-CODE
OFFSET
8 BITS
8 BITS
BRANCH ADDRESS =
[ UPDATED PC ]
DATA FORMAT
16 BITS
2' s COMPLEMENT
8 BITS
8 BITS
CHARACTER
CA - IV - D&IF - 6
CHARACTER
+
2 x OFFSET
BASIC INSTRUCTION FORMAT
& PDP-11 ADDRESS FIELD
OP CODE
ADDRESS
15
6 5
0
ADDRESS
Rn
MODE
MODE
5
4
3
2
1
0
RN
Register
(0)
0
0
0
0
0
0
R 0
(RN)+
Autoinc.
(2)
0
1
0
0
0
1
R 1
-(RN)
Autodec.
(4)
1
0
0
X(RN)
Index
(6)
1
1
0
1
1
1
R 7
If "1" Indirect
CA - IV - D&IF - 7
INSTRUCTION FORMATS for PowerPC
0
Two operand
general instruction
format
(1)
6
OP code
0
Three operand
general instruction
format
(2)
OP code
(3)
OP code
(4)
Instruction format for
logical operations with (5)
the use of crb
0
9
21 22
RB
OE
11
Sub OP code
31
16
11
Rc
I16
RA
21
16
21
crbB
16
31
Sub OP code
RB
crbA
11
31
16
RB
crbD
6
16
11
CRD OPc
6
I16/X
RA
CRD OPc
OP code
0
9
31
RA
RD/RS
6
OP code
16
11
6
0
Instruction format
for comparing II
RD/RS
6
0
Instruction format
for comparing I
11
21
0
31
Sub OP code
0
26
31
Instruction format for
(6)
OP code
RS
RA
SH
Shift/Rotate operations
MB
ME
Rc
RD – Destination Register, RS – Source Register, RA – Additional Register, I16 – Immediate Operand, X –
offset value, RB – third Register, CR – Condition Register, XER – Exeption Register, OE/Rc – setting flags,
MB – Mask Begin, ME – Mask End, SH – Shift/Rotate, crb – Conditional Register Bit, CDR – Comparing field
CA - IV - D&IF - 8
DATA FORMAT for PowerPC
0
8
Byte 0
16
24
32
40
48
Byte 1
Half word 0
56
63
Byte 7
Half word 2
Word 0
Word 4
Double word 0
•The big-endian ordering is default mode, the little-endian mode is also possible.
CA - IV - D&IF - 9
INSTRUCTION FORMAT for MOTOROLA 68000
15
14
13
12 11
10
9
8
7
6
5
4
3
2
Operation Word (First Word specifies Operation and Modes)
1
0
Immediate Operand (If Any, One or Two Words)
Source Effective Address Extension (If Any, One or Two Words)
Destination Effective Address Extension (If Any, One or Two Words)
SINGLE - EFFECTIVE - ADDRESS
INSTRUCTION OPERATION WORD
GENERAL FORMAT
15
X
14
X
13
X
12
X
11
X
10
X
9
X
8
X
7
X
CA - IV - D&IF - 10
6
X
5
4
Mode
3
2
1
0
Register
Effective Address
PENTIUM INTEGER DATA FORMATS
Sign
Byte Signed Integer
Sign
76
Word Signed Integer
15 14
Doubleword Signed Integer
Sign
31 30
0
0
Byte Unsigned Integer
7
Word Unsigned Integer
0
15
Doubleword Unsigned Integer
0
31
X
BCD
0
0
BCD
BCD
BCD Integers
X
...
X
BCD
Packed BCD Integers
BCD
BCD
...
7
BCD
7
BCD
4 3
0
BCD
4 3
0
Near Pointer
Offset or Linear Address
31
0
Far Pointer or Logical Address
Offset
Segment Selector
47
32 31
CA - IV - D&IF - 11
0
PENTIUM GENERAL INSTRUCTION FORMAT
Instruction
Prefixes
Up to four
prefixes of
1 byte each
(optional)
7
Opcode
ModR/M
1 or 2 byte
65
Mod
1 byte (if
required)
32
Reg/
Opcode
SIB
1 byte (if
required)
0
R/M
Displacement
Address
displacement
1, 2 or 4 bytes
or none
7
65
Scale
Index
Immediate
Immediate data
1, 2, or 4 bytes
or none
32
0
Base
Opcode
Smaller encoding fields can be defined within the primary opcode. These fields define the
direction of the operation, the size of displace-ments, the register encoding, condition codes, or
sign extension. The encoding of fields in the opcode depends on the class of operation.
ModR/M and SIB Bytes
• The mod and the r/m form 32 possible values: 8 registers and 24 addressing modes.
• The reg/opcode field is either a register number or 3 more opcode bits.
It’s is specified in the primary opcode.
• The r/m field can specify a register as an operand or can be combined
with the mod field to encode an addressing mode.
Certain encodings of the ModR/M byte require a second addressing byte, the SIB byte, to fully
specify the addressing form. The base-plus-index and scale-plus-index forms of 32-bit
addressing require the SIB byte. The SIB byte includes the following fields:
• The scale field specifies the scale factor.
• The index field specifies the register number of the index register.
• The base field specifies the register number of the base register.
CA - IV - D&IF - 12
NUMBER OF ADDRESSES
ONE - AND TWO - ADDRESS MACHINES
X=AxB+CxC
Instruction
Comments
LOAD A
MULTIPLY B
STORE T
LOAD C
MULTIPLY C
ADD T
STORE X
Transfer A to accumulator AC
AC
AC x B
Transfer AC to memory location T
Transfer C to accumulator AC
AC
AC x C
AC
AC + T
Transfer result to memory location X
Instruction
Comments
MOVE A, T
MULTIPLY B,T
MOVE C, X
MULTIPLY C, X
ADD T,X
T
T
X
X
X
CA - IV - D&IF - 13
A
TxB
C
XxC
X+T
THREE - AND ZERO-ADDRESS MACHINES
X=A xB+CxC
Instruction
Comments
MULTIPLY A, B,T
MULTIPLY C, C, X
ADD X, T,X
T
X
X
Instruction
Comments
PUSH A
PUSH B
MULTIPLY
PUSH C
PUSH C
MULTIPLY
ADD
POP X
AxB
CxC
X+T
Transfer A to top of stack
Transfer B to top of stack
Remove A, B from stack and replace by A x B
Transfer C to top of stack
Transfer second copy of C to top of stack
Remove C, C from stack and replace by C x C
Remove CxC, AxB from stack, replace by their sum
Transfer result from top of stack to X
CA - IV - D&IF - 14
ADDRESSING METHODS
ABSOLUTE (DIRECT) ADRESSING
- The address of operand is given explicity as part of the instruction
IMPLIED ADDRESSING
- The address is implied by the instruction (e.g.,in one-address machine, the address
of the second operand is implied as being accumulator)
IMMEDIATE ADDRESSING
- The operand is given explicitly as the instruction. No memory
access is required. Also operand could follow immediately after the instruction.
INDIRECT ADDRESSING
- The effective address of the operand is in the register or main memory location
whose address appears in the instruction. It can have more than one level.
INDEXED ADDRESSING
- The effective address (EA) of the operand is generated by adding an index register
value (X) to the direct address (DA)
- EA = X + DA
BASE ADDRESSING
- The effective address of the operand is generated by adding base register value (B)
to the address
- EA = B + DA
CA - IV - D&IF - 15
SELF-RELATIVE ADDRESSING
- Effective address is a sum of a direct address and a program counter contents (PC).
EA = DA + PC
AUGMENTED ADDRESSING
- Effective address is a concatenation of the contents of the augmented address
register (AAR) and direct address.
EA = AAR || DA
(AAR often specifies a page and DA is an address within this
particular page)
BLOCK ADDRESSING
- Address of the first word in the block is given. Length of the block is usually specified
in the instruction; or also the last address can be given; or special end-of-block
character can be given; or blocks may have fixed length. Very useful in the
secondary storage management.
CA - IV - D&IF - 16
PowerPC Family - Consortium of Apple, IBM and
Motorola (announced in 1991)
CPU
601
603
603e
604
604e
G3
750CX
750CXe
G4
7410
7450
Speed*
60-120 MHz
75-160 MHz
100-300 MHz
120-180 MHz
150-350 MHz
200-450 MHz
366-466 MHz
400-700 MHz
350-600 MHz
466-533 MHz
667-733 MHz
Instructions
3 per cycle
2 per cycle
2 per cycle
4 per cycle
4 per cycle
3 per cycle
3 per cycle
3 per cycle
19 per cycle**
20 per cycle**
unknown
L1 cache
32 KB
2x8 KB
2x16 KB
2x16 KB
2x32 KB
2x32 KB 8-10x bus multiplier
2x32 KB+ 8x bus multiplier
2x32 KB+ 10x bus multiplier
2x32 KB plus 2 MB L2 cache
2x32 KB plus 1 MB L2 cache
2x32 KB+ 256K L2+2 MB L3
cache
* as used in Apple
** AltiVec can do up to 16 simultaneous calculations + integrated 256 KB level 2
cache
CA - IV - D&IF - 17
GENERAL METHODS OF ADDRESSING
OF PowerPC
IMMEDIATE INDEX ADDRESSING MODE
-The effective address of the operand is the sum of the contents of a register named in
the instruction and a signed 16-bit offset, X, that is also given in the instruction. In
assembly language, the operand is specified in the form X(Rsrc), and the effective
address is computed as Aeff = X + [Rsrc], where Rsrc is any of the general purpose
registers R1 through R32.
REGISTER INDEX ADDRESSING MODE
- The effective address of the operand is the sum of the contents of two general
purpose registers named in the instruction. The effective address is computed as
Aeff = [Ri] + [Rj]. If zero is used in place of Ri, the value 0 is used instead of the
contents of R0. In this case the effective address is [Rj].
CA - IV - D&IF - 18
METHODS OF ADDRESSING MODES FOR BRANCH
INSTRUCTIONS OF PowerPC
ABSOLUTE
- The target address is given in the instruction
RELATIVE
- The distance between the branch instruction and the target address is given in the
instruction
REGISTER INDIRECT
- The target address is the contents of a register specified by the instruction OP code.
Instructions that use this mode are called branch to register, for simplicity.
CA - IV - D&IF - 19
PDP-11 ADDRESSING MODES
B5B4B3
Decim.
NAME
SYNTAX
MEANING
000
0
REGISTER
Rn
EA = Rn
( THAT IS,
OPERAND =
[Rn ])
010
2
AUTOINCREMENT
( Rn )+
EA = [Rn
];
INCREMENT Rn
100
110
4
6
AUTODECREMENT
INDEX
- ( Rn )
DECREMENT
X( Rn )
FETCH X;
INCREMENT PC
];
EA = [Rn
EA = X + [Rn];
001
1
REGISTER
INDIRECT
@Rn
EA = [
011
3
AUTOINCREMENT
INDIRECT
@( R n )+
EA = [[Rn
AUTODECREMENT
INDIRECT
@-( R n )
DECREMENT Rn;
INDEX INDIRECT
@X(R
101
111
5
7
n )
Rn];
]];
INCREMENT Rn;
EA = [[Rn
]];
FETCH X;
INCREMENT PC
EA = [X+[Rn]]
EA
[L]
[[L]]
= effective address
= contents of the location whose address is L (the address L can be that of a main
memory location or a register Rn)
= L points to a location where the effective
address can be found
CA - IV - D&IF - 20
PDP-11 ADDRESSING MODES WITH Rn = PC
B5B4B3
Decim.
NAME
SYNTAX
010
2
I MMEDIATE
( AUTOINCREMENT)
#N
011
3
A BSOLUTE
(AUTOINCREMENT
@#A
RELATIVE
( INDEX )
A
INDIRECT)
110
111
6
7
RELATIVE
INDIRECT
(INDEX INDIRECT)
@A
MEANING
EA = [PC];
Increment PC (That is, operand
N follows the intstruction)
EA = [[PC]];
Increment PC (that is, EA,
which is A, follows the intstr.)
F ETCH X;
I NCREMENT PC;
EA = X + [PC]
( THAT IS, EA IS A,
IT IS SPECIFIED
RELATIVE TO PC BY
DISPLACEMENT X IN
WORD FOLLOWING
INSTRUCTION)
FETCH X;
I NCREMENT PC;
EA = [X+[PC]];
( THAT IS THE ADDRESS
A OF LOCATION
CONTAINING EA IS
SPECIFIED RELATIVE
TO [PC] BY
DISPLACEMENT X IN
WORD FOLLOWING
INSTRUCTION)
EA
[L]
[[L]]
= effective address
= contents of the location whose address is L (the address L can be that of a main
memory location or a register Rn or PC)
CA - IV - D&IF - 21
= L points to a location where the effective
address can be found
THE 68000 MICROPROCESSOR
ADDRESSING MODES & INSTRUCTIONS
68000, 68020, 68030, 68040 & 68060 (two architectures)
•16-bit external & 32-bit internal - (16 data, 24 address) 64 pins
(other models have 32 data and 32 address)
•32, 16 & 8 bit words (operands)
31
16 15
7
0
byte
word
long word
8 DATA REGISTERS,
8 ADDRESS REGISTERS
(A USER STACK POINTER, SUPERVISOR STACK POINTER)
PROGRAM COUNTER
STATUS REGISTER (supervisor or trace mode select,
interrupt mask, X extended, N negative, Z zero, V overflow, C carry)
byte 0
byte 1
0
long word 0
byte 3
byte 2
2
long word 4
2
24
-2
byte 224 - 2
byte 224 - 1
CA - IV - D&IF - 22
PENTIUM ADDRESSING MODES
1) Immediate Operands
2) I/O Port Addressing
3) Register Operands
4) Memory Operands
Process or Word and Bus Widths of some
16, 16/32 and 64/32 Bit CISC Microprocessors
CA - IV - D&IF - 23