Computer
System
Fundamentals
The Central
Processing Unit
CPU
Digital Forensics Center
Department of Computer Science and Statics
U
THINK BIG
The CPU
Central Processing Unit
-
-
WE DO
http://www.forensics.cs.uri.edu
Instructions and data stored in memory
Celeron, Celeron M
XEON, Itanium, Atom, i5, i7 and more
Other common CPUs
CU (Control Unit)
Instructions
and Data
Complex Instruction Set Computing (CISC)
- Intel and AMD Processors
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Pentium Series
CPU Architecture
Memory Bus
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80386DX/SX/SL, 80486DX/DX2/DX4
00:19
CPU Architecture
Computers have a Von Neumann
Architecture
8086/8088 (XT), 80286 (AT)
- AMD - Intel Compatible
- IBM/Motorola PowerPC, PPC
- ARM Cortex
R I
00:00
Intel CPUs
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Reduced Instruction Set Computing (RISC)
- PowerPC (Power Macintosh)
- ARM Processors
- Smartphones
- Tablets
- Dec Alpha
- IBM RISC 6000
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Performs fetch/execute cycle
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Moves data to and from CPU registers and other
hardware components
Accesses program instructions and issues
commands to the ALU
ALU (arithmetic logic unit)
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Performs calculations and comparisons
FPU - Floating Point Unit
MMU (Memory Management Unit)
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supervises fetching instructions and data from
memory
02:42
04:48
CPU Architecture
Registers
Registers
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Fast (expensive) memory close to CPU
Stores frequently used instructions and data
sometimes combined with memory
management unit as Bus Interface Unit
05:55
Instruction Register (IR)
- Stores instruction fetched from memory
Can hold data, an address or an instruction
I/O Interface
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Each register is wired for specific function
Scratchpad for currently executing program
Program Count Register (PC)
- Memory location of next instruction
Manipulated directly by the Control Unit
Caches
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Special Purpose Registers
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Small storage locations within the CPU
MMU
CU
Caches
Memory Address Register (MAR)
- Where to Store/Fetch
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ALU
FPU
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Memory Data Register (MDR)
- What is stored/fetched
Registers
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Status Registers
- Status of CPU and currently executing program
I/O Interface
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I/O Registers
07:41
MMU
CU
ALU
FPU
Memory Bus
CSC414
Registers
CPU Instructions
One Bit
Accessing Memory from
the CPU
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Address from an instruction is
copied to the MAR which finds
the location in memory
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CU determines if it is a store or
retrieval
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Transfer takes place between
the MDR and memory
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MDR is a two way register
1
0
1
0
1
1
1
0
0
0
0
0
1
0
0
0
Set Bits
Address Decoder
Each memory location has a
unique address
Memory Address Register
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Memory
Data Movement (load, store)
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Shift and rotate
10:05
Fetch - Execute Cycle
- Use of specific registers can be implied by op code
Address Field
- Where to get the data for the operation
Execute
Number of operands
Length of operands
Example 32-bit Instruction Format
01000010011011110110110101100010
01000010011011110110110101100010
8-bit
24-bit
op code
address field
11:05
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Performs operation that matches
op code
Moves or transforms data
Instruction Pipelining
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Getting next instruction and data
during previous instruction's
execute cycle
12:06
Central Processing
Unit
Digital Forensics Center
Department of Computer Science and Statics
THINK BIG
WE DO
R I
http://www.forensics.cs.uri.edu
14:34
Program Counter (PC)
Memory Address
Register (MAR)
Memory Data Register
(MDR)
Instruction Register (IR)
Instruction Data
Address
(IR[address])
Memory Address
Register (MAR)
Memory Data Register
(MDR)
Execute
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Instruction sets differ by CPU type
Length of the op code
(bring instructions & data to CPU)
Decode or find instruction
Load from memory into register
Prepare ALU
Fetch
Fetch
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Operation (op code)
U
Flags to test for conditions
I/O and machine control
Memory Data Register
Instructions are comprised of
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Testing AND OR XOR
Program control (branching)
0000011000001000
CPU Instructions
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Integers and floating point
Bit manipulation instructions
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08:43
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Involve memory and registers
Arithmetic and Boolean Logic
Accumulator
Accumulator / MDR
Operation
Accumulator
Accumulator
Memory Data Register
(MDR)
Increment
Program Counter (PC)
Program Counter (PC)