Adv. Radio Sci., 7, 201–211, 2009
www.adv-radio-sci.net/7/201/2009/
© Author(s) 2009. This work is distributed under
the Creative Commons Attribution 3.0 License.
for the future. Up to now technology development has the main
responsibility to adjust the technology processes to achieve the
required lifetime. In future, reliability can no longer be the task of
technology development only. Device degradation becomes a
collective challenge for semiconductor technologist, reliability experts
and circuit designers. Reliability issues have to be considered in design
as well to achieve reliable and competitive products. For this work,
designers require support by smart software tools with built-in
reliability know how. Design for reliability will be one of the key
requirements for modern product designs.
An overview will be given of the physical device damage
mechanisms, the operation conditions within circuits leading to stress
and the impact of the corresponding device parameter degradation on
the function of the circuit. Based on this understanding various
approaches for Design for Reliability (DfR) will be described. The
function of aging simulators will be explained and the flow of circuitsimulation will be described. Furthermore, the difference between full
custom and semi custom design and therefore, the different required
approaches will be discussed.
Advances in
Radio Science
Device reliability challenges for modern semiconductor circuit
design – a review
DEVICE DEGRADATION
C. Schlünder
Negative Bias Temperature Instability (NBTI) and Hot Carrier
Injection
(HCI, also6,called
carrier Germany
stress’ Æ HCS) are nowadays
Infineon Technologies AG, Corporate Reliability Methodology, Otto-Hahn-Ring
81739‘hot
Munich,
the most critical device degradation mechanisms and became a
limiting factor in scaling of modern CMOS technologies [1-3].
Abstract. Product development based on highly integrated
semiconductor circuits faces various challenges. To ensure
the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted
by competing mechanisms like process variations and device
degradation (Fig. 1). Degradation mechanisms like Negative
Bias Temperature Instability (NBTI) or Hot Carrier Injection
(HCI) lead to parameter drifts during operation adding on top
of the process variations.
The safety margin between real lifetime of MOSFETs and
product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology
development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future,
reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and
circuit designers. Reliability issues have to be considered in
design as well to achieve reliable and competitive products.
For this work, designers require support by smart software
tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product
designs.
An overview will be given of the physical device damage
mechanisms, the operation conditions within circuits leading
to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this
understanding various approaches for Design for Reliability
(DfR) will be described. The function of aging simulators
will be explained and the flow of circuit-simulation will be
Correspondence to: C. Schlünder
(christian.schluender@infineon.com)
Fig.
device d
points o
leading
factor l
mechani
adjoinin
change o
electrica
circuit s
malfunc
Besid
HCI, w
plasma i
paramet
during p
degradat
review,
semicon
conditio
reliabilit
variation
continuo
Window for correct circuit function
Degradation
230
260
Process variation / mismatch
290
320
350
380
410
Degradation
440
470
Vth
Fig. 1: Specific window for correct circuit function
Fig. 1. Specific window for correct circuit function. In worst case
process variations and parameter degradation add up.
described. Furthermore, the difference between full custom
and semi custom design and therefore, the different required
approaches will be discussed.
1
Device degradation
Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI, also called “hot carrier stress” → HCS)
are nowadays the most critical device degradation mechanisms and became a limiting factor in scaling of modern
CMOS technologies (Schlünder, 2005, 2007; Martin, 2009).
Figure 2 shows the chain of causation of circuit IC failures
based on device degradation. The circuit function determines
the operation points of every involved device. The operation of the transistors leading to device stress depending on
the operation point and other factor like operation temperature, device geometry etc. Damage mechanisms occur leading to changes mainly of the gate oxide and adjoining parts
of the transistors. These damages lead in turn to a change of
the electrical behavior of the devices, which is described by
electrical parameters. If this electrical parameter degradation
Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.
Hot
paramet
lateral e
transisto
carriers
carrier o
gate ox
illustrate
Methodology, Otto-Hahn-Ring 6, D-81739 Munich, Germany
the degradation. VGS affects the amount of carriers within the channel
and also the energy which carriers can collect. These effects lead to a
specific VGS for maximal damage.
557544; e-mail:
202 christian.schluender@infineon.comC. Schlünder: Device reliability challenges for modern semiconductor circuit design
ductor
ts the
ndow.
ocess
nisms
arrier
on top
oduct
The
anged
main
e the
sk of
es a
xperts
esign
work,
uilt-in
e key
mage
stress
on on
arious
. The
rcuitn full
quired
arrier
adays
me a
70
Circuit
function
Device
Stress
conditions
G
chain of causation
D
V ds
S
V gs
Damage
mechanisms
Electrical
parameter
degradation
Fig. 3: Schematic Hot carrier stress condition
Application
failure
V
c
p
Fig. 3. Schematic Hot carrier stress condition.
At lower VGS the amount of carriers within the inversion layer is
voltage also the gate-source voltage has an effect on the
decreased. For higher gate-voltage the drift zone will be reduced and
degradation. VGS affects the amount of carriers within the
correspondingly
the carriers can collect less energy. The worst case
channel and also the energy which carriers can collect. These
Fig. 2 shows the chain of causation of circuit IC failures based
on
gate-source
a givenV drain-source
voltage can be determined
effectsvoltage
lead to for
a specific
leaves
a circuit specific
window,
the circuit
fails and
GS for maximal damage.
device
degradation.
The circuit
function
determines
the finally
operation
by
set
of
a
measurements.
The
gate
current
of p-MOS
devices is a
At lower VGS the amount of carriers within
the inversion
the application
malfunctions.
points
of every involved
device. The operation of the transistors
measure
for
the
amount
electron
hole
pair
generation
under
hot carrier
Beside
the two
important
degradation
leading
to device
stressmost
depending
on the
operation mechanisms
point and other layer is decreased. For higher gate-voltage the drift zone
stress
conditions.
For
n-channel
device
the
injected
gate
current
will be reduced and correspondingly the carriers can collect is hard
NBTI
HCI, which
cause transistor
durfactor
likeand
operation
temperature,
device parameter
geometry shifts
etc. Damage
toand
measure
(especially
for thicker
oxides) since
the injected
electrons
less energy.
The worst
case gate-source
voltage
for a given
ing IC operation,
plasma
inducedmainly
damage
canoxide
also
mechanisms
occur leading
to changes
of (PID)
the gate
drain-source
be determined
by setand
of adrain
measurein the voltage
electriccan
field
between gate
node. The
contribute
MOS
drifts. PID
a degraadjoining
partstoof
the transistor
transistors.parameter
These damages
leadisin
turnslow
to a down
Theisgate
currentalternatively.
of p-MOS devices
a measure
forcurrent
substrate
current
measured
Whileisthe
measured
dation
of MOS
devices,
which
occurs
during
processing
and
change
of the
electrical
behavior
of the
devices,
which
is described
by ments.
only
the quantity
electron
holeand
pair
electrical
If this the
electrical
degradation leaves
a the amount
in fact,parameters.
it can accelerate
NBTIparameter
and HCI degradation
durhighlights
only thehighlights
quantity of
potentially
injected
carrier
not their
hot carrier for
stress
conditions.
n-channel
circuit
window, thePID
circuit
fails
and finally
the application
ing specific
circuit operation.
is not
discussed
in this
review,
energy,generation
the worstunder
case condition
HCS
damagesFor
is at
slightly lower
device theSince
injected
current isofhard
measure (especially
malfunctions.
details can be found elsewhere (Martin, 2009). Generally,
gate voltages.
thegate
maximum
thetosubstrate
current curve is
Beside
the two most manufacturing
important degradation
mechanisms
NBTIinand for thicker oxides) since the injected electrons slow down in
in a semiconductor
environment
variations
reasonably flat, the error is negligible.
HCI,
which cause
transistor
parameter
shiftsthe
during
IC operation,
the electric field between gate and drain node. The substrate
processing
conditions
influence
not only
parameter
mis- Furthermore,
HCS shows temperature dependence. At lower
plasma
induced
damage
(PID)
can
also
contribute
to
MOS
current is measured alternatively. While the measured curmatch but also vary reliability degradation. In order totransistor
keep
temperature
the
mean
free path for the carrier is longer. They can
parameter
PID is a degradation
MOS
devices,
which
occurs rent highlights only
the quantity of potentially injected cartrack ofdrifts.
the reliability
variations,ofvery
fast
reliability
meacollect
higher
energies.
Accordingly,
thecase
worst
case forfor
HCS
during
processing
and in fact,
can accelerate
theonNBTI
and HCI rier and not their energy,
the worst
condition
HCSis at the
surements
are performed
onita continuous
basis
productive
(product-)
injected Since
carriers
impact the
degradation
during and
circuit
operation.
PID is not discussed inlowest
this damages
is at temperature.
slightly lower The
gate voltages.
the maxwafers (Martin
Vollertsen,
2004).
review, details can be found elsewhere [3]. Generally, electrical
in a imum
parameters
of
stressed
devices,
especially
the
threshold
of the substrate current curve is reasonably flat, the
semiconductor manufacturing environment variations in processing
).
For
n-MOSFETs
the
HCS
voltageerror
andis the
carrier
mobility
(g
m
negligible.
conditions influence not only the parameter mismatch but alsodegradation
vary
leads
to
an
increase
of
the
threshold
voltage
of
and
Furthermore, HCS shows temperature dependence. At to a
2 Hot Carrier Stress
reliability degradation. In order to keep track of the reliability
reduction
oftemperature
the carrierthe
mobility.
The
current
lower
mean free
pathdrive
for the
carriercapability
is longer. of nvariations, very fast reliability measurements are performed on a
Theydegrades.
can collect higher energies. Accordingly, the worst case
Hot Carrier Stress describes a degradation of the electrical
MOSFETs
continuous basis on productive wafers [4].
HCS
is at the lowest
temperature.
parameters of MOSFETs under a dynamic stress mode (Hu Forforthe
degradation
of (product-)
pMOSFETs
we haveThe
toinjected
consider the
carriers
impact
the electrical
parameters
stressed
et al., 1985; LaRosa et al., 1997; Thewes et al., 1999; Chen
technology
node,
especially
the gate
lengthofand
the devices,
work function
Hal.,
OT2004;
CARRIER
TRESS
the threshold
and the carrier
mobility
(gm ).channel
et al., 1999; Lu et
BravaixSet
al., 2009). The lateral
formedespecially
by the material
for thevoltage
gate electrode.
A classic
buried
For
n-MOSFETs
the
HCS
degradation
leads
to
an
increase
electrical
field
between
source
and
drain
of
a
current
drivHot Carrier Stress describes a degradation of the electrical
p-MOS device degrades in the opposite direction to n-MOSofdevices.
thresholdleads
voltage
and tothreshold
a reduction
of the carrier
mo- drain
ing
transistor
can
lead
to
high
energetic
carriers.
A
part
ofThe thetrapping
parameters of MOSFETs under a dynamic stress mode [5-10].Electron
tooflower
voltages,
increased
bility.
The
drive
current
capability
of
n-MOSFETs
degrades.
these
“hot”
carriers
cause
impact
ionization
(electron
hole
lateral electrical field between source and drain of a current driving
current and higher off-currents. For modern technologies with boron
pair generation).
of the
pair drains
subFor the degradation of pMOSFETs we have to consider
transistor
can lead to One
high carrier
energetic
carriers.
A part in
of the
these
‘hot’
doped polysilicon gates for surface channel pMOSFETs (dual
strate,
the
other
one
can
damage
the
gate
oxide
and
adjacent
the
technology node, especially the gate length and the
carriers cause impact ionization (electron hole pair generation). One
workfunction)
the p-channel
show a contrary
behavior.
carrier
of the
pair drains
in the substrate,
the3other
one canthe
damage
the work function
spacer
oxides.
The schematic
in Fig.
illustrates
stress
formed devices
by the material
for the gate
elec- In this
case
the
damage
is
dominated
by
hole
trapping.
In
general
the
gatecondition
oxide and
adjacent
spacer oxides.
The drives
schematic
in Fig. 3 trode. A classic buried channel p-MOS device degrades
for HCS.
A gate-source
potential
the transisdegradation
is comparable
transistors.
Thetrapthreshold
illustrates
stressinversion,
condition and
for HCS.
A gate-source potential
drives
tor intothe
strong
the drain-source-voltage
forms
in the opposite
directiontoton-channel
n-MOS devices.
Electron
voltageping
increases
thethreshold
drain current
decreases.
modern
the lateral field. In a classic model lucky electrons can colleads toand
lower
voltages,
increased At
drain
cur- dual
work function
HCS leads
to a reduction
of drive
lect enough energy within the drift zone beyond the pinch
rent and technologies
higher off-currents.
For modern
technologies
withcurrent
capability
of the
transistor
independently
of channel
type.pMOSoff point to create impact ionization. The injected carriers
boron
doped
polysilicon
gates for surface
channel
can damage gate- and spacer-oxide at the drain side of the Also
FETs
workfunction)
the p-channel
devices
showwith
a conthe(dual
worst
case condition
for HCS
differs
different
transistor. Therefore the device is damaged inhomogenously,
trary
behavior.
In
this
case
the
damage
is
dominated
by
technology nodes. In modern technologies (below quarter micron)
the
s
s
f
f
N
H
o
g
Fig. 2: Chain of causation of IC-failures
Fig. 2. Chain of causation of IC-failures.
the device is no longer symmetrical. Beside the drain-source
Adv. Radio Sci., 7, 201–211, 2009
hole trapping. In general the degradation is comparable to
www.adv-radio-sci.net/7/201/2009/
a
r
s
o
r
c
o
c
F
c
d
a
s
t
p
t
e
g
o
t
t
r the
nction
annel
vices.
drain
boron
(dual
n this
l the
shold
dual
urrent
ferent
n) the
G
D
Fehlstelle
im Oxid
oxide
imperfection203
Si
Si
Fig. 5: Schematic
of theInterface
interface region of MOSFETs.
O
Si
Grenzfläche
Si
Si
Slightly different
lattice structures leads to dangling
bonds
Si
Si
Si
Si
O
satured by SiSihydrogen.
Under NBTI stress the bonds
break
O
O
Si
Si
and the dangling
bonds
act
as
interface
states
Si
Si
S
Furthermore
the charged interface can reduce the carrier
mobility.
monokristalines
amorphes
mono-crystalline
amorphous
Silizium
SiOoxide
Fig. 6 illustrates
a simplified
cross-section of a NBTI silicon
stressed
Si
silicon
2 p-MOS
device. Positive oxide charges and filled donor-type interfaces are
symbolized with circles and rectangles. NBTI has a pronounced
process impact up to theunterschiedliche
passivation layer. TheFehlstelle
process
imfor
Oxidgate oxide
oxide
different lattice
growing and the hydrogen
inventory
of
the
entire
process
influence the
Gitterstrukturen
imperfection
structures
NBTI
behavior.
SiON
gate
oxides
show
enhanced
NBTI,
but the
Fig.
4:
Schematic
NBTI
stress
condition
Fig. 4. Schematic NBTI stress condition.
nitrogen
fraction
is
necessary
as
a
diffusion
barrier
in
the
gate
oxide
Fig.5:
5. Schematic
Schematic ofof
thethe
interface
region region
of MOSFETs.
Slightly of
Fig.
interface
of MOSFETs.
surface
channel
p-MOSFETs.
The
barrier
prevents
boron
penetration
The high electrical field across the gate oxide in combination with
different
lattice
structures
leads
to
dangling
bonds
satured
hySlightly+ different lattice structures leads to dangling by
bonds
doped
poly-silicon
into
the
channel.
from
the
p
an elevated
temperature
leads
to
an
electrochemical
reaction
in
the
drogen.
Under
NBTI
stress
the
bonds
break
and
the
dangling
bonds
n-channel transistors. The threshold voltage increases and satured by hydrogen. Under NBTI stress the bonds break
region of the interface between silicon and gate oxide. Fig. 5 shows a and
act the
as interface
states.
dangling
bonds act as interface states
the drain current decreases. At modern dual work function
schematic of this interface. Due to slightly different lattice structures
technologies HCS leads to a reduction of drive current capaof monocrystaline silicion and the amorphous oxide, an interface
Furthermore the charged interface can reduce the carrier mobility.
negatives Potenzial
bility of the transistor independently of channel type.
negative
potential
region is formed during and after gate oxide processing, which Fig. 6 illustrates a simplified cross-section
of a NBTI
stressed p-MOS
Also
the
worst
case
condition
for
HCS
differs
with
differconsists of only a few atomic layers and many dangling blonds. The device. Positive oxide charges and filled donor-type interfaces are
entdangling
technology
In modern
technologies
quar- symbolized with circles and rectangles. NBTI has a pronounced
open
bondsnodes.
act as interface
states.
They can (below
catch (channel-)
ter micron)
theformean
freetime
pathand
plays
longer
carriers,
trap them
a certain
emitno
them
back the
intodomichannel. process impact up to the passivation layer. The process for gate oxide
+
+
+
+ inventory
+
+ of +
nantinterface
part forstates
the p-MOS
The energy
of reduce
the hotthe growing and the hydrogen
Filled
shift thedegradation.
threshold voltage
and can
+
+
+
+
+ the+ entire
+ process influence the
carriers
andmobility.
therefore, the degradation has its maximum at NBTI behavior. SiON gate oxides show enhanced NBTI, but the
channel
carrier
p+the gate oxide of
p+ is necessary as a diffusion barrier in
higher temperatures.
Thesteps
worstafter
case gate
operation
shifts
During
high temperature
oxide point
process
these nitrogen fraction
surface
channel
p-MOSFETs.
The
barrier
prevents
boron penetration
to VDSbonds
=VGSwere
. For passivated
the latest technology
(belowAdditional
65 nm
dangling
typically bynodes
hydrogen.
n
from the p+ doped poly-silicon into the channel.
anneals
hydrogen
atmosphereis support
this
Such
node),under
the worst
case condition
at VDS =V
and higher
GS process.
Fig. 6: Simplified cross-section of a NBTI stressed p-MOS
saturated
bonds are
nofor
longer
electrical
active and
not disturb
Fig. 6. Positive
Simplified cross-section
of a NBTI
stressed
p-MOS
device.
temperature
even
n-channel
devices.
Fordo
a lifetime
as-the
device.
oxide charges
and
filled
donor
type
transistor
function.
negative bias
stress
these Positive oxide charges and filled donor type interface states are symsessment
it has During
to be considered
thattemperature
the operation
point
interface states are symbolized with circles and rectangles.
negatives
Potenzial
bolizedholes
with circles
andthe
rectangles.
Trapped
holes
impact
elecpassivated
break
open
within
an electrochemical
reaction.
negative
potential
VDS =Vbonds
very
untypical
within circuit
function. Trapped
GS =V
DD is
impact
electrical
behavior
of thethe
device.
trical
behavior
of
the
device.
The
bonds
‘dangle’
again
and
act
as
interface
states.
Filled
donor
Only the charge/discharge of very large capacitances can lead
typetointerface
states
counteract
gate electrode. For
operation
points
close to the
VDScharge
=VGSon
=Vthe
DD .
each trapped hole in an interface state one electron of the charge on the The n-channel transistor of standard CMOS-technologies with SiO2
+
+by bias
+
+
+ trap
+ them
or SiON
oxide +is+carriers,
almost
temperature
stress.
gate electrode is missing for controlling the channel. In other words
catchgate
(channel-)
time and
+
+ not
+ affected
+
+ for
+ a certain
There
is
no
comparable
electrochemical
reaction
between
the
interface
one carrier is missing in the channel. As a result the absolute value of
emit them back into channel. Filled interface states shift the
3 Negative bias temperature instability
p+
p+
and threshold
electron voltage
channel.
technologies
offering
the threshold value increases. Additionally holes can be trapped within
andFor
canfuture
reduceCMOS
the channel
carrier mobiltransistors
with
an
High-K
gate
stack
also
‘Positive
Bias
Temperature
the oxide bulk with the same effect.
n
ity.
NBTI for pMOSFETs describes the parameter degradation
Instability’
(PBTI)
a severe
device
reliability
concern.
Fig. During
6: Simplified
cross-section
of after
a NBTI
p-MOS
highbecomes
temperature
steps
gatestressed
oxide
process
V gs
under a static stress mode at elevated temperature (Jeppson
and Svensson, 1977; Schlünder et al., 1999; Krishnan et al.,
2003; LaRosa et al., 1997). A high gate-source voltage drives
the device in inversion. The carrier channel is formed, but
since the drain-source voltage equals zero, no current flows
in the channel region. Figure 4 illustrates the schematic for
the NBTI stress condition. Due to the missing lateral field in
contrast to HCS, a homogenous damage of the whole active
region can be obtained. Therefore, NBTI shows only weak
dependence on the geometry, based on oxide edge effects.
The high electrical field across the gate oxide in combination with an elevated temperature leads to an electrochemical reaction in the region of the interface between silicon
and gate oxide. Figure 5 shows a schematic of this interface. Due to slightly different lattice structures of monocrystaline silicion and the amorphous oxide, an interface region
is formed during and after gate oxide processing, which consists of only a few atomic layers and many dangling blonds.
The open dangling bonds act as interface states. They can
www.adv-radio-sci.net/7/201/2009/
device.
Positivebonds
oxide
and
filled by
donor
type
these dangling
werecharges
passivated
typically
hydrogen.
interface
states
are
symbolized
with
circles
and
rectangles.
Additional anneals under hydrogen atmosphere support this
Trapped holes impact
the electrical
behavior of the device.
NBTI
RECOVERY
process. Such saturated bonds are no longer electrical active
andthe
dostrong
not disturb
the degradation
transistor function.
During negative
Beside
parameter
another phenomenon
of NBTI
The temperature
n-channel transistor
ofthese
standard
CMOS-technologies
withopen
SiO2
bias
stress
passivated
bonds
break
challenges
reliability
assessments.
The
stress
induced
parameter
orwithin
SiON gate
oxide
is
almost
not
affected
by
bias
temperature
stress.
anrecovers
electrochemical
reaction.
degradation
very
fast
after reaction
end ofbetween
stress the
[14-21].
The
There is no comparable
electrochemical
interface
The
bonds
“dangle”
again
and
act as
interface
states.
parameter
valueschannel.
drift back
values
before
the
stress. This
effect
and electron
Forto the
future
CMOS
technologies
offering
Filled
type
interface
states
the Temperature
charge
hastransistors
to be donor
considered
for
correct
parameter
extraction
during on
stress
with an
High-K
gate stack
alsocounteract
‘Positive
Bias
the
gate
electrode.
For
each
trapped
hole
in
an
interface
state
experiments.
The
flow-chart
on
the
right
hand
side
describes
the
Instability’ (PBTI) becomes a severe device reliability concern.
one electron
the charge
on themeasurement
gate electrode
is missing
problem:
Due to of
delays
of the used
equipment
andfor
time
controlling the channel. In other words one carrier is missing
in the channel. As NBTI
a result the
absolute value of the threshold
RECOVERY
value increases. Additionally holes can be trapped within the
Beside the strong parameter degradation another phenomenon of NBTI
oxide bulk with the same effect.
challenges reliability assessments. The stress induced parameter
Furthermore
the very
charged
the carrier
degradation
recovers
fast interface
after end can
of reduce
stress [14-21].
The
mobility.
Figure
6
illustrates
a
simplified
cross-section
of a
parameter values drift back to the values before the stress. This effect
NBTI
p-MOS
device.
Positive
oxide charges
and
has
to bestressed
considered
for correct
parameter
extraction
during stress
experiments.
The flow-chart
on are
thesymbolized
right hand side
the
filled donor-type
interfaces
with describes
circles and
problem: Due to delays of the used measurement equipment and time
Adv. Radio Sci., 7, 201–211, 2009
with di
draw-bac
method i
[17]. The
extracted
mentione
paramete
measurem
time. The
decades
without s
the elect
before NB
VT-shift ( mV )
lower
y can
at the
t the
shold
HCS
d to a
of n-
unterschiedliche
different
lattice
Gitterstrukturen
C. Schlünder: Device reliability challenges for modern semiconductor circuit design
structures
and n
clock
Vt
consid
differe
introd
demands
thewithp
drawcharacter
metho
voltage
is
[17].
In c
extrac
measurem
within
pr
menti
long
reco
param
andmeasu
next
clock
freq
time.
Vth
decade
consider
witho
different
the el
introduce
before
-3
-2
VT-shift ( mV )
yer is
d and
case
mined
s is a
arrier
s hard
ctrons
. The
urrent
their
lower
rve is
NBTI stress condition. Due to the missing lateral field in contrast to
HCS, a homogenous damage of the whole active region can be
obtained. Therefore, NBTI shows only weak dependence on the
geometry, based on oxide edge effects.
-2
Fig.-17
and
thres
-1
betw
Af
in the
symbo
falsifi
Nowa
Fig.
7:aU
and
and
re
under
thresho
field
between
severe
grows
After
in the ti
symbols)
falsified
Nowaday
and a lim
understoo
field eve
severe d
grows up
measurement card. Fig. 7 shows recovery curves a different stress
device. Positive oxide charges and filled donor-type interfaces are
time. The threshold is measured continuously after end of stress. for 11
symbolized with circles and rectangles. NBTI has a pronounced
decades of time (black symbols). ). A Vth measurement sequence
process impact up to the passivation layer. The process for gate oxide
without stress was done for verification (red line).After end of stress
growing and the hydrogen inventory of the entire process influence the
the electrical
parameterformoves
backwards
very fastcircuit
to the design
values
NBTI behavior. SiON gate oxides show enhanced
NBTI, but
the reliability
204
C.
Schlünder:
Device
challenges
modern
semiconductor
extraction routines, the device is already recovered at
before NBTI stress.
nitrogen fraction is necessary as a diffusion barrier in the gate oxide of
time
of surface
thechannel p-MOSFETs. The barrier prevents boron penetration
from the p+ doped poly-silicon into the channel.
The threshold
aft
s
er
10
V @
T
dela
y=1
µs
10
0
experiments.
The flow-chart
right poly-silicon
hand side describes
boron
penetration
from theonp the
doped
into thethe
problem: Due to delays of the used measurement equipment and time
channel.
The n-channel transistor ofVstandard
CMOS-technologies
= -2.8V
Stress
with SiO2 or SiON gate oxide is
almost not affected by bias
T=125°C
temperature stress. There is no
comparable electrochemical
reaction between the interface
and
50% ofelectron
VT-shift channel. For future CMOS technologies offering
transistors
"lost" until start with an HighK gate stack also “PositiveofBias
Temperature Instability”
conventional
(PBTI) becomes a severe device
reliability concern.
measurement
s
4
NBTI recovery
aft
er
1s
V
T
@
de
la
y=
1s
Beside the strong parameter degradation another phefinal
nomenon of NBTI challenges reliability
assessments. The
relaxation
stress induced parameter degradation
recovers
very fast afcurve
ter end of stress (Rangan et al., 2003; Reisinger et al., 2006;
Campbell et al., 2006; Reisinger et al., 2007a; Grasser et al.,
2007; Reisinger et al., 2007b; Schlünder et al., 2007; Grasser
parameter
values drift back to the values
et al., 2008). The V
w/o stress
T
before the stress. This
effect has to be considered for correct
parameter extraction during stress experiments. The flow-4
-2 in Fig. 7 describes
2
4
6
chart
due
10
10
1
10 the problem:
10
10 to delays of the
used measurement equipment and time demands of Vth exstresstime
& routines,
measuring
delay
( srecovered
)
traction
the device
is already
at the pointast Vth measurement
as a function
stressof-time of the characterization.
Theof
threshold
voltage is aly time. ready
Afterrecovered.
100s stress the degraded
tage recovers by 50% in the timeframe
nd 1s after end of stress
Adv. Radio Sci., 7, 201–211, 2009
ress the degraded threshold voltage recovers by 50%
-15
er
10
s
50% of VT-shift
"lost" until start
of conventional
measurement
aft
er
1s
final
relaxation
curve
de
la
y=
1s
-10
-5
@
n methods have to
effect. Several
Fig. 6: Simplified cross-section of a NBTI stressed p-MOS
ods have device.
been Positive oxide charges and filled donor type
he literature,interface
each states are symbolized with circles and rectangles.
Trapped holes impact the electrical behavior of the device.
advantages and
Characterization
20]. A very The
fastn-channel transistor of standard CMOS-technologies with SiO2
duced in [15]
and gate oxide is almost not affected by bias temperature stress.
or SiON
There
is no comparable electrochemical reaction between the interface
old voltageFig.
can7. be
Flow-chart illustrating the critical time delay between end
and electron channel. For future CMOS technologies offering
y within of
0.5µs
after
end
of gate
stress.
It
toThe
beNBTI
stress and
characterization
ofstack
the test-device.
degratransistors
with
an
High-K
alsohas
‘Positive
Bias
Temperature
dation
recovers
very
fast.
this cannot
be achieved
witha severe
today’s
available
Instability’
(PBTI) becomes
device reliability
concern.
zers. We recorded the data with a self-developed
rd. Fig. 7 rectangles.
shows recovery
a different
NBTI hascurves
a pronounced
processstress
impact up to the
NBTI
RECOVERY
old is measured
continuously
after
end
of
stress.
for
11 and the
passivation layer. The process for gate oxide
growing
Beside
the
strong
parameter
degradation
another
phenomenon
NBTI
(black symbols).
). A Vthof measurement
sequence
hydrogen inventory
the entire process
influence the of
NBTI
challenges reliability assessments. The stress induced parameter
SiON
gatevery
oxides
enhanced
NBTI,
but the
as done forbehavior.
verification
(red
line).After
degradation
recovers
fast show
afterend
end of
of stress
stress
[14-21].
The
nitrogen
fraction
is necessary
a to
diffusion
barrier
in This
the gate
parameter
values drift
back
theasvalues
beforevalues
the stress.
effect
arameter moves
backwards
veryto fast
the
oxide
channel
p-MOSFETs.
barrierduring
prevents
has toofbesurface
considered
for correct
parameter The
extraction
stress
ss.
+
aft
-20
T
p+
s
V
p+
Delay
to
+
+
+
+
+ due
+
+
+
+
+
+
equipment and
measurement
n
routines
+
10
0
VStress= -2.8V
T=125°C
-25
VT-shift ( mV )
critical time!
+
+
af t
er
-30
V @
T
dela
y=1
µs
End of
device
negatives Potenzial
negative
potential
stress
y recovered.
to experimental
nditions, transistors
ircuits do not have
mes between stress
on (determined by
0
-6
10
-4
10
-2
10
1
VT w/o stress
2
10
4
10
6
10
stresstime & measuring delay ( s )
Fig. 7: Ultra fast Vth measurement as a function of stressand recovery time. After 100s stress the degraded
Fig. 8. Ultra fast V measurement as a function of stress- and rethreshold voltageth recovers by 50% in the timeframe
covery time.
100
s stress
degraded threshold voltage rebetween
1µs After
and 1s
after
endthe
of stress
covers by 50% in the timeframe between 1 µs and 1 s after end of
stress.
After 100s stress the degraded threshold voltage recovers by 50%
in the timeframe between 1µs and 1s after end of stress (blue
symbols). Neglecting the NBTI recovery phenomenon leads to
In contrast
to experimental
conditions,
tranfalsified
measurement
value andmeasurement
inaccurate lifetime
estimations.
sistors within
circuits
not degradation
have longmechanism
recovery
Nowadays
NBTI product
is the most
serious do
device
and
a limiting
factor
for and
technology
development.
It is not completely
times
between
stress
next operation
(determined
by clock
understood
and measures like metal gates will lead to higher electric
frequency).
field even at fixed gate oxide thicknesses. With PBTI an additional
Vthdevice
extraction
methods
to consider
Sevsevere
degradation
of have
n-MOSFETs
with this
Hi-Keffect.
gate stacks
grows
up.
eral different
methods have been introduced in the literature,
each with different advantages and draw-backs (Reisinger
et al., 2007b; Schlünder et al., 2007). A very fast method
is introduced in Reisinger et al. (2006) and Reisinger et al.
(2007a). The threshold voltage can be extracted directly
within 0.5 µs after end of stress. It has to be mentioned that
this cannot be achieved with today’s available parameter analyzers. We recorded the data with a self-developed measurement card. Figure 8 shows recovery curves at different stress
time. The threshold is measured continuously after end of
stress for 11 decades of time (black symbols). A Vth measurement sequence without stress was done for verification
(red line). After end of stress the electrical parameter moves
backwards very fast to the values before NBTI stress.
After 100 s stress the degraded threshold voltage recovers
by 50% in the timeframe between 1 µs and 1 s after end of
stress (blue symbols). Neglecting the NBTI recovery phenomenon leads to falsified measurement value and inaccurate lifetime estimations. Nowadays NBTI is the most serious device degradation mechanism and a limiting factor for
technology development. It is not completely understood and
measures like metal gates will lead to higher electric field
even at fixed gate oxide thicknesses. With PBTI an additional severe device degradation of n-MOSFETs with Hi-K
gate stacks grows up.
www.adv-radio-sci.net/7/201/2009/
CLK
CLK
A SRA
The impact of degraded electrical device parameters ondynamic
digital
stress conditions.
In region
the inverter from
has to discharge
conduct
the 1)current
VDD tocanthe
be us
the next
stage, the output signal has to be driven down to zero (better:
cuits can be easily explained at an inverter as a simple basic
block
shows the
capacitance.
In
this
region
mainly
HCS
low level). For that mainly the n-MOS device has to drive the
digital applications.
necessary current to
discharge
the (gate-) capacitance
of the
next stage.
for
this p-MOS
transistor
occurs.
C. Schlünder: Device reliability challenges for modern semiconductor
circuit design
205
Region 4) defines again a static stress
V in
mode. In this case the p-MOSFET of the
inverter is loaded by NBTI stress. The
gate electrode is on low level, all other
terminals are on high level time
(VDD). An
elevated temperature accelerating NBTI
V out
can originate from the environment or
V in
V
In out
this region mainly Hot Carrier Stress for this n-MOS device
ACT ON CIRCUIT FUNCTION
circuits
itself.
occurs. After finishing this job the circuit is infrom
a staticthe
mode
(region 2).
on after HCS or NBTI has an impact on circuit
In this region no current but leakage current
flows
within
the
The induced degradations
of the
time
trical parameter of one device leaves a specific
inverter. The n-channel device is c
underdPBTI
condition.
The input
e
f
ircuit function can not be guaranteed any more.
signal and therefore the gate of the n-MOS iselectrical
on high level,device
the drain-,parameter impact the
Fig. 9: Example for a chronological sequence of an inputnot necessarily destroyed (e.g. gate oxide
source- and substrate contact
is 10.
on
low level.
n-MOSFETs
function
ofwith
the
inverter.
First
Fig.
Example
for
a chronological
sequence
of an inputand (Fig.
cor-of all
and
corresponding
output-signal
ofSiO2
an
CMOS
inverter
Fig. a
10:
radation of the electrical behavior can lead to IC
or SiON gate oxides are responding
almost
notoutput-signal
affected,
a
high-K
n-channel
of
an
CMOS
inverter
(Fig.
9).
Four
differ8). Four
different
regions
are
marked
with
numbers
cell. The
reduction
of
the
current
drive
capability
wing examples for typical analogue and digital
describing
static
and dynamic
conditions.
device would degrade underent
these
PBTI
conditions.
Entering
regionsstress
correspo
regions
aredifferent
marked
with
numbers
describing
different
static and
thisup stage
occurs. Furthermore the
given. Furthermore a possible impact of ‘Low
3) the capacitance of the next
stage has
to conditions.
be of
charged
to high level.
dynamic
stress
ill be introduced.
For this task mainly the p-MOSFETs is required.
The device
has to
switching
thresholds
of the inverter
egraded electrical device parameters on digital
conduct the current from VDD to the
shifts and duty cycle (high level to low
y explained at an inverter as a simple basic block
capacitance. In this region mainly HCS
Fig.
9.
CMOS
inverter
as
a
simple
example
for
the
degradation
ims.
levelRegister
ratio) changes [22]. This changed
for this p-MOS transistor occurs.
g.
8: CMOS
inverter
a simple
for the
pact on circuit
function. Theas
capacitance
at the outputexample
symbolizes
Region 4) defines again a static stress
behavior of one circuit block influences
egradation
impact
circuit
The the
capacitance
at
a following
stage. on
The inverter
has tofnction.
charge or discharge
gate
mode. In this case the p-MOSFET of the
capacitance
of
the
next
stage.
the entire circuit.
e output symbolizes a following stage.
inverter
has to
inverter isThe
loaded
by NBTI stress.
The
gate electrode
on low
level,
all other
On the right hand side a part of a
harge or discharge the gate capacitance
of isthe
next
stage.
terminals are on high level (VDD). An
logic path is pictured. The degradation
5 Impact on circuit function
elevated temperature accelerating NBTI
of the different elements leads to longer
canhas
from on
the environment or
VFig.
V
in
Device degradation
after HCS
or NBTI
impact
8 shows
a outschematic
diagram
of originate
a anCMOS
inverter. The
from the circuits itself.
signal rise times. As a result the time dela
the electrical parameter of one device
pacitancecircuit
at thefunction.
outputIfsymbolizes
a following
stage.
The inverter
The induced
degradations
of the
leaves a specific window, a correct circuit function can not
(propagation delay) is increased. The set-up
electricalofdevice
parameter
s to charge
discharge
the gate
the next
stage.impact
Fig. the
9
be or
guaranteed
any more.
The capacitance
transistors are not
necessarily
changes. Furthermore the degradation im
function of the inverter. First of all a
destroyed (e.g. gate
oxide breakdown),
the degradation
ofan
the input- and
ots an exemplary
chronological
sequence
of
reduction of the current drive capability
immunity. This is critical especially at
electrical
behavior can lead
to IC CMOS
failures. Ininverter.
the following
rresponding
output-signal
of the
Four
different
of this stage occurs.
Furthermore
the
examples for typical analogue and digital
application
will be of the inverter
nominal (low power applications).
switching
thresholds
gions aregiven.
marked
with anumbers
describing
different
static and
Furthermore
possible impact
of
“Low
power
techA SRAM cell is another typical basic
shifts and duty cycle (high level to low
niques”
will be introduced.
namic
stress
conditions.
In
region
1)
the
inverter
has
to
discharge
level
ratio)
changes
[22].
This
changed
nverter as a simple example for the
can be used as another good example for
of degraded
electrical
parameters
on zero
behavior
ofdown
one circuit
block (better:
influences
ectnext
stage,The
theimpact
output
signal has
to
driven
to
on circuit
fnction.
The
capacitance
at bedevice
shows the schematic diagram for a typical 6
digital stage.
circuitsThe
can be
easily explained
anentire
inverter
as a simcircuit.
lizes a following
inverter
has to atthe
w
level).
For
that
mainly
the
n-MOS
device
has
to
drive
the
ple
basic
block
of
digital
applications.
On the right hand side a part of a
ge the gate capacitance of the next stage.
cessary current
the (gate-)
of theThe
next
stage.
Register
Figureto9 discharge
shows a schematic
diagramcapacitance
of a CMOS
logic
path is inverter.
pictured.
degradation
WL
The capacitance at the output symbolizes
a following
stage. leads to longer
of the
different elements
schematic diagram of a CMOS inverter. The
The inverter has to charge or dischargesignal
the gate
risecapacitance
times. As a resultFig.
the11.
time
delay for
for aloading
the next
Example
logic circuit
path.stage
Due to device degradation
utput symbolizes a following stage. The inverter
(propagation
delay) is increased.
The
set-up
and
hold
time
of
flip-flops
of the next stage. Figure 10 plots an exemplary
chronologithe
set
up
and
hold
time
of
flip-flops
can
change. IC-failures can
harge the gate capacitance of the next stage. Fig. 9
changes.
Furthermore
impacts
speed
and noise
cal sequence of an input- and corresponding
output-signal
of the degradation
occur, especially
in lowthe
power
application
with supply voltages less
Vy inchronological
sequence of an input- and
immunity.
This is
critical than
especially
nominal.at supply voltages less than
the CMOS inverter. Four different regions
are marked
with
t-signal of the CMOS inverter. Four different
nominal
(low
power
applications).
numbers
describing
different
static
and
dynamic
stress
conwith numbers describing different static and
A SRAM cell
is another typical basic block of digital circuits and
ditions.
In inverter
region (1)
inverter has to discharge
the next
itions. In region
1) the
hasthe
to discharge
can
be to
used
as(better:
another good
example
for circuit
stage,
the
output
signal
has
to
be
driven
down
zero
The
input signal
and degradation.
therefore theFig.
gate10of the n-MOS is on
utput signal has to be driven down to zero (better:
shows
thehas
schematic
diagram
for level,
a typical
6drain-,
transistor
SRAM
cell.
low
level).
For
that
mainly
the
n-MOS
device
to
drive
high
the
sourceand
substrate
contact is on low
t mainly the n-MOS device has to drive the
the
necessary
current
to
discharge
the
(gate-)
capacitance
of
level.
n-MOSFETs
with
SiO2
or
SiON
gate
oxides are aldischarge the (gate-) capacitance of the next stage.
out
the next stage.
In this region mainly Hot Carrier Stress for this n-MOS
device occurs. After finishing this job the circuit is in a static
mode (region 2).
In this region no current but leakage current flows within
the inverter. The n-channel device is under PBTI condition.
time
www.adv-radio-sci.net/7/201/2009/
c d e f
time
most
not affected, a high-K n-channel device would degrade
WL
under these PBTI conditions. Entering regions (3) the capacitance of the next stage has to be charged up to high level.
For this task mainly the p-MOSFETs is required.
A The device
has to conduct the current from VDD to the capacitance. In
this region mainly HCS for this p-MOS transistor occurs.
Adv. Radio Sci., 7, 201–211, 2009
time
A
g. 9: Example for a chronological sequence of an input-
B
BL
ifferent
ic and
scharge
(better:
ve the
t stage.
immunity. This is critical especially at supply voltages less becomes
than
clear that degradation in static mode and accordingly NBTI is
nominal (low power applications).
the most severe reliability concern. The NBTI degradation of the pA SRAM cell is another typical basic block of digital circuits and
channel devices within SRAM cells leads mainly to a decrease of the
can be used as another good example for circuit degradation. Fig. 10
of the challenges
cell [23]. for modern semiconductor circuit design
206
C.
Schlünder:
Device
reliability
shows the schematic diagram for a typical 6 transistor SRAM cell. stability
VA
WL
time
time
inputr (Fig.
mbers
ons.
A
BL
B
BLQ
VB
Fig.
diagram
a typical
6 transistor
Fig.10:
12.Schematic
Schematic diagram
of of
a typical
6 transistor
SRAMSRAM
cell.
cell.
The
stress
conditions
for
the
different
devices
and
the
The stress conditions and the impact of degradation can be transFig. 11: Butterfly-diagram of a SRAM cell. The two inverter
corresponding
impact
on the cell function
ferred from a single
inverter.
Fig.determine
13. Buttefly-diagram
a SRAM
cell. area
The twoof
inverter
curves
the of
form.
The
the curves
turquoise
determine
the form. The
area cell
of thestability.
turquoise square is a measure
square
is a measure
of the
fo the cell stability.
Region (4) defines again a static stress mode. In this case
the p-MOSFET of the inverter is loaded by NBTI stress. The Fig. 11 shows a ‘Butterfly-diagram’ of a 6T-SRAM cell. The two
and accordingly
NBTI
is thediagrams
most severe
inverterin static
curvesmode
determine
the form.
These
arere-used to
gate electrode is on low level, all other terminals are on high
liability
concern.
The
NBTI
degradation
of
the
p-channel
level (VDD ). An elevated temperature accelerating NBTI can
describe the stability of the cell. The area of the turquoise square is a
devices
within
SRAM cells
leads mainlyoftothe
a decrease
of the has an
originate from the environment or from the circuits itself. measure
for this
parameter.
A degradation
two inverters
stability
of
the
cell
(LaRosa
et
al.,
2006).
The induced degradations of the electrical device parameimpact on ß- and n-/p-MOS ratio of the SRAM-cell. The static noise
Figure
13 shows
a “Butterfly-diagram”
a 6T-SRAM
ter impact the function of the inverter. First of all a reduction
margin and
dynamic
read
stability decrease.ofThe
cell shows an
cell.
The
two
inverter
curves
determine
its
shape.
Thesevoltage
of the current drive capability of this stage occurs. Furtherincreased sensitivity against Soft Error Rate (SER), supply
diagrams
are
used
to
describe
the
stability
of
the
cell.
The
more the switching thresholds of the inverter shifts and the
drops, noise, etc. Furthermore an increase of access time is possible.
area
of
the
turquoise
square
is
a
measure
for
this
parameduty cycle (high level to low level ratio) changes (Reddy et
ter. A degradation of the two inverters has an impact on βal., 2002). This changed behavior of one circuit block influand n-/p-MOS ratio of the SRAM-cell. The static noise marences the entire circuit.
T
RANSISTOR
ELIABILITY
UNDER
ANALOGUE
gin and dynamicR
read
stability decrease.
The cell
shows an
In Fig. 11, a part of a logic path is pictured. The degraincreased
sensitivity
against
Soft
Error
Rate
(SER),
supply
dation of the different elements leads to longer signal rise
OPERATION
voltage
drops,
noise,
etc.
Furthermore
an
increase
of
access
times. As a result the time delay for loading the next stage
time
is
possible.
(propagation delay) is increased. The set-up and hold time Reliability evaluation of MOS transistors under analog operation
of flip-flops changes. Furthermore the degradation impacts
requires a specifically adapted approach. The operating points and thus
the speed and noise immunity. This is critical especially the
at stress conditions significantly differ. Different device parameters
supply voltages less than nominal (low power applications).
Transistorinreliability
analogue
must be6 considered
the circuitunder
design
process operation
[24-29].
A SRAM cell is another typical basic block of digital cir- Fig. 12 illustrates the background for the different impact of device
cuits and can be used as another good example for circuit
Reliability evaluation of MOS transistors under analog operdegradation
on analogue and mixed signal applications. The diagram
degradation. Figure 12 shows the schematic diagram for a
ation requires a specifically adapted approach. The operating
plots the relative degradation of the input characteristic of a MOSFET
typical 6 transistor SRAM cell.
points and thus the stress conditions significantly differ. Difas a function
of operation gate voltage and stress time. Typical NBTI
ferent device parameters must be considered in the circuit deSince the function is based on two cross-coupled invertdegradation
behavior
can be
obtained
with strongest
drift2001;
close to the
sign process (Chung
et al.,
1990; Thewes
et al., 1999,
ers, both the stress conditions of the device and the impact
threshold
voltage
and
weaker
drift
with
increasing
gate
voltages.
Schlünder et al., 2003; Chaparala et al., 2003; Schlünder et
of degradation on the circuit can be transferred from a sinfor many analog applications the effective gate-to-source
al., 2005).
gle inverter. Read and write operations are dynamic modes Since
voltage is
in the
order ofthe
a background
few 100mV,
the different
impact imof device
and lead accordingly to HCS. All the remaining period the
Figure
14 illustrates
for the
degradation
muchdegradation
stronger for
analogue
or mixed
SRAM cell is in static mode, corresponding in NBTI (and
pact ofisdevice
oncircuits
analogueofand
mixed signal
ap- signal
PBTI).
applications.
In those
circuits plots
the operation
point
relies onofthe
plications.
The diagram
the relative
degradation
theaccurate
input
of a MOSFET as a function of operation
Dependent of the data the cell has to store (1 or 0), the
matching
of characteristic
paired transistors.
gate voltage and stress time. Typical NBTI degradation bep-MOS transistor of the left or of the right inverter is unhavior can be obtained with strongest drift close to the threshder NBTI stress. Since this static mode typically occurs for
old voltage and weaker drift with increasing gate voltages.
biggest part of the lifetime, it becomes clear that degradation
Adv. Radio Sci., 7, 201–211, 2009
www.adv-radio-sci.net/7/201/2009/
The two
used to
are is a
has an
c noise
ows an
voltage
ible.
UE
peration
nd thus
ameters
device
diagram
OSFET
l NBTI
e to the
.
-source
device
d signal
ccurate
D D
nverter
quoise
[%]
/I I
p-MOS
s. Since
time, it
NBTI is
the pe of the
-5
-10
TRANSISTOR
RELIABILITY UNDER ANALOGUE
PERATION
tO
Belastung
tstress
∆ID/ID [%]
both the
on the
d write
All the
ding in
our example, the connection between drain and gate of M3 and
Fig. 11 shows a ‘Butterfly-diagram’ of a 6T-SRAM cell. The two between drain and gate of M6 leads to low gate-to-bulk/well voltages
inverter curves determine the form. These diagrams are used to of the transistors connected to the gates of M3 and M6 (M1, M2, M3,
describe
the stability
of the
cell. Thechallenges
area of the turquoise
square
is a
M6, and
M7), so
that these devices are not prone to high oxide fields.
C.
Schlünder:
Device
reliability
for modern
semiconductor
circuit
design
207
measure for this parameter. A degradation of the two inverters has an
impact on ß- and n-/p-MOS ratio of the SRAM-cell. The static noise
margin and
0 dynamic read stability decrease. The cell shows an
increased sensitivity against Soft Error Rate (SER), supply voltage
drops, noise, etc. Furthermore an increase of access time is possible.
-15
stress
Reliability evaluation of MOS transistors under analog operation
requires-20
a specifically adapted approach. The operating points and thus
the stress conditions significantly differ. Different device parameters
must be considered in the circuit design
process [24-29]. mit
characterization
Charakterisierung
Characterization
withwith
Fig.-25
12 illustrates the background for the different impact of device
|V | = 1.25 V , T=125°C
degradation on analogue and mixed Dsignal applications. The diagram
plots the
-30relative degradation of the input characteristic of a MOSFET
as a function 0.5
of operation gate1.0
voltage and stress
NBTI
1.5time. Typical 2.0
degradation behavior can be obtained with strongest drift close to the
[V]
threshold voltage and weaker drift |V
with
gate voltages.
G| increasing
Since for many analog applications the effective gate-to-source
Fig. 12: Relative degradation of the input characteristic of a
voltage
is in thedegradation
order of aof few
100mV,
the impact of
device
Fig.
14. Relative
the input
a MOSMOSFET
as a function of operation
gatecharacteristic
voltage and of
stress
time.
degradation is much stronger for circuits of analogue or mixed signal
FET asdegradation
a function offor
operation
gatepoints
voltagewith
and stress
Strong
operation
small time.
gate Strong
voltages
applications. In those circuits the operation point relies on the accurate
degradation
operation
points with
and
a weaker for
impact
on operation
withsmall
highgate
gatevoltages
voltagesand
can abe
matching of paired transistors.
obtained.
weaker impact on operation with high gate voltages can be obtained.
Fig. 13 shows the schematic diagram for a two stage operational
Since for many Here
analog
thefunction
effective
gate-toamplifier/comparator.
theapplications
correct circuit
relies
on the
source
voltage
is
in
the
order
of
a
few
100
mV,
the
impact
of
accurate matching of the input devices (M4 and M5). In the powerdevice
degradation
is
much
stronger
for
circuits
of
analogue
down mode, the bias current is switched off to avoid power
or mixed signal
In but
those
operation
consumption
of the applications.
inactive circuit,
thecircuits
supply the
voltages
are not
pointdown
reliesinonorder
the accurate
matching
of paired
driven
to allow fast
reactivation
of thetransistors.
circuit without
switching
of 15
the shows
supply the
lines.schematic
The potentials
of the
Figure
diagram
forinternal
a two nodes
stageof
theoperational
circuit are then
determined by the subthreshold
characteristics
amplifier/comparator.
Here the correct
circuitof
thefunction
devices, relies
leakage
and by the
signals applied
to thedevices
inputs. In
onpaths,
the accurate
matching
of the input
our(M4
example,
the
connection
between
drain
and
gate
of
M3 and
and M5). In the power-down mode, the bias current
between
drain
and
gate
of
M6
leads
to
low
gate-to-bulk/well
voltages
is switched off to avoid power consumption of the inactive
of the transistors connected to the gates of M3 and M6 (M1, M2, M3,
circuit, but the supply voltages are not driven down in order
M6, and M7), so that these devices are not prone to high oxide fields.
to allow fast reactivation of the circuit without switching of
the supply lines. The potentials of the internal nodes of the
circuit are then determined by the subthreshold characteristics of the devices, leakage paths, and by the signals applied
to the inputs. In our example, the connection between drain
and gate of M3 and between drain and gate of M6 leads to
low gate-to-bulk/well voltages of the transistors connected to
the gates of M3 and M6 (M1, M2, M3, M6, and M7), so that
these devices are not prone to high oxide fields.
However, high values of gate-to-channel or gate-tobulk/well voltage can occur in the case of M4, M5, and M8
according to the values of the subthreshold currents of M1,
M6, and M7 and possible further leakage paths. If in addition high temperature is applied to the circuit (e.g. provided
by the environment) NBTI conditions can occur. To evaluate
the effect of NBTI applied to the input devices M4 and M5
under active mode operation conditions, we must consider
that a defined (fixed) current is forced through these transistors by current source transistor M1.
Fig. 13: Two stage operational amplifier/comparator. The switch
drives the circuit in active or power down mode. During active
mode HCS and inhomogenous NBTI can occur. However the
worst case is the power down mode, where the input devices are
www.adv-radio-sci.net/7/201/2009/
exposed
to NBTI with full VDD.
Fig. 13: Two stage operational amplifier/comparator. The switch
Fig. 15.theTwo
stageinoperational
amplifier/comparator.
The switch
drives
circuit
active or power
down mode. During
active
drives HCS
the circuit
in active or power
down
active
mode
and inhomogenous
NBTI
can mode.
occur. During
However
the
mode HCS
and
inhomogenous
occur.
the worst
worst
case is
the
power down NBTI
mode,can
where
theHowever
input devices
are
exposed
to NBTI
VDD.where the input devices are exposed
case is the
powerwith
downfull
mode,
to NBTI with full VDD .
Therefore, M4 and M5 are operated with approximately
the same drain current before and after stress. Thus the device degradation must be compensated by an increase of the
absolute value of the gate-to-source voltage. Asymmetric operation of the input branches of the circuit in Fig. 15 or asymmetric degradation of the input devices under symmetrical
stress conditions thus leads to a stress-induced offset voltage of the circuit which equals the difference of the stressinduced threshold voltage degradations of the input devices.
7
Low Power Techniques
In the following Low Power Techniques and their possible
impact on device reliability is discussed. LP techniques are
used in circuits for modern portable applications like PDAs,
mobile phones, etc. to increase the standby time with accumulators. Furthermore Low Power is also used in high
performance application to reduce power dissipation and accordlingly the demand for cooling (CPUs/GPUs)
Low power systems/circuit designs can affect the reliability of the integrated circuits. One typical example for these
techniques are systems with “Sleep Transistors”. Figure 16
helps to understand this approach. The schematic shows a
block diagram of a test chip with several Low Power Techniques assembled together to evaluate the behavior of the different techniques. We focus here on the “Sleep Transistor”
approach which is based on leakage power control.
A p-MOS connects the external VCC to supply rails (Virtual VCC), or an nMOS connects the external ground VSS
to the ground rail (Virtual VSS). These sleep transistors are
distributed throughout the layout. The area overhead is about
Adv. Radio Sci., 7, 201–211, 2009
Fig. 15: Sketched block diagram of the Sleep Transistor
Since
process
evolution
willmode
leadis entered
to higher
device stress and
approach. The schematic shows a block diagram of a test chip with
Low
Power
Technique.
When idle
the sleep
several Low Power Techniques assembled together to evaluate the reliability
transistors
turnedmargins
off and VCC
are no in
longer
connected
to
safety
decrease
modern
technologies,
circuit
behavior of the different techniques. We focus here on the ‘Sleep
external VCC. Whereas idle blocks dissipate no power other
reliability
is
not
longer
a
task
only
for
technology
development
but
circuit blocks are still working without restrictions.
Transistor’ approach which is based on leakage power control.
208
C. Schlünder: Device
also reliability
for circuitchallenges
designers.for modern semiconductor circuit design
APPROACHES FOR DESIGN FOR RELIABILITY
In the following the function of Aging Simulators will be briefly
introduced. The typical flow of circuit simulation will be discussed
and a simple example for circuit design optimization will be given.
Furthermore constraints for semi-custom design will be evaluated.
Since process evolution will lead to higher device stress and
reliability safety margins decrease in modern technologies, circuit
reliability is not longer a task only for technology development but
also for circuit designers.
fre sh
1y
10 y
well
A p-MOS connects the external VCC to supply rails (Virtual
the
VCC), or an nMOS connects the external ground VSS to the ground
200 ps
sible
rail (Virtual VSS). These sleep transistors are distributed throughout
o the
the layout. The area overhead is about 3%-6%. A control block
4ccur.
Blockswitches
diagram
a test
chipand
forwatches
different
Low Power
the of
sleep
transistors
clock.
iques.
WeWhen
focus
sleep
transistor
which
and
idlethe
mode
is entered
the sleepapproach,
transistors turned
off and VCC
Fig. 16: Example
for 1y
a output
signal of a example circuit by
es
consumption
by toswitching
off complete
hat apower
are no
longer connected
external VCC.
Whereas idle blocks
fre sh
10 y signal of a example circuit by an
Fig. 18. Example
for a output
an
aging
simulator.
The
output
signal can be plotted and
blocks
from
powerother
supply.
But are
Lowstill Power
rrent
dissipate
no power
circuit blocks
working without aging simulator. The output signal can
be plotted and compared
compared
before
and
after
given
200 ps
ques can
also impact
theimpact
circuit
restrictions.
This can
thereliability.
circuit reliability of whole system. before and after
given operation times. operation times.
ame
The Operation
times of different blocks varies, this leads to various
Fig. 14 Block diagram of a test chip for different Low Power
Fig.
Block diagram
of a test
chip
for differentdelay
Low within
Power the
must
stages
of16.parameter
The
propagation
Techniques.
We degradation.
focus the sleep
transistor
approach, which
Techniques.
We
focus
the
sleep
transistor
approach,
which
reduces
hand degraded
circuit
blocks
the opportunity
16: Example
for a output
signal
of aget
example
circuit by for pareduces
powerdue
consumption
switching
off complete
e-todifferent
can vary,
to different by
operation
(stress)
time. This Fig.
can other
power
consumption
by switching
off
complete
circuit
blocks
from an aging
simulator.
The
output
signal
can
be
plotted
and
rameter
recovery
as
already
discussed
in
the
NBTI
recovery
circuit
blocks
from
power
supply.
But
Low
Power
the
have an impact on timing between the different circuit blocks. On the
before and after given operation times.
techniques
circuit reliability.
power
supply.can
Butalso
Lowimpact
Powerthe
techniques
can also impact the cir- compared
chapter.
nder
other hand degraded circuit blocks get the opportunity for parameter
cuit reliability.
ffset
recovery already discussed in the NBTI recovery chapter.
8 Approaches for design for reliability
uced
VCC
In the following the function of Aging Simulators will be
briefly introduced. The typical flow of circuit simulation will
be discussed and a simple example for circuit design optimization will be given. Furthermore constraints for semipact
custom design will be evaluated.
s for
Block
Block
Block
. to
Since process evolution will lead to higher device stress
ower
and
reliability safety margins decrease in modern technoloA
B
C
ower
gies, circuit reliability is not longer a task only for technology
development but also for circuit designers.
f the
For this work the designers have to be supported by smart
VSS
are
software tools with built-in reliability know how. Already
this
Fig. 15: Sketched block diagram of the Sleep Transistor available are aging simulators for full-custom design. These
Fig. 17. Sketched block diagram of the Sleep Transistor Low Power
with
LowTechnique.
Power Technique.
When idle mode is entered the sleep tools are reasonable for relatively low numbers of transistors
When idle mode is entered the sleep transistors turned
the
transistors
turned
off
and
VCC are no longer connected to (analog/RF circuits). The circuit simulators with built-in reoff and VCC are no longer connected to external VCC. Whereas
leep
external
VCC.
Whereas
idle
blocks dissipate no power other liability can simulate entire circuit blocks. The parameter
idle blocks dissipate no power other circuit blocks are still working
circuit
blocks
are
still
working
without restrictions.
degradation can be calculated individually for each device.
without restrictions.
The circuit designer can adjust the characteristic of each device (e.g. geometry, type).
3%–6%.
A controlFOR
blockD
switches
sleep
transistors and
APPROACHES
ESIGN the
FOR
RELIABILITY
Afterwards the circuit can be simulated again and in iterawatches clock.
tion reliable solutions can be found. Figure 18 shows an exIn the following the function of Aging Simulators will be briefly
ample for a circuit simulation with an aging circuit software
When idle mode is entered the sleep transistors turned off
introduced. The typical flow of circuit simulation will be discussed
tool. The output signal can be plotted after a given operation
and VCC are no longer connected to external VCC. Whereas
and a simple example for circuit design optimization will be given.
time. The designer can check whether the results achieve the
idle blocks dissipate no power other circuit blocks are still
Furthermore constraints for semi-custom design will be evaluated.
requirements.
working without restrictions. This can impact the circuit reSince process evolution will lead to higher device stress and
liability of whole system. The operation times of different
The goal of circuit aging simulators is to describe the
reliability safety margins decrease in modern technologies, circuit
blocks varies, this leads to various stages of parameter degrachange of the transistor model (e.g. BSIM) due to dereliability is not longer a task only for technology development but
dation. The propagation delay within the different can vary,
vice degradation as a function of age. The information of
also for circuit designers.
due to different operation (stress) time. This can have an imthe deviation of a parameter as function of age is required
pact on timing between the different circuit blocks. On the
[1BSIM-Par=f(age)]. Different degradation effects have to
Adv. Radio Sci., 7, 201–211, 2009
www.adv-radio-sci.net/7/201/2009/
parameters (e.g
For this work the designers have to be supported by smart software
without stress,
tools with built-in reliability know how. Already available are aging
Afterwards the circuit can be simulated again and in iteration
the circuit. A s
simulators for full-custom design. These tools are reasonable for
all different op
reliable
solutions
can beoffound.
Fig.(analog
16 shows
an example
for a circuit
relatively
low numbers
transistors
/ RF circuits).
The circuit
Id
simulator. In th
simulation
with
an
aging
circuit
software
tool.
The
output
signal
can
C. Schlünder:
Device reliability challenges for modern semiconductor
circuit
design
209
simulators with built-in reliability can simulate entire circuit blocks.
Based on the f
be The
plotted
after degradation
a given operation
time. The
designer
parameter
can be calculated
individually
for can
each check
new model car
device.
The
circuit
designer
can
adjust
the
characteristic
of
each
device
whether
the
results
achieve
the
requirements.
Afterwards the circuit can be simulated again and in iteration
individual degr
(e.g.
geometry,
type). aging simulators is to describe the change of the
The
goal of circuit
reliable
solutions
can
be found. Fig. 16 shows an example for a circuitThis netlist
Id
transistorwith
model
BSIM)
to device
degradation
as signal
a function
this aged circu
simulation
an(e.g.
aging
circuitdue
software
tool.
The output
can
age. The
information
the deviation
a parameter
as function
of
simulation
of t
beofplotted
after
a given ofoperation
time.of The
designer
can check
achieve the req
age is the
required
= f(age)]. Different degradation effects
whether
results[∆BSIM-Par
achieve the requirements.
have
be of
taken
intoaging
account
(typicallyisHCS
and NBTI).
In Fig. of
17 the
anFig. 19 show
The to
goal
circuit
simulators
to describe
the change
of the critica
output characteristic
of a virgin
is degradation
compared with
transistor
model (e.g. BSIM)
due todevice
device
as asimulated
function
operational am
degraded device.
The
of age. The information of the deviation of a parameter as functionM14/M15.
of
Fig. 18 shows the sketched simulation flow. The reliability
potential. Thus
age is required [∆BSIM-Par = f(age)]. Different degradation effects
Vd
simulation has to be integrated in the design flow. Based on a large
mode are avoid
have to be taken into account (typically HCS and NBTI). In Fig. 17 an
not degrade. Th
number of stress experiments with various stress- and characterization
Fig. 17: Output characteristic of a MOS transistor before
output characteristic of a virgin device is compared with simulated
the power dow
and after stress. An aging simulator simulate this
operation points degradation models can be fitted to the real
degraded
device.
leakage curren
degradation for every device in a circuit
degradation behavior of the device of the used technology.
demand.
Fig.
18
shows
the
sketched
simulation
flow.
The
reliability
The virgin circuit can be simulated based on standard device
Vd
simulation has to be integrated in the design flow. Based on a large
this work
the designers have
supported
by smartbefore
software
Fig. 17:ForOutput
characteristic
of to
a be
MOS
transistor
with
built-in characteristic
reliability
know
how.
available
aging
Fig.
19. stress.
Output
of asimulator
MOSAlready
transistor
before are
and
afand tools
after
An aging
simulate
this
simulators
for
full-custom
design.
These
tools
are
reasonable
ter stress.for
Anevery
agingdevice
simulator
degradation
in simulate
a circuitthis degradation for everyfor
relatively
numbers of transistors (analog / RF circuits). The circuit
device inlow
a circuit.
simulators with built-in reliability can simulate entire circuit blocks.
For
thisparameter
work the degradation
designers have
supportedindividually
by smart software
The
can tobebecalculated
for each
tools device.
with
built-in
reliability
know
how.HCS
Already
are
aging
be taken
account
(typically
and available
NBTI).ofIn
Fig.
19
Theinto
circuit
designer
can adjust
the characteristic
each
device
simulators
for full-custom
These device
tools are
reasonablewith
for
(e.g.
geometry,
type). design.
an output
characteristic
of a virgin
is compared
relatively
low numbers
of transistors
simulated
degraded
device. (analog / RF circuits). The circuit
simulators
with
built-in
reliability
can simulate
entire flow.
circuit The
blocks.
Figure 20 shows the sketched
simulation
reThe parameter
degradation
can
be
calculated
individually
for
each
liability simulation has to be integrated in the design flow.
device.Based
The circuit
can adjust
characteristic
of each
on a designer
large number
of the
stress
experiments
withdevice
vari(e.g. geometry,
type).
ous stress- and characterization operation points degradation
models can be fitted to the real degradation behavior of the
device of the used technology.
The virgin circuit can be simulated based on standard device parameters (e.g. BSIM). Besides the simulation of the
circuit function without stress, the tool extracts the duty cycle for each device within the circuit. A suitable input pattern stimulates the circuit function and all different operation
points during operation are integrated by the simulator. In
this manner the tool collects the aging of each device. Based
on the fitted degradation model the aging simulator creates
a new model card for each device. After this step a new
flat netlist with individual degraded model cards or subcircuit substituions is available.
This netlist describes the circuit after stress. A new simulation of this aged circuit can be done and can be compared
with the first simulation of the fresh circuits. The designer
can check if the result achieve the requirement and can improve the circuit if necessary.
Figure 21 shows an example for Design for Reliability
(Thewes et al., 2001). The gates of the critical input devices M4/M5 of the already discussed operational amplifier
(chapter 6) are connected to VDD via additional transistors
M14/M15. The gate and all other terminals are pulled to the
same potential. Thus high electrical gate oxide fields during
power down mode are avoided. No NBTI stress occurs, the
device parameters do not degrade. The necessary enable sigFig. 18: Circuit simulation flow. The reliability simulation
nal is already available to select the power down mode. Since
has to be integrated in the design flow
the additional devices have to balance only leakage currents,
the inserted devices lead to an only small additional area demand.
Fig. 18:
Circuit simulation flow. The reliability simulation
www.adv-radio-sci.net/7/201/2009/
has to be integrated in the design flow
parameters (e.g. BSIM). Besides the simulation of the circuit function
number
of stress,
stress the
experiments
withthe
various
stresscharacterization
without
tool extracts
duty cycle
forand
each
device within
operation
points
degradation
models
can
be
fitted
the real
the circuit. A suitable input pattern stimulates the circuit to
function
and
degradation
behavior
of
the
device
of
the
used
technology.
all different operation points during operation are integrated by the ENABLE
The virgin
circuit
can the
be tool
simulated
on standard
device
simulator.
In this
manner
collectsbased
the aging
of each device.
parameters
BSIM).
Besides the
simulation
of the
circuit creates
function
Based on(e.g.
the fitted
degradation
model
the aging
simulator
a
without
stress,card
the for
tooleach
extracts
theAfter
dutythis
cycle
eachflat
device
new model
device.
stepfor
a new
netlistwithin
with
IN theindividual
circuit. Adegraded
suitable model
input pattern
the circuit function
and
cards orstimulates
subcircuit substituions
is available.
all different
operation
points
operation
integrated
by the
This netlist
describes
the during
circuit after
stress.are
A new
simulation
of
IN +
this agedIncircuit
can be the
done
can bethecompared
first
simulator.
this manner
tooland
collects
aging ofwith
eachthe
device.
simulation
the fresh
circuits.model
The designer
cansimulator
check if the
resulta
Based
on theoffitted
degradation
the aging
creates
achieve
requirement
and can After
improve
circuit
if necessary.
new
modelthe
card
for each device.
thisthe
step
a new
flat netlist withENABLE SI
Fig. 19
shows an
example
for Reliability
[26].
The gates
individual
degraded
model
cardsfororDesign
subcircuit
substituions
is available.
ofThis
thenetlist
critical
input the
devices
of the
already
discussed
describes
circuitM4/M5
after stress.
A new
simulation
of
via additional
amplifier
aredone
connected
to Vbe
DD compared
thisoperational
aged circuit
can be
and can
withtransistors
the firstactive mode
M14/M15.
gate and
all other
are pulled
the result
same
simulation
of The
the fresh
circuits.
The terminals
designer can
check to
if the
potential.
Thus
high
electrical
gate
oxide
fields
during
power
down
achieve the requirement and can improve the circuit if necessary. Fig. 19: Exam
Fig.19
18:
Circuit
simulation
flow.
The
simulation
mode
are
avoided.
No
NBTIforstress
occurs,
the device
parameters
do
Fig.
shows
an
example
Design
forreliability
Reliability
[26].
Theto
gates
Fig.
20.toCircuit
simulation
flow.
Theflow
reliability
simulation
has
transistors M
has
be integrated
in the
design
not
degrade.
The
necessary
enable
signal
is
already
available
to select
during the ‘P
ofbethe
criticalin input
devices
integrated
the design
flow. M4/M5 of the already discussed
the power amplifier
down ode.are
Since
the additional
devices
have to balance
only
via additional
transistors
operational
connected
to VDD
leakage
currents,
the
devices
lead
to
an
only
small
additional
area
M14/M15. The gate and all other terminals are pulled to the same
demand.
potential. Thus high electrical gate oxide fields during power down
mode are avoided. No NBTI stress occurs, the device parameters do
not degrade. The necessary enable signal is already available to select
the power down ode. Since the additional devices have to balance only
M14lead M15
M1 additional area
leakage currents, the devices
to an only small
demand.ENABLE
M4
IN -
M14
M15
M1
M5
IN +
ENABLE
ENABLE SIGNAL :
IN -
VDD
VSS
IN +
active mode
M4
M6
M7
M5
power-down mode
ENABLE SIGNAL :
Fig.21.
19:Example
Example
Design
for reliability:
The critical
input
Fig.
forfor
Design
forVDD
Reliability:
the critical
input trantransistors
are protected
against
NBTI stress
sistors
M4 andM4
M5and
are M5
protected
against NBTI
stress during
the
M6
M7
VSS
duringDown
the ‘Power
“Power
Mode”.Down Mode’.
active mode
power-down mode
Fig. 19: Example for Design for reliability: The critical input
Adv. Radio Sci., 7, 201–211, 2009
transistors M4 and M5 are protected against NBTI stress
during the ‘Power Down Mode’.
completely different approach is necessary. A possible consideration
of reliability in semi-custom designs is the calculation of parameter
degradation as a part of on-chip-variations. Stress induced parameter
variation can be transformed in propagation-delays [30].
210
designer can consider reliability aspects early in the design phase and
can develop reliable and competitive products.
The different requirements and constraints of “Design for
full custom and semi-custom design were pointed out.
C. Schlünder: Device Reliability”
reliability for
challenges
for modern semiconductor circuit design
For full-custom design capable aging simulators are already available.
The function and integration into the design were briefly discussed.
Forthesemi-custom
design
differentIf approach
required.
critical time
pathsa again.
necessaryisfurther
gateBywill
transferring
device
degradation
into a shift of induced
the propagation
of is
be replaced
until
every degradation
time delay
conflict
basic
gate
elements
‘Design
for
Reliability’
can
be
integrated
into
solved.
semi-custom design flows. Smart software tools can check time critical
paths after simulated aging and ensures the circuit function for the
entire required lifetime.
10
Summary
REFERENCES
Fig. 20: Critical time path of a semi-custom design (e.g.
base22.band
chip).
the
designers do
not have
a direct
Fig.
Critical
timeSince
path of
a semi-custom
design
(e.g. base
band
access
to
single
devices
within
the
design
tool,
a
smart
chip). Since the designers do not have a direct access to single
deapproach is necessary to implement reliability checks into
vices within the design tool, a smart approach is necessary to imthe design flow.
plement reliability checks into the design flow.
Smart software tools can check time paths within the product. In
9the case
Constraints
for semi-custom
designby faster ones. On the
of time conflicts,
gates can be replaced
other hand the tools have to take area demand and power consumption
into digital
account.application a more automated design approach is
For
The
tool can
selectelements
one of several
differentautomatically
versions of gates
used. The
library
are placed
bywith
the
the same function (e.g. XOR). The tool decision for substitution is
design
tool. The designers do not know in advance where a
based on
single element
is placed.
They have no direct access to the
•
Performance
requirements
single devices.
Therefore
automated
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•
Stability against process
variations
make it•difficult
to
manually
determine
reasonable operation
Stability against degradation
• for
Area
demand
conditions
single
library elements.
•
Power
consumption
A single
library
element is used in many different subcircuits, and within, exposed to a lot of different applicaThe different demands have to be weighted. This is very difficult
tions/operation
conditions.
all of
these
combinations
for the tool and therefore
a keyFor
factor
of the
software
tool. Aftera
delay-calculation
would
be
necessary,
since
digital
design
replacement of gates the simulator checks the critical time paths.
If
further gate
will be replaced
until every degradation
isnecessary
delay driven.
Therefore,
in semi-custom
design ainduced
comtime conflict
is solved.
pletely
different
approach is necessary. A possible consideration of reliability in semi-custom designs is the calculation of parameter degradation as a part of on-chip-variations.
Stress induced parameter variation can be transformed in
propagation-delays (Pompl et al., 2006).
Smart software tools can check time paths within the product. In the case of time conflicts, gates can be replaced by
faster ones. On the other hand the tools have to take area
demand and power consumption into account.
The tool can select one of several different versions of
gates with the same function (e.g. XOR). The tool decision
for substitution is based on
– performance requirements
– stability against process variations
– stability against degradation
– area demand
– power consumption
The different demands have to be weighted. This is very
difficult for the tool and therefore a key factor of the software tool. After replacement of gates the simulator checks
Adv. Radio Sci., 7, 201–211, 2009
This paper gives an overview of device degradation chalC. Schlünder, Tutorial,
IRPSdesign.
2005
lenges [1]
of semiconductor
circuit
The most critical
[2]
C.
Schlünder,
Tutorial,
IRPS
2007
device degradation mechanisms NBTI and HCS were de[3]
A. Martin,
JVST B 2009
scribed.[4] Furthermore
critical
stress conditions in cirA. Martin et al.,
Micr.device
Rel. 2004.
cuits of[5]digital/mixed
applications
Hu et al., signal
J. of S.S.
Circ. 1985 and low power techLaRosa et al.,
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niques [6]
were G.
highlighted.
[7]
R. Thewes et al,
IRPS 1999
Since process evolution will lead to higher device stress
[8]
Y.Y.Chen et al.,
VLSI 1999
and reliability
margins IRPS
decrease
[9]
M.F.safety
Lu et al.,
2004 in modern technologies, circuit
a task only for technology
[10] reliability
A. Bravaix et is
al.,not longer
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[11] Jeppson
et al.,forJ.Appl.Phys.1977
development
but also
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[12] Aging/reliability
C. Schlünder et al. ESREF
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challenge.
simulators
[13] A.T. Krishnan et al., IEDM 2003
the circuits
saveetcosts.
The
can consider re[14] and
S. Rangan
al.,
IEDM designer
2003
liability[15]aspects
early etinal.,the design
phase and can develop
H. Reisinger
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J.P.Campbell et products.
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reliable[16]
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H. Reisinger et al., TDMR 2007
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different
requirements and constraints of “Design for
[18] T. Grasser et al.,
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forReisinger
full custom
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[19] H.
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II
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design
Schlünder
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IRPS
2008capable aging simulaT. Grasser
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tors are[21]
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[22] were
V. Reddy
et al.,discussed.
IRPS 2002
the design
briefly
For semi-custom design a
[23] G. LaRosa et al.,
IRPS 2006
different
approach
is
required.
By
transferring device degra[24] J. Chung et al.,
IEDM 1990
dation [25]
into aR.shift
of
the
propagation
Thewes et al.
IEDM 1999delay of basic gate elR. Thewes
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ements[26]
“Design
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can
be integrated into semiC. Schlünder
al., software
IRPS 2003 tools can check time
custom[27]
design
flows. etSmart
[28] P. Chaparala et al.,
P2ID 2003
critical[29]
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Schlünder et al. Micro. Rel. 2005
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thePompl
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