LabVIEW FPGA Module
A tutorial using Xilinx
Spartan 3-E Dev Kit
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
1
1
Xilinx Spartan 3-E Dev Kit
Serial ITF
VGA ITF
ADC in
ADC out
Ethernet ITF
DIO
BTNS N
W
Encoder
Massimo Lanzoni
8 LED
E
S
2x16 LCD
LabVIEW FPGA Module Tutorial
4 SW
2
2
Introduction to LabVIEW FPGA for cRIO
5/17/2011
FPGA Palette
FPGA specific functions
•Programming structures
•Device I/O
•Arithmetic and Boolean Logic
•Arrays and clusters
•Timing
•Math and control functions
•Synchronization and FIFOs
•Lookup tables
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
3
The functions palette in FPGA will display only the VIs that are supported under
in this environment. Many of all the LabVIEW structures, such as the while
loop, for loop, and sequence structure, are supported under LabVIEW FPGA.
There are also other standard LabVIEW functions for arithmetic operations,
Boolean logic, timing and synchronization, a Device I/O and others.
33
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Basic FPGA VI
F=(A+B)CD
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
4
Programming with LabVIEW FPGA is very simple. If you have LabVIEW
experience, you will have very few additional concepts to learn. The same
structures and functions are used for coding.
In this example, we have a simple VI where two numbers are added and
multiplied to the product of two other numbers.
44
Introduction to LabVIEW FPGA for cRIO
5/17/2011
LabVIEW Mapped to FPGA
Implementing Logic on FPGA: F =(A+B)CD
F
A
B
C
D
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
5
The heart of RIO is an FPGA chip. You can think of an FPGA as having logic
gates such as AND and OR gates that are unconnected. Your LabVIEW program
is used to connect these gates and implement your logic.
The process of mapping graphical code to the structure of the FPGA occurs
during the compilation of a VI for the LabVIEW FPGA Module and is
completely abstracted from the end user. Hardware implementations of
LabVIEW’s functions are placed into the look-up tables of the FPGA and signals
are routed between them as appropriate. Additional logic is used to implement
LabVIEW’s dataflow.
55
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Compile Process and
Server
Convert
LV diagram to intermediate files
Send intermediate files to the compile server
Compiles
VIs for FPGA
Returns FPGA bitstream to LabVIEW
Bitstream is stored in VI
LabVIEW
environment is a client
Compile
Server
Can
disconnect from server and reconnect while
compiling
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
6
Once the FPGA VI is completed it needs to be compiled before it can be run on
the FPGA. The output of the compile process is a bitstream which is downloaded
to the FPGA.
During the compile process, LabVIEW converts the diagram into intermediate
VHDL files which are then passed to the Xilinx compile server. The compile
server then compiles the VHDL into the resulting bitstream. Once returned, the
bitstream is stored in the VI by the LabVIEW environment.
The compile server is started automatically on the same computer as the
development environment, however in the project options you can specify to use
the compile server on your local machine or the compile server on another
computer on the network. In order to use the compile server on another
networked computer, the compile server must be started manually before
connecting to it. This allows you to use a faster machine for compiling.
66
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Download
Occurs
Windows OS
LabVIEW FPGA Module
automatically after
a compile initiated
by the run button
FPGA VI
Target FPGA
Bit File Embedded
Massimo Lanzoni
Download
LabVIEW FPGA Module Tutorial
FPGA VI (actually
the bit file)
7
To test and run the FPGA VI the compiled bitstream must be downloaded to the
FPGA. The code is automatically downloaded when the Run button on the VI is
pressed.
77
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Interactive Mode
Interact
Windows OS
LabVIEW FPGA Module
with VI on
FPGA through Front
Panel
No Debugging
VI
is running in the
FPGA
Target FPGA
FPGA VI
(Front Panel)
Updates
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
FPGA VI
(running)
8
Running the FPGA VI while targeted to the FPGA, executes the VI in interactive
mode. In this mode the VI is executed on the FPGA while you see the front panel
of the VI on the development machine. Updates between the front panel and the
FPGA VI are handled automatically. This allows you to test the performance and
behavior of the VI, though you do not have access to most of the traditional
debugging tools like execution highlighting.
88
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Host PC Interactive
Mode
Interact
Windows OS
with FPGA
through host PC based
Front Panel
Allows you to do other
processing in Host VI
Target FPGA
VI
(Front Panel)
Updates
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
FPGA VI
(running)
9
Running the FPGA VI while targeted to the FPGA, executes the VI in interactive
mode. In this mode the VI is executed on the FPGA while you see the front panel
of the VI on the development machine. Updates between the front panel and the
FPGA VI are handled automatically. This allows you to test the performance and
behavior of the VI, though you do not have access to most of the traditional
debugging tools like execution highlighting.
99
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Windows Target Mode
Windows OS
LabVIEW FPGA Module
(targeted to Windows)
• Run FPGA VI on Windows
• Software Emulation
– No hardware timing
• Debugging possible
FPGA VI
Massimo Lanzoni
– Check logic before compile
LabVIEW FPGA Module Tutorial
10
You can target LabVIEW to Windows after building your FPGA VI. While target
to Windows you can run the VI and test its behavior. In this mode the I/O
functions do not access the FPGA hardware but return random data instead.
1010
LabVIEW FPGA Project
FPGA vi
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
11
11
Xilinx Spartan 3-E Dev Kit
Switches and LEDs
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
12
12
Xilinx Spartan 3-E Dev Kit
Encoder and push buttons
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
13
13
Xilinx Spartan 3-E Dev Kit
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
14
14
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Configuring FPGA I/O
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
15
In order to access I/O on the FPGA, you will need to first add I/O into your
project. You can do this from the project window by right clicking on the FPGA
target and selecting New>>FPGA I/O. This will launch the New FPGA I/O
dialog window where you can select I/O in the left hand tree and click the Add
button to add it to the project. Additionally, you can name you I/O by
clicking on the default name and typing in an alias.
1515
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Using FPGA I/O Nodes
Two ways to use FPGA I/O:
Drag and drop from LabVIEW Project
Drop empty I/O node on block diagram and select I/O by left
clicking
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
16
After adding FPGA I/O to the Project, using it is as simple as dragging and
dropping the I/O from the Project Window onto the block diagram. This will
automatically drop the appropriate FPGA I/O node onto the block diagram.
Another way to access I/O is to drop down an FPGA I/O node from the functions
palette. To select your I/O you can left click the part of the FPGA I/O node that
says “I/O name” and select your I/O. You can also add additional I/O to your
Project from the FPGA I/O node, simply left click as mentioned previously and
select Add New FPGA I/O this will launch the New FPGA I/O dialog.
1616
Introduction to LabVIEW FPGA for cRIO
5/17/2011
I/O Types
Digital
lines – writes/reads Boolean
value to/from digital line
ADC
and DAC – High level Vis to
read and write values; NI R-Series
hardware
Assigned
IO Pins of FPGA to
Spartan 3E components
Use
example projects as templates
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
17
There are three basic FPGA I/O types in LabVIEW FPGA hardware: digital
lines, digital ports, and analog I/O. Digital lines are basic digital I/O, these lines
are bi-directional on all R Series devices and some CompactRIO modules.
Additional information on digital enable and digital data functionality is
contained within the documentation of your specific device.
On the Spatan 3E board, all lines are digital. The IO Configuration dialog groups
the IO lines by on-board components. See example 2.1
The Digital Port is a group of eight digital lines. The ports use a U8 data type.
One bit is used for each line. The read and write functions will take data form all
lines in a given port.
The analog input node reads data form the specified line(NI Hardware). The
analog output node writes data to a given line. The values from the I/O lines are
binary values. The binary value is based on the resolution of the board. The
boards resolution is divided up into discretized values based on the range of the
board. All I/O values must be converted from a nominal value to a matching
binary value or vice versa to be correctly interpreted by the FPGA device.
1717
FPGA I/O node
FPGA I/O node
Will run on FPGA !
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
18
18
Xilinx Spartan 3-E Dev Kit
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
19
19
Introduction to LabVIEW FPGA for cRIO
5/17/2011
Creating Counters from Digital I/O
•Minimum input pulse width detectable depends on loop period
Example Finder: Toolkits and Modules >> FPGA >> CompactRIO/R
CompactRIO/R Series >> FPGA
Fundamentals >> Counters
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
20
The FPGA devices do not have counter hardware built into them. All counters
need to be programmed into the FPGA itself. The count register can be 32, 16,
or 8 bits. It depends of the type of integer selected for the counter’s indicator.
The loop period will also determine the minimum detectable pulse width. The
example above has the following specs:
1 ticks per iteration in a Single Cycle Timed Loop with default 40MHz clock
25 ns to guarantee a high or low read
50 ns period = 20 MHz signals.
It can read a signal at a maximum if 20 MHz. It is important to benchmark your
counter before using it in a final application. Shipping examples are located in
the Example Finder: Toolkits and Modules >> FPGA >> CompactRIO/R
Series >> FPGA Fundamentals >> Counters
2020
Timing Control Functions
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
21
The Timing & Dialog palette contains all of the FPGA timing structures. Timing control
functions are critical to your FPGA application. The timing structures include the Loop
Timer, Wait, and Tick Count VI’s.
The loop timer is used to control a For or While loop and set the iteration rate of the
loop. This is commonly used to control the acquisition or update rate of an analog or
digital I/O function.
The Wait function adds an explicit delay between two operations on the FPGA. This can
be used to control the pulse length of a digital output or add a trigger delay between
trigger signal and resulting operation.
The Tick Count function returns the current value of the FPGA clock and is used to
benchmark loop rates or create your own custom timers.
21
21
Configure Timing
Functions
Counter
Units
Ticks
µsec
msec
Size
of Internal Counter
32 Bit
16 Bit
8 Bit
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
22
Each timing control structure is an Express VI that has an appropriate Configure
dialog box that pops-up when you first place the VI on the block diagram or
when you right click on the VI and select Properties. The dialog box allows you
to configure the timing units and the size of the internal counter. The available
Counter Units include ticks; a single clock cycle, the length of which is
determined by the clock rate for which the VI is compiled; microseconds, and
milliseconds. The Size of Internal Counter determines the maximum time the
timer can track. The free running counter rolls over when the counter reaches the
maximum of Size of Internal Counter specified in the Configure dialog box.
To save space on the FPGA, you should use the smallest Size of Internal
Counter possible for the FPGA VI.
22
22
Loop Timer
Sequence
structure used so that
Loop Timer initializes loop timing
on first while loop iteration
If code execution time exceeds
the loop rate, then loop timing
adjusts for subsequent
iterations.
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
23
Use the loop timer function to control the acquisition rate of an analog input
operation. The sequence structure controls the flow of operations in the loop.
In the first iteration of the sequence, the loop timer will set a flag to mark the
loop start and then the next sequence will immediately begin execution. During
the second loop iteration, the loop timer will read the timestamp of the flag from
the previous loop iteration and hold for the wait time to expire.
If the execution of the code within the loop exceeds the loop rate defined by the
timing function, then the loop timing adjusts itself for subsequent iterations.
23
23
Loop Timer vs. Wait
Code
structure is the same
Loop Timer will only execute the first time it is
called
Wait will execute every iteration of the while loop
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
24
You can time your FPGA code using either the loop timer or the wait function. The
difference between these two functions is how they effect code execution.
When using the Loop Timer, during the first iteration the code will execute right away
while with the wait, it will wait however long the wait statement is defined.
For both cases, the options for choosing the timing units and the counter size are
available.
24
24
Tick Count Application Example:
Measuring Execution Time
Method 1
Method 2
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
25
As we mentioned before, the tick count function is commonly used in
benchmarking implementations. In these examples we present two possible
methods. Using the first method, we get the current value of the FPGA clock, in
the second sequence, we execute the code we want to measure, and in the third
sequence we get the current value of the FPGA clock again. Knowing the tick
count before and after executing the code, we can subtract both of them to find
the elapsed time.
Using the second benchmarking method, we use the same principle with the
exception that this method is used for getting the period. Here we run the code
multiple times and calculate the elapsed time every iteration.
25
25
Timing Using the SingleCycle Timed Loop
Execute
multiple
functions in a single
clock cycle
Loop executes at
compile clock speed
by default
Increases code speed
and efficiency
All code must execute
within one clock tick
Massimo Lanzoni
50 MHz Clock = Spartan 3E HW
40 MHz Clock = NI HW
LabVIEW FPGA Module Tutorial
26
The single-cycle timed loop structure allows you to execute multiple functions in
a single clock tick, 25 nsec for NI HW. Using the default clock, these loops run at
40 MHz. Traditional while loops in LabVIEW FPGA have 3 ticks of execution
overhead, and since every function must begin on a clock edge, the functions
inside the loop can add several ticks to the execution time of a loop iteration.
However, in the case of a single-cycle timed loop, each function is not required to
begin execution on a clock edge, but rather all functions execute as soon as their
inputs become valid, and all functions complete within a single clock cycle.
The code inside a single-cycle timed loop can directly interact with DIO, clock,
and trigger lines of the your I/O devices, as well as the onboard RAM. Since the
loop must execute in a single clock tick, some functions are not allowed. For
example, any function that waits such as a loop timer or I/O method node can not
be used inside the single-cycle timed loop. Analog I/O functions also cannot be
used, as they require longer than 25 nsec to execute. These operations can be
placed in another structure and triggered from operations inside a single-cycle
timed loop.
26
26
Multiple Clock Domains
• Derive different clock domains
based off 40 MHz
• Different Single-Cycle Timed
Loops can have different clocks
• I/O Supported:
• R Series Digital I/O
• cRIO-9401
• Used for:
– Generating clocks
– Local speed optimization
Massimo Lanzoni
LabVIEW FPGA Module Tutorial
27
You can now run Single-Cycle Timed Loops at different rates using multiple clock
domains. To implement multiple clock domains, you will multiply or divide the 40 MHz
clock by integers between 1 and 32 to derive specific clocks. To do this, go to the
Project, right click on the 40 MHz Onboard clock and select New FPGA Derived Clock.
A dialog will then open to allow you to select an appropriate clock.
Then you can configure a Single Cycle Timed Loop to use a derived clock by doubleclicking the configuration node of the Single Cycle Timed Loop and selecting your
clock. Using multiple clock domains is useful for when you need to optimize certain
sections of code. For instance, consider that you have an application that has
components that will only compile using the 40 MHz clock and you have a segment of
code that is performing a digital edge detection operation that you want the response time
to be a fast as possible. For this application, you might want to have the loop performing
the digital edge detection to run inside a Single Cycle Timed Loop running at 120 MHz.
27
27