Atmel’s Power Management Expertise Provides Optimum
Solutions for Portable Systems
Michele Casetta, Marketing Manager, Power Management Products, Atmel Rousset
Peter Bishop, Communications Manager, Atmel Rousset
Summary
Handheld devices such as mobile phones have exacting power management requirements.
Different elements require different supply voltages and have differing requirements in terms of
power efficiency, noise, power supply rejection ratio (PSRR) etc. Quiescent (standby) current
must be kept to an absolute minimum in order to give maximum battery autonomy. Power
management ICs comprise mostly analog elements, consisting principally of voltage regulators
(LDO and DC to DC), battery chargers and digital state machines for system control. They are
fabricated on a mixed analog/digital CMOS technology that achieves the best tradeoff between
performance and die size. Atmel has years of experience in developing the process technology
and intellectual property (IP) blocks that constitute a power management IC, and offers a range of
ASSPs and ASICs that satisfy the power management requirements of most handheld devices.
Atmel Corporation • 2325 Orchard Parkway • San Jose, CA 95131
TEL (408) 441-0311 • FAX (408) 487-2600 • Web Site: http://www.atmel.com
ATMEL’S POWER MANAGEMENT EXPERTISE PROVIDES OPTIMUM SOLUTIONS FOR PORTABLE SYSTEMS
Table of Contents
Background................................................................................................ 3
Process Technology for Power Management ........................................ 4
Atmel’s IP Blocks for Power Management .............................................. 5
Power Supply Rejection Ratio (PSRR)..................................................... 5
Reduction of Standby Current.................................................................. 6
Selection of regulator Output Transistors.......................................................................7
Selection of LDO or DC to DC Switching Regulators ....................................................8
Atmel’s AT73C202 Power Management IC .............................................. 9
Conclusion ............................................................................................... 12
Editors’ Notes .......................................................................................... 13
About Atmel Corporation ..............................................................................................13
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Background
Handheld electronic devices are today built around system-on-chip (SoC) or system-inpackage (SiP) technology. Their power supply requirements are exacting. While in
operation, they must be capable of high-performance data/signal processing, highbandwidth communications, high-resolution displays and high-quality audio output. This
must be achieved as economically as possible in terms of power consumption. Different
sub-systems require different supply voltages and draw different currents. While on
standby, the power consumption of the device should be reduced to the absolute minimum.
Transition from standby to operational mode (for example when a call is received on a
mobile phone) must be achieved as smoothly as possible, with no voltage or current spikes
that could disrupt the operation of the device. The objective is maximum battery autonomy
and prolonged battery life.
In designing a handheld device, power management is often a secondary consideration.
Discrete components are initially selected for power management to give flexibility in
development and debug. It is only when the design has become frozen that the question
arises of integrating these discrete components into a single IC for power management.
This saves space on the PCB, reduces the bill of materials and can achieve further power
savings by intelligent switching, and reduction of power consumption by the power
management system itself.
Figure 1. Power Management IC Concept
This article describes how Atmel responds to these challenges in the design of its power
management product range that consists of ASSPs and ASICs integrated from a set of
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pre-qualified IP (intellectual property) blocks. The general concept of an integrated Power
Management ASIC or ASSP is shown in Figure 1.
Process Technology for Power Management
Today, for reasons of cost and integration, CMOS is becoming the preferred technology for
power management. Power management ICs do not generally follow Moore’s law in
evolving to a new generation of process technology every one to two years. This is in order
to achieve the best (and most precisely modeled) analog performance, which is not
necessarily possible on the smallest geometries. In addition, the power management ICs
require 5V (or sometimes higher) interfaces for battery connections, as well as providing
3.3V, 2.5V and 1.8V supplies for internal blocks.
For the above reasons Atmel has selected a mature 0.35-micron CMOS technology for its
power management products. The IP blocks that make up the power management ICs
contain semi-custom cells that are developed and fully characterized using this reference
technology. This enables ASICs or ASSPs to be integrated rapidly from these IP building
blocks. A further advantage is that certain parameters such as supply voltage can be
modified by a single mask change. Wafers can be partially fabricated and held at the
required fabrication step awaiting the customization order from a customer. This enables
extremely short delivery times to be achieved.
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Atmel’s IP Blocks for Power Management
The basic cells of a power management unit are linear voltage regulators, known as low
dropout (LDO) regulators, and switching voltage regulators, known as DC to DC regulators.
As summarized in Table 1, their characteristics are different. This makes them suitable for
different applications. For example, an LDO regulator is ideal for supplying the RF section
of a mobile phone where low noise and high PSRR are essential.
Table 1.
Characteristics of LDO and DC to DC Voltage Regulators
Voltage
Regulator
Type
Characteri
stics
Output
Current
Output
Voltage
Noise
PSRR
Linear
(LDO)
High PSRR
5 mA to 180
mA
1.8V to
3.0V
Down to 35
µV RMS
Up to 65 dB
Step Up
Up to 400
mA fully
integrated
3.6V to 5V
(Step Up)
Step Down
Up to 1.5A
with
external
FET switch
0.9V to
1.9V (Step
Down)
Low Noise
Low
Quiescent
Current
Low Drop
Out
Switching
(DC to DC)
Step
Up/Down
The basic advantage of DC to DC regulators is their higher efficiency. In a typical case
where a battery voltage of 3.6V is transformed into a core supply voltage of 1.8V, a DC to
DC regulator can reach 90% efficiency whereas an LDO regulator achieves 50% efficiency
at full load. However, the quiescent (standby) current of a DC to DC regulator can be 100
times that of an LDO regulator. A way of obtaining the best performance from a
combination of the two is described below.
Power Supply Rejection Ratio (PSRR)
The PSRR measures the degree of immunization against voltage fluctuations achieved by
a regulator. An example of its importance is in the case of a GSM phone when the antenna
switch activates the RF power amplifier (PA). This causes a current peak of up to 2A on
the battery, with a consequent spike on the battery voltage. The voltage regulator must
filter or at least attenuate this spike.
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As shown in Figure 2, Atmel has achieved PSRR figures that are more than adequate for
mobile phone systems.
Figure 2. Power Supply Rejection Ratio as Functions of Frequency and Battery Voltage
From Figure 2 it can be seen that, for example, if a noise signal occurs at 1 kHz when the
battery voltage is at 3V, the noise will be attenuated by 70 dB (divided by more than 3000)
at the output of the regulator. Consequently, a 2V spike on the battery is attenuated to less
than 1 mV, which is low enough to avoid any risk of malfunction by a device supplied by
the regulator.
Reduction of Standby Current
One of the principal objectives of a power management system is to reduce the standby
(quiescent) current of the device to a minimum. Two techniques for achieving this are
described in the following sections.
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Selection of Regulator Output Transistors
The first approach to reducing standby current is to decrease the standby current inside
the regulators themselves. Atmel achieves this by implementing a dual mode architecture
where two output transistors are used in parallel as switches in the regulation loop. Figure
3 illustrates this architecture.
Figure 3. Parallel Output Transistors in Voltage Regulator
In Figure 3, the left-hand output transistor is sized large enough for the required output
current under full load, for example 100 mA. In order to achieve a sufficient margin of
stability, the current sensing block uses a bias cell where the current consumption is linked
to the required output current. The higher the output current, the higher the bias current
needed to stabilize the loop.
The right-hand output transistor delivers a very small output current, typically less than 1
mA, sufficient only to maintain the output voltage with enough current to cover the leakage
current of the supplied device. This requires a much smaller bias current and consequently
a smaller standby current inside the regulator.
Switching between the two modes is by a low power (LP) selector signal originating from
the supplied device, which switches between operational and standby modes under control
of its hardware and software. A typical example is a mobile phone in standby mode while it
is listening for a call and in operational made when it is receiving or transmitting a call.
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Selection of LDO or DC to DC Switching Regulators
Figure 4. Switching Circuit for LDO or DC to DC Regulator Selection
As explained above, LDO and DC to DC regulators have different characteristics making
LDO regulators more suited to low-current supply situations and DC to DC regulators more
suited to high-current situations. Consequently a second technique for limiting standby
current is to switch between an LDO regulator and a DC to DC regulator in the supply for
the same device. This is achieved by a circuit as shown in Figure 4. A capacitor is inserted
to smooth the transition between the two supply modes.
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Atmel’s AT73C202 Power Management IC
Figure 5. Atmel’s AT73C202 Power Management Controller IC for Mobile Phones
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Atmel’s AT73C202 Power Management Controller IC (Figure 5) implements the design
principles described in the previous sections. It is a low-cost, ultra low-power, power and
battery management IC designed to interface directly with state-of-the-art cellular phones,
for example with 2.5G GSM phones. It includes all required power supplies tailored to be
fully compatible with the sub-systems of recent mobile phone chipsets, including the RF,
analog and digital (DSP, microcontroller, memories) sections.
In addition, the AT73C202 includes a low-cost battery charger, using a simple external
PNP transistor for Li-Ion or Li-Polymer batteries. The safe battery operating conditions are
fully under hardware control during the start-up procedure (when the phone is turned on or
a charger is plugged in). The battery pre-charge and fast charge phases are also
integrated and self-operated by the AT73C202. On completion the end-of-charge
procedure is transferred to the baseband software.
The AT73C202 also includes a back-up battery charger and an ultra low-power regulator
dedicated to the baseband real-time clock (RTC) supply during sleep mode.
The hardwired start-up mechanism (power management controller state machine) ensures
safe telephone operation during the wake-up and shut-down procedures, and during the
multiple real-life operating conditions of a mobile phone (such as charger plug-in, plug-out,
battery plug-in, plug-out, low or dead battery, etc.).
The AT73C202 also provides all the interfaces currently required in cellular phones: buzzer
driver, vibrator driver, battery monitoring, charging LED driver and a SIM level shifter
interface for GSM (including a SIM 1.8V/2.8V voltage regulator compliant with ETSI
GSM11.12 & 11.18).
Figure 6. AT73C202 Die
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The AT73C202 is implemented on an extremely compact die, with most of the area
occupied by analog elements. See Figure 6. It is packaged in an ultra-thin 5mm x 5mm 49ball FBGA package, as shown in Figure 7.
Figure 7. AT73C202 FBGA Packaging
A variant of the AT73C202 can provide two levels of voltage programming for the
baseband core (1.8V and 2.5V) and for the analog cells (2.5V and 2.8V) in order to
accommodate recent sub-micron technologies (e.g. 0.25µm, 0.18µm). A low-power mode
is available in order to minimize the standby current consumption during the quiet
transmission periods.
An evaluation board (Figure 8) is available for the AT73C202. It permits complete device
characterization and measurements including noise, quiescent current, PSRR and load/line
transient regulation. It can also be used as the starting point for developing applications
based on the AT73C202.
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Figure 8. AT73C202 Evaluation Board. The AT73C202 is the small IC in the center.
Conclusion
Atmel’s power management products are the result of the judicious choice of a true mixed
analog/digital CMOS process technology, a design/characterization flow that is adapted for
modular IP block development, integration and re-use, coupled with an awareness of the
importance of a cost-effective end product. The outcome is a family of ASSPs that can
rapidly be transformed into ASICs to satisfy the power management requirements for a
wide range of high-performance portable devices such as mobile phones.
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Editor's Notes
About Atmel Corporation
Founded in 1984, Atmel Corporation is headquartered in San Jose, California with
manufacturing facilities in North America and Europe. Atmel designs, manufactures and
markets worldwide, advanced logic, mixed-signal, nonvolatile memory and RF
semiconductors. Atmel is also a leading provider of system-level integration semiconductor
solutions using CMOS, BiCMOS, SiGe, and high-voltage BCDMOS process technologies.
Further information can be obtained from Atmel’s Web site at www.atmel.com.
Contact: Peter Bishop, Communications Manager,
Tel: (+33) (0)4 42 53 61 50, e-mail: pbishop@atmel.com
Atmel
Rousset,
France,
®
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