CIC Xilinx FPGA training
July 2004
Jan.
2004
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After completing this module, you will be
able to:
• Describe how to enter symbols, wires, and
buses
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Beginning a Schematic
Symbols, Wires, and Buses
I/O Markers
Other Useful Commands
Synthesis Considerations
Summary
Lab 2: ECS
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• What is ECS?
– ECS stands for Engineering Capture System
– ECS is the schematic entry method for
Foundation ISE series software
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• Wire - Single lines representing electrical
connections
• Net - Set of interconnected pins and wires
• Bus - Wire that represents more than one signal
• Bus Tap - Used to define connections between
nets and a bus
• I/O Marker - Identifies a net name as an input,
output, or bidirectional signal. This establishes
net polarity (direction of signal flow), and it
indicates that the net is externally accessible
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• Introduction
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Symbols, Wires, and Buses
I/O Markers
Other Useful Commands
Synthesis Considerations
Summary
Lab 3: ECS
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• In an opened project,
create a new
schematic source:
– Project Æ New
Source
– Source window
ÆCreate New Source
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• Project Navigator
will open the
ECS program to
begin a design
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•View Æ Toolbars
View
File
Widow
Edit
Tools
Check
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• Introduction
• Beginning a Schematic
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I/O Markers
Other Useful Commands
Synthesis Considerations
Summary
Lab 3: ECS
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Add Æ Symbol
All components are listed in
the right-side of the ECS GUI
Components are divided into
categories
Exact symbols located
in Symbol box
Symbol Name Filter
for easier search
Orientation
– Rotate 0, 90, 180, 270
– Mirror and rotate 0, 90, 180,
270
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• Draw wires through the
Add menu
– Drawing Toolbar or
– Add Æ Wire
• Place your cursor where
the wire should begin
• Hold left mouse button
down
• Drag cursor to where the
wire should end
• Release left mouse
button
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To name nets use
Enter the net name in the
Options tab
Bring cursor into the
schematic
– The name will appear
with the cursor
Click on net, and the
name will append to the
end of the net
Options: Keep Name,
Decrement/Increment
Name, Clear Name
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Introduction
Beginning a Schematic
Symbols, Wires, and Buses
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Other Useful Commands
Synthesis Considerations
Summary
Lab 3: ECS
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I/O Markers replace the functionality of
IPAD/OPAD in other schematic tools
Buffers are automatically inferred for I/Os
(except for clocks)
You do not need to use IBUFs or OBUFs
in schematics unless you have a specific
IO standard you wish to use
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Select Add I/O Marker mode:
Determine the direction of the I/O
Marker in the Options window
With the direction selected, add I/O
markers to the design using one of
the following techniques:
– Click the red box at the end of the net (if
the net is not named)
– Click the point between the net name
and the net
– Draw a bounding box around one or
more net names, by click-dragging
around them
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Š Method 1: Select a
point at the end of
the net or a point
between the net
name and the net
Š Method 2: Draw a
bounding box
around one or more
red boxes at the end
of the nets (if the
nets have not been
named) or the net
names
mysig
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Introduction
Beginning a Schematic
Symbols, Wires, and Buses
I/O Markers
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Synthesis Considerations
Summary
Lab 3: ECS
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Drag and move objects
using the pointer
To move objects with net
connections (nets will
autoroute), use “Keep
the connections to other
objects” in the Options
tab
To move only the
selected object, select
“Break the connections to
other objects”
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• Check Schematic
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Checks the schematic connectivity
Dialog box will appear indicating errors
Navigate to schematic by clicking on each line
Access using
• Consistency Check button in toolbar
• DRC Æ Consistency Check
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or...
• Mirror button
–
“Flips” object in the schematic
– Located in the Drawing tool bar
• Rotate button
– rotates the selected object 90
degrees counterclockwise.
– Located in the Drawing tool bar
• Query
– supplies information about an
object you select.
• ESC button
– Release, or get out of, current
command
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Introduction
Beginning a Schematic
Symbols, Wires, and Buses
I/O Markers
Other Useful Commands
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Summary
Lab 2: ECS
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• HDL keywords cannot be used on schematics
• BUFG instantiations incorrectly handled in
Express
– Workarounds
• Use an IBUF -- not a BUFG -- on the input, then use the
constraints editor to change it to a BUFG
• Use an IBUF and a BUFG on the input, then lock the IBUF to
a global clock pin
• Unified components require all input pins to be
connected
– Tie unused pins, both inputs and outputs, to GND or
VCC
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Introduction
Beginning a Schematic
Symbols, Wires, and Buses
I/O Markers
Other Useful Commands
Synthesis Considerations
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Lab 3: ECS
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• ECS is the Engineering Capture System,
used for schematic designs in the ISE
software
• The main design components can be
accessed through the Drawing Toolbox
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Introduction
Beginning a Schematic
Symbols, Wires, and Buses
I/O Markers
Other Useful Commands
Synthesis Considerations
Summary
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This lab will takes you 30 ~ 40 minutes
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