ISE 4 Tutorial – Schematic-Based Design
Gang Zheng
Department of Electrical and Computer Engineering
University of Colorado at Colorado Springs
gzheng@uccs.edu
This tutorial is made for students who are unfamiliar with the Xilinx Integrated Software
Environment (ISE) FPGA synthesis tool. The primary objective is to enable students make a
quick start on the ISE schematic-based design. It introduces the ISE design environment and
guides through the schematic design flow. By following this tutorial, students are supposed to be
able to draw, synthesize and download the designed circuitry (schematics) onto the Digilab XLA
board.
This tutorial is to prepare students for further in-depth investigation into the ISE tool set.
Additional documentation about Xilinx ISE 4 can be found at
http://www.xilinx.com/support/techsup/tutorials/tutorials4.htm. Also see the Xilinx University
Programs located at http://xup.msu.edu.
1. GET STARTED
One design example is used through this tutorial. It is actually one of experiments for ECE 2420
Logic Circuit Lab, in University of Colorado at Colorado Springs. The design requirement states:
Design a 2-bit counter with the following sequence: 00 Æ 01 Æ 10 Æ 11 Æ 00 ……
Use positive edge triggered D flip-flops that have active low clear and active low set
controls.
Without going through every step, the final logic expressions of the D flip-flops are given as:
D1 = Q1 ⊕ Q0
D0 = Q0’
The circuitry is derived as:
Figure 1. 2-bit counter schematic
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Now we are ready to jump into the ISE environment. The ISE software is called Project
Navigator. Invoke the Xilinx ISE tool by double click on the icon of Project Navigator located
on the desktop.
Figure 2. Xilinx ISE desktop icon.
This will bring you to the Project Navigator environment where you are going to work on your
project. Figure 3 shows the activated window.
Figure 3. Project Navigator wake-up window
2. CREATE A NEW PROJECT
A new project needs to be created for your design. To do that, click on File on the tool bar, and
select New Project in the pull-down menu, as shown in Figure 4.
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Figure 4. Create a new project
The New Project dialog window is going to pop up on the screen, which is shown in Figure 5.
First, in the Project Location dialog box, select the directory where you want your project to be
saved. You may change directory by click “…” button. Then specify the name of your project in
the Project Name box. In our example, we call it “two_bit_counter”.
Figure 5. New Project dialog window
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The contents of the Project Device Options are very specific to the device you are going to use in
the lab. So you need to be very careful. The Device Family MUST be SpartanXL. The Device
MUST be xcs10xl-4pc84. And the Design Flow may be either FPGA Express VHDL or FPGA
Express Verilog.
If you have done above steps successfully, you’ve set up the frame for your new project. Now
you need something to fill up this frame. You may build some new source file or add some
sources you’ve built before. On the tool bar, click Project, then select New Source in the pulldown menu if you want to build a new source file for your project, as shown in Figure 6.
Figure 6. Add new source
ISE tool supports Schematic design entry, and Hardware Description Language (HDL) design
entries as well. We will focus on the Schematic-based design entry in our tutorial, while ignoring
the features about HDL design flows.
A new source dialog window will be brought, as shown in Figure 7. In the big box on the left
side, select Schematic, which allows you to create a schematic as the source file. In the File
Name box, specify a name for your schematic file. The file will be automatically saved in the
directory you created before. Make sure the Add to project box is checked before you click the
Next button. Clicking on Next brings you to the next window called New Source Information,
shown in Figure 8. Simply click on the Finish button, and you will be pushed into the Xilinx
ECS schematic editor. Now you are ready for drawing the logic circuit you’ve designed.
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Figure 7. New source dialog window
Figure 8. New source information
3. DRAW A SCHEMATIC
Figure 9 shows the Xilinx ECS schematic editor window. In the white dotted area, you are going
to draw the schematic shown in Figure 1.
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Figure 9. Xilinx ECS schematic editor
3.1 Find and place logic parts
From Figure 1 we know the elements we are going to use for building the circuit include two D
flip-flops and an XOR gate. Select the right elements from the boxes on the right hand side, and
place them on the dotted sheet one by one. Make sure the parts you selected have all the
functionalities you need, because there may be more than one element available that have the
same basic functionalities but different control logics. For instance, element fd and fdrs both are
D flip-flops. But the fdrs is the D flip-flop with active high set and reset control signals, while fd
is not. By the way, the set and reset actions of the D flip-flop fdrs are triggered by active edge of
clock signal, or in other words, synchronous.
In the Flip_Flop category, we can find the fdrs which is closest to the one we need. In the Logic
category, we can find all kinds of gates including the XOR gate that is the one we need. You
may try to take a look at what are included in other categories and place them on the sheet with
no harm to get used to the tool. You can simply remove the ones you don’t want anymore by
those normal ways you are supposed to know.
After checking all of those D flip-flop options, you can find out there isn’t any one which has the
negation of the output Q that is also one item you need in your circuit. This results in an inverter
which is denoted as inv and can be found in Logic category too. Recall that you are required to
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use the D flip-flop with active low set and reset controls, instead of active highs. So two
additional inverters are needed to negate the set and reset signals. Figure 10 shows the window
with selected parts placed on the sheet.
Figure 10. Xilinx ECS with parts placed
3.2 Add wires
Hook up the parts by adding wires. Click on Add on the tool bar, then Wire in the pull-down
menu. By single left clicking on one end of a desired wire then single left clicking on the other
end, a wire is to be draw automatically. You may change the layout of the wire by click and drag.
You may also remove a wire by normal ways you are supposed to know. Figure 11 shows the
schematic with parts hooked up by wires.
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Figure 11. Schematic with wire added
3.3 Add I/O buffers
The inputs and outputs may not be connected to the board directly. They have to be separated
from the board by I/O buffers. To add I/O buffers, select the IO category, and place ibuf before
the inputs, one for each port, and obuf after the outputs, again one for each port. Notice that the
inputs and outputs of buffers are extended by wires for next step.
You should pay special attention to the clock signal because it’s not regular input. Instead of
using an ibuf, a buffer called bufg needs to be placed between the clock input of the flip-flops
and the clock source. Bufg, an architecture-independent global buffer, distributes high fan-out
clock signals throughout the circuitry. The input of the buffer should be the clock source.
Depending upon the design, the clock source can be an internal clock, output of an internal logic,
or an output of an ibuf. Since manual clock is going to be used in this example, an ibuf is placed
before the bufg. Bufg can be found in the Buffer category. Figure 12 shows the schematic with
buffers.
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Figure 12. Schematic with I/O buffers
3.4 Name the I/O ports
Those I/O ports are to be connected to the resources of the Digilab board. Wiring the I/O ports to
the board will be stated in next section. So we are not going to worry about them at this time. But
we do need to specify the I/O names for the I/O ports so that they can be recognized by the tool
and by the designers sometime later.
To name those I/O ports, click Add on the tool bar, then Net Name, a bar with three boxes is
going to be added onto the header of the window, as shown in following figure.
Figure 13. Adding net name
In the middle box of the three, type the name you would like to call your input/output ports, for
example, “clock” for the clock input of the flip-flops, Q1 for the output of one of the D flipflops. Then move the mouse to the appropriate port and left click on it. You need to repeat this
for all the I/O ports and name them one after another. Part of the schematic with named ports are
shown in Figure 14.
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Figure 14. Name the I/O ports
3.5 Make I/O pads
Click on Add on the tool bar, then click on I/O Maker to activate the I/O Maker tool bar on the
header, as shown in Figure 15. Click on input on the I/O Maker tool bar, and place the pad on
each input port by left click on those ports. Select output pad and do the same for all of the
output ports.
Figure 15. I/O Maker tool bar
The step of drawing the circuit has been finished. You may save the file and close the editor.
Figure 16 and Figure 17 show part of the schematic with I/O pad added and the whole circuitry,
respectively.
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Figure 16. Schematic with I/O pads
Figure 17. Final looking of the schematic
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4. SYNTHESIZE THE SCHEMATIC
Notice that back into the Project Navigator environment, in the Sources in Project window on
left side, the file you just created has been included in the design tree. Before you synthesize the
circuitry, you need to map the I/O pads onto the resources of the board.
4.1 Edit User Constraints File (.ucf)
Recall that the circuitry we have created will be downloaded onto an FPGA chip. But be aware
that there are 84 pins on the chip. How does Xilinx ISE know which pin is for which I/O port?
This can be done by modifying the .ucf file.
Below the Sources in Project window there is a window called Processes for Current Source.
The window is full of commands or say processes by which we are going to eventually get the
synthesized circuit. In that window, click on the plus sign in front of Design Entry Utilities, then
click on the plus sign in front of User Constraints. This exposes two processes, as shown in
Figure 18.
Figure 18. Processes for Current Source
Double click on the Edit Implementation Constraints (Constraints Editor). This action brings
you to the Xilinx Constraints Editor window as shown in Figure 19. Find the Ports tab, in the
Location column of the table, assign pin numbers to the corresponding I/O ports of the circuit. In
this example, clock is connected to P19 which is the switch 8 (SW1). Q1 and Q0 are connected
to P69 and P68 which are LED 1 (LD1) and LED 2 (LD2), respectively. Reset and set are
connected to P27 and P28 which are switch 2 (SW2) and switch 1 (SW1), respectively. Refer to
“Introduction to The Digilab XLA Board” for more information about the definition of the pins.
The pin assignments are not necessarily like these. Of course, you may use other buttons,
switches and LEDs too.
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Figure 19. Xilinx Constraints Editor Window
Save the modification to the .ucf file and close the Xinlinx Constraints Editor window. A Notice
window could then pop out and say you need to reset the implement design process so that your
UCF file changes can be read, which is shown in Figure 20. Simply click on the Reset button.
Figure 20. Reset notice
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4.2 Synthesize the circuit
Go back to the Xilinx Project Navigator environment. In the Processes for Current Source
window, double click on the Implement Design process. Xilinx ISE allows user to jump into any
step of process while having those steps ahead of the current process executed automatically. So
this action actually activates all of the previous and present synthesis steps.
A check mark in the Processes for Current Source denotes a process that was run successfully,
as shown in Figure 21. An exclamation mark indicates that when running the process a warning
was resulted. A cross mark means that you’ve got some error(s). Detail information about the
errors can be obtained in the console window on the bottom.
Figure 21. Step through the synthesis process
If the design can survive after going through the processes, you are now ready to move on to the
next step. Otherwise, you have to go back to the source file and get the problem fixed. Some
successful information can be viewed in the console window on the bottom of the Project
Navigator window. Then double click on the Generate Programming File process, as shown in
Figure 22. You can always expect a check mark for this step because this step is always run
based on a correct and synthesized design. If you do get a check mark, go get your Digilab board
set up.
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Figure 22. Generate programming file
4.3 Download file onto the board
Connect the board and the host computer by parallel cable. Make sure the switch 9 (SW9) on the
board is switched to PROG position. Expand the Generate Programming File process by click
the plus sign ahead of it. Double click on Configure Device (iMPACT). Following window is to
pop out.
Figure 23. Download the design on to FPGA
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in the center of the window, then click on Program, the .bit file
Right click on the chip
will be downloaded onto to FPGA chip on the board.
You are all done. Have fun in playing your design!
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