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Input/Output Devices
INPUT/OUTPUT HANDLING
☞ Input and output devices provide a means for
information storage and for people (environment) to
interact with the computer.
• Secondary memory: provides the long-term
storage of large amounts of data and program
(diskette, hard-disk, magnetic tape, CD-ROM).
1. Input/Output Devices and System Buses
2. Bus Arbitration
• Sensors and actuators: used for direct
interaction with the environment.
3. Bus Timing
• Human interface: keyboard, monitor, mouse,
printer.
4. I/O Modules
5. I/O Address Decoding
• Communication devices: modem, network
controller.
6. Programmed and Interrupt-driven I/O
7. Direct Memory Access
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Input/Output Devices (cont’d)
Video
controller
Keyboard
controller
Diskette
controller
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Input/Output Devices (cont’d)
Hard disk
controller
☞ The bus is used
- by I/O controllers for communication to/from
CPU or memory
- by the CPU for fetching or storing instruction
and data from/to memory.
Conflicts between CPU and I/O controllers
Bus
CPU
Main
Memory
☞ Controller: controls its I/O device and handles bus
access for it.
• Hard disk controller receives, for example, a
read request from the CPU ⇒ gives
corresponding commands to the device in
order to execute the request, collects data and
organises the incoming bit stream into units to
be sent on the bus.
• A controller has to interact with the bus,
according to a certain protocol, in order to
transmit and/or receive.
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☞ In case of conflicts a device (chip) called bus arbiter
decides on access.
• In general, I/O devices are given preference over
the CPU; usually devices cannot be stopped ⇒
forcing them to wait would result in loss data.
- When no I/O is in progress, the CPU has all bus
cycles for itself to reference memory.
- When some I/O device is also running and requests the bus, it gets it ⇒ cycle stealing
slows down the computer.
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Input/Output Devices (cont’d)
Memory
bus
Main
Memory
PCI
bridge
CPU
Input/Output Devices (cont’d)
☞ Different buses are connected through adequate
bridges (bridges also perform buffering of
information);
SCSI
bus
SCSI
controller
Video
controller
Network
controller
PCI Bus
Printer
controller
Sound
card
ISA
bridge
Modem
☞ Advantages of architectures with multiple buses:
• avoids bus conflicts;
• insulates CPU-to-memory traffic from I/O traffic;
• allows the system to support a variety of I/O
devices tailored for different bus standards.
ISA Bus
•
•
•
•
ISA (Industry Standard Architecture) bus:
relatively slow.
PCI (Peripheral Component Interconnect) bus:
faster bus.
CPU and memory are connected through a
dedicated high speed interconnection.
SCSI (Small Computer System Interface) is a hard
disk interface; it is also a bus standard for high
transfer rate peripherals.
Up to seven devices can be attached to a SCSI
bus; typically: hard discs, CD-ROMs, scanners.
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External Interface of the CPU Chip
Addressing
Data
Bus
control
m
Bus
arbitration
n
Micro
Processor
Coprocessor
Interrupts
Φ +5V
Clock Power
signal
☞ The CPU pins can be divided into: address pins, data
pins, and control pins.
•
•
External Interface of the CPU Chip (cont’d)
•
control pins:
- bus control: the CPU uses these pins to control the
rest of the system and tell it what it wants to do;
control signals are propagated over the system
bus.
- interrupt pins: on these pins the CPU gets signals from I/O modules; they usually indicate
that an I/O operation has been completed;
- bus arbitration: are needed to regulate traffic on
the system bus, to prevent devices from trying
to use it at the same time;
- coprocessor: facilitate communication with coprocessors, such as floating point chips, graphic chips, etc.
address pins: the address is output to the system
bus on these pins, for read/write operations.
- with m address pins, 2m locations can be
addresses.
data pins: data bits are output/received to/from the
system bus on these pins.
- with n data pins an n-bit word can be read written
in a single operation.
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System Buses
System Buses (cont’d)
Memory
bus
CPU
Main
Memory
PCI
bridge
SCSI
bus
SCSI
controller
Video
controller
Network
controller
PCI Bus
Sound
card
Printer
controller
ISA
bridge
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☞ A system bus typically consists of 50-100 separate
lines. They can be classified into three functional
groups:
1. Data lines: provide a path for moving data between system components.
The width of the data bus: 8, 16, 32, 64 lines.
2. Address lines: are used to designate the
source or destination of data.
The width of the address bus determines the
maximum memory size which can be addressed.
3. Control lines: are used to control bus access,
synchronize operations, and to propagate
commands throughout the system.
Modem
ISA Bus
☞ A bus is a common electrical pathway between
multiple devices. One or several buses can be used
in a computer system to interconnect CPU, memory,
and devices.
• in addition to such "system buses", there are
buses also inside the CPU (internal buses).
☞ System buses differ in the number and organization
of lines, arbitration, timing, and specific bus operations.
In order to connect a device to a bus, the device
controller must fit to the respective bus features.
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☞ In order to avoid vary large buses ⇒ multiplexed
bus. Instead of having separate address and data
lines, we can have 32 lines for address and data
together.
At the start of the bus operation first the lines are
used for address; later on, the same lines are used
for data.
Bus width can be reduced, but the system becomes
slower (for a write, address and data can not be put
on the lines simultaneously).
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Bus Arbitration
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Bus Arbitration (cont’d)
What happens if two or more devices want to act
simultaneously as masters?
☞ Devices connected to a bus can be of two kinds:
1. Master: is active and can initiate a bus transfer.
2. Slave: is passive and waits for requests.
☞ Some devices can act both as master and as slave,
depending on the circumstances:
• CPU is typically a master.
A coprocessor, however, can initiate a transfer
of a parameter from the CPU ⇒ CPU acts like
a slave.
• An I/O device usually acts like a slave in
interaction with the CPU.
Several devices can perform direct access to
the memory, in which case they access the bus
like a master.
• The memory acts only like a slave.
Since only one unit at a time can transmit over the bus,
arbitration is needed.
☞ Arbitration mechanisms:
• Centralized arbitration: there is a single device,
the bus arbiter, that determines who goes next.
• Decentralized (distributed) arbitration: no
arbiter is needed.
For example:
- there are as many request lines on the bus
as devices; each device monitors each
request line ⇒ after each bus cycle each
device knows if he is the highest priority
device which requested the bus ⇒ if yes, it
takes it.
☞ With decentralized arbitration, no arbiter but more
bus lines are needed.
☞ Examples:
• PCI and ISA buses use a centralized arbitration
scheme.
• SCSI buses use a decentralized scheme.
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Bus Timing
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Synchronous Timing
Bus cycle
Clock
☞ Timing refers to the way in which events are
coordinated on the bus:
Start
1. Synchronous timing: the occurrence of events
on the bus is determined by a clock.
Read
Address
Lines
2. Asynchronous timing: the occurrence of one
event on a bus follows and depends on the occurrence of a previous event.
Data
Lines
Acknowledge
☞ Examples:
• PCI and ISA buses use synchronous timing.
• SCSI buses use asynchronous timing.
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•
The bus includes a clock line; all devices on the bus
can read the clock line.
• All events on the bus start at the beginning of a
clock cycle.
☞ A bus sequence for a synchronous memory read.
- The CPU (master) issues a start signal to mark
the presence of address and control information
on the bus: the read signal is issued on the respective control line, and the memory address
is placed on the address lines.
- After a delay of two bus cycles, the memory
(slave) places the data on the data lines and issues an acknowledge signal on the respective
control line.
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Asynchronous Timing
Synchronous Timing (cont’d)
•
•
Advantages with synchronous timing: simple to
implement and test.
Disadvantages with synchronous timing: not
flexible.
- Execution times have to be multiples of clock
cycles (if an operation needs 3.1 clock cycles, it
will take 4 cycles).
- Bus frequency has to be adapted to slower devices ⇒ one cannot take full advantage of the
faster ones.
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•
There is no clock line on the bus.
•
Each event is caused by a prior event, not by the
clock pulse. The master will wait exactly as much
as is needed for the slave to finish.
•
If a master has to wait long for a certain slow slave,
this does not influence how much it will have to wait
for another faster slave in a following operation.
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I/O Modules
Asynchronous Timing (cont’d)
☞ I/O modules are usually performing the task of the I/O
controller. Very often they are produced as standard
I/O chips.
MSYN
Read
☞ An I/O module has an interface to the device it
controls, and another one to the system bus (or
directly to the CPU and/or memory).
Address
Lines
Data
Lines
SSYN
☞ A bus sequence for an asynchronous memory read.
- After the CPU (master) has asserted the address lines and issued the read signal, it waits
until this lines are stable and then issues the
MSYN signal (Master SYNchronization).
- When the memory (slave) sees the MSYN, it
performs the work as fast as possible and puts
the data values on the data lines and then asserts
the SSYN (Slave SYNchronization) signal.
- When the master has noticed the SSYN, it
knows that data is on the lines and latches it, after which it negates the address lines, MSYN,
and read.
- When the slave sees the negation of MSYN, it
knows that data has been read, and negates
data lines and SSYN.
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☞ Major functions of an I/O module:
• control and timing of the operations;
• bus (possibly direct CPU) communication;
• device communication;
• data buffering;
• error detection.
☞ A possible sequence of steps, for a data transfer
between a device and the CPU (over the bus):
1. The CPU interrogates (over the bus) the I/O
module, over the status of the device.
2. The I/O module returns (over the bus) the
device status.
3. If the device is OK and ready, the CPU
requests the transfer of data by means of a
command to the I/O module.
4. The I/O module issues appropriate commands
to the device and obtains a unit of data.
5. The data is transmitted (over the bus) to the CPU.
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I/O Address Decoding
I/O Modules (cont’d)
☞ Data buffering is essential for I/O modules; it allows
transfer to/from memory to be performed at memory
speed instead of the much lower speed of I/O
devices.
Problem: How is the external device selected for an I/O
operation?
☞ Structure of an I/O module
Device
interface
System bus
interface
Data buffer
Data lines
Interface
Device 1
Data
Status
Control
Interface
Device n
Data
Status
Control
Status/control reg.
Address lines
Control lines
internal
control
logic
There are two possible ways:
1. Memory mapped I/O
2. Isolated I/O
☞ I/O modules hide several details of handling a device
from the CPU ⇒ the CPU can view the device in
terms of simpler operations:
• Sophisticated modules, I/O channels, take over
most of the details and present a high-level
interface to the CPU; they are used on
mainframes and some minicomputers.
• Simpler modules, device controllers, are used
on PC’s, workstations.
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Memory-mapped I/O
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Memory-mapped I/O (cont’d)
Data lines
•
Address lines
Control
lines
read
write
Addr
dec
Addr
dec
Addr
dec
Memory
Memory
Memory
mod. 1
mod. 2
mod. 3
Addresses Addresses Addresses
X1+1 .. X2 X2+1 .. X3
0 .. X1
Addr
dec
device 1
A single read and a single write line are needed on
the bus.
The particular address is deciding if it is going to be
a memory read/write or an input/output on a certain
device.
Addr
dec
Advantage
• Easy to program: memory reference instructions
are used for I/O programming, instead of a quite
reduced set of difficult to use specific I/O
instructions (see Fö 5).
device 2
Addresses Addresses
X3+1,X3+2 X3+3,X3+4
Disadvantage
• Only a part of the address space is available for
memory. Another part is dedicated for device
addressing.
☞ There is a single address space for memory
locations and I/O devices.
The CPU treats the status and data registers of I/O
modules as memory locations ⇒ the same machine
instructions are used to access both memory and I/O
devices.
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Isolated I/O
Isolated I/O (cont’d)
Data lines
Address lines
Control
lines
mem.
read
mem.
write
I/O
read
I/O
write
Addr
dec
Addr
dec
Addr
dec
Memory
Memory
Memory
mod. 1
mod. 2
mod. 3
Addresses Addresses Addresses
X1+1 .. X2 X2+1 .. X3
0 .. X1
Addr
dec
device 1
Addr
dec
device 2
Addresses Addresses
2, 3
0, 1
☞ The CPU treates memory access and I/O differently.
I/O operations are performed by specific I/O
instructions.
• When the CPU is executing a memory access
instruction, the memory read/write line is
asserted.
• When an I/O instruction is executed, the I/O
read/write line is asserted.
Depending on which bus line is asserted, the
address on the address lines is interpreted as a
memory or as a device address.
☞ The address space for I/O is isolated from that for
memory ⇒ the full range of addresses is available for
both memory and device addressing.
☞ There are separate I/O-read, I/O-write and memoryread, memory-write command lines on the bus.
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Input/Output Processing
Programmed I/O
•
Three techniques are possible for transferring data to/from
I/O devices:
1. Programmed I/O
The CPU executes a sequence of instructions,
being in direct control of the I/O operations (sensing
device status, read/write commands, etc.). When
the CPU issues a command to the I/O module, it
must wait until the I/O operation is complete.
A lot of waisted time, because the CPU is much
faster then devices.
2. Interrupt-driven I/O
Issue read
command
3. Direct memory access
read status
of I/O module
not
ready
check
status
ready
read word from
I/O module
write word
to memory
more
words?
yes
no
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Interrupt-driven I/O
•
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Interrupt-driven I/O (cont’d)
After issuing an I/O command, the CPU has not to
wait until the operation has finished; instead of
waiting, the CPU continues with other useful work.
Issue read
command
When the I/O operation has been completed, the I/
O module issues an interrupt signal on the bus.
read word from
I/O module
After receiving the interrupt, the CPU moves the
data to/from memory, and issues a new command if
more data has to be read/written.
Do something
useful
Interrupt
write word
to memory
Advantage over programmed I/O
• Instead of waiting the operation to be finished,
the CPU can do some useful work
yes
more
words?
no
Still a problem
• The CPU has to take care of each data unit
(word), to move it to/from memory, and to issue
an I/O command.
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☞ If large amounts of data have to be moved, this
technique is still not efficient, because
- the CPU has to take care for each data unit
separately;
- handling the interrupt also takes some time.
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Direct Memory Access (DMA)
•
•
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Direct Memory Access (cont’d)
An additional module on the system bus, the DMA
module, takes care of the I/O transfer for the whole
sequence of data.
Issue read
command
for block
The CPU issues a command to the DMA module
and transfers to it all the needed information.
The DMA module performs all the operations
(acting similarly to the CPU with programmed I/O):
it transfers all the data between I/O module and
memory without going through the CPU.
Do something
useful
Interrupt
continue
A simple structure with DMA module:
When the DMA module has finished, it issues an
interrupt to the CPU.
•
When starting an operation, the CPU informs the
DMA module about:
- what operation (read or write);
- the address of the I/O device involved;
- the starting location in memory where information has to be stored to or read from;
- the number of words to be transferred.
Video
controller
Keyboard
controller
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Summary
•
•
•
•
•
•
•
•
•
Input/Output devices provide a means for
information storage and for interaction with the
computer. CPU, memory and devices are
interconnected by one or several system buses.
Having several system buses makes the system
faster and allows to connect devices tailored for
different bus standards.
The CPU chip is connected to the rest of the
system through address, data, and control pins.
A bus consists of data, address, and control lines;
address and data lines can be multiplexed.
Bus arbitration avoids simultaneous use of the bus
by two masters. Centralized and decentralized
arbitration schemes can be used.
Coordination of events on a bus can be
synchronous or asynchronous. Asynchronous
timing is more efficient but more difficult to
implement.
I/O modules are interfacing an I/O device to the
system bus. They are hiding the details of I/O
devices from the CPU.
Selection of an I/O device can be memory-mapped
or based on isolated I/O. With memory mapped I/O
there is a single address space for memory and I/O
devices. With isolated I/O, the two address spaces
are separated.
Three techniques can be used for I/O data transfer:
programmed I/O, interrupt-driven I/O, and direct
memory access.
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Hard disk
controller
Bus
CPU
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Diskette
controller
DMA
Module
Main
Memory