Working with Xilinx® devices
and place and route tools
Summary
Application note
AP0112 (v1.0) January 13, 2004
This application note provides an advanced Xilinx designer
with information on how to control the Xilinx place and route
software options and properties, and also includes
information on libraries.
The DXP-based FPGA development environment can be used to capture, synthesize, place and route
and download a digital system design into an FPGA. Place and route, the process of implementing the
design on the target silicon, requires an intimate understanding of the functionality and architecture of
the device, a task best performed by software tools provided by the device vendor. The vendor
software is operated by the DXP environment, which automatically manages all project and file
handling aspects required to generate the FPGA program file. There is a large degree of user-control
over this process, which this application note details.
Introduction
Xilinx tools are integrated and accessed in the DXP environment through the Device view (View »
Devices View). This view allow step-by-step control over the entire FPGA design process, enabling
you to program and debug your system design on the FPGA.
For a detailed description of the Devices view refer to the application note Processing the Captured
FPGA Design.
This application note makes reference to a number of Xilinx documents. Users wishing to change
any of the default settings should refer to these documents for details: Xilinx Development System
Reference Guide, Constraints Guide, and XST User Guide.
If you are not familiar with the Xilinx tools it is recommended that you start designing with the builtin default settings.
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Supported architectures
The system supports the latest Xilinx FPGA technology and includes both FPGA and PCB schematic
library support. The following table show the supported technology and its dependent schematic
libraries, at the time of publication of this document.
Technology
Vendor independent
library support
Vendor specific library
name
PCB Library
Virtex
Yes
Virtex FPGA
Virtex
Virtex E
Yes
VirtexE FPGA
Virtex-E
Virtex 2
Yes
Virtex-II FPGA
Virtex-II
Virtex 2 Pro
Yes
Virtex-II PRO FPGA
Virtex II Pro
Spartan 2
Yes
Spartan-II FPGA
Spartan-II
Spartan 2E
Yes
Spartan-IIE FPGA
Spartan-IIE
CoolRunner 2
Yes
CoolRunner-II FPGA
CoolRunner II
CoolRunner XPLA3
Yes
CoolRunner-XPLA3 FPGA
CoolRunner-XPLA3
XC9500
Yes
XC9500 FPGA
PLD XC9500
XC9500XV
Yes
XC9500 FPGA
PLD XC9500XV
XC9500XL
Yes
XC9500 FPGA
PLD XC9500XL
XCF
Yes
NA
XCF
XC18V00
Yes
NA
XC18V00
FPGA architecture-independent library
To maintain device independence, the system includes a large library of typical generic design
components, the FPGA Generic Library. This library can be found in the
\Altium2004\Library\FPGA folder. For complete documentation of this library refer to the FPGA
Generic Library Guide.
FPGA architecture-dependent libraries
If device independence is not required the system also includes Xilinx FPGA libraries. These integrated
libraries contain both the Unisim and Macro types of components.
Vendor-specific integrated libraries are packaged according to the selection guide provided in the Xilinx
Libraries Guide. This ensures that only specific components that are available with your target device
are used in your design. The FPGA design libraries can be found in the
\Altium2004\Library\Xilinx folder.
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Xilinx core generator component support
Specialized cores that have been created using the Xilinx Core Generator can be used in your FPGA
design. Once you have generated the core, you link the generated EDIF file to a schematic component,
and place this component in your FPGA design.
To create a component symbol from the EDIF, open it in the software and select Design » Create
Schematic Part from File from the menus. The EDIF file must be placed in the FPGA project folder, or
stored in a User pre-synthesized Model folder (specified in the FPGA Preferences dialog).
Integrated FPGA PCB libraries
There are also PCB design libraries available for many of the Xilinx programmable devices, in the
\Altium2004\Library\Xilinx folder. These libraries include both schematic symbols and PCB
footprints.
Xilinx place and route tools configuration
To enable the Xilinx FPGA process flow in the Devices view (the place and route tools are all accessed
by clicking the Build button), your design must be configured for a valid Xilinx target architecture. This
is done by including a suitable device constraint in a project constraint file, which belongs to a current
project configuration (Project » Configuration Manager). Once this is established, the FPGA design
process flow will be enabled and Xilinx options can be configured.
For an example of creating a design and configuring it for a target FPGA, refer to the tutorial
Getting Started with FPGA design.
Build options
The Build process allows interface with Xilinx tools and produces the bitstream (BIT) file to download
into your FPGA. By clicking on the down arrow, a list of individual steps used to complete the Build
process can be found.
Options
Reports
Figure 1. Vendor place and route tools are accessed via the Build button.
Click the Options icon adjacent to each stage to configure that feature. Errors or design rules that are
not allowed for your target architecture or in the design will be picked up at each stage of the Build
process. The location in the design and the error or warning is logged in a report file, accessed by
clicking on the appropriate Report icon.
For advanced users who want more control over the options passed to the Xilinx tools, each stage in
the Build process is linked to a script file located in the \Altium2004\System folder. Be aware that
these scripts are defaulted to standard optimization – any changes should be carefully applied in
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consultation with the Xilinx Development System Reference Guide. Individual Build stages, options and
the corresponding default script files are described below.
Translate EDIF files
This stage invokes the Xilinx NGDBuild tool, translating the EDIF output from the FPGA project
synthesis process to a Xilinx Native Generic Database (NGD) file and Xilinx Project Navigator project
(NPL) file. In this process, a logic design rule check is also run to confirm that the design is fit for
mapping to any target FPGA. For more information on options available with this process refer to
chapter 6 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_NGBuild.Txt script file. NGDBuild switches can be configured in this file,
in accordance with the Xilinx documentation. The Xilinx project can be opened in the Xilinx Project
Navigator if required.
Map design to FPGA
This stage invokes the Xilinx MAP tool, mapping the NGD file to the logic available in your target Xilinx
FPGA. In this process, a physical design rule check is run to find physical and logical errors that may
be present, depending on your target FPGA. The output of this process is an NCD (Native Circuit
Description) file. For more information on options available with this process refer to chapter 8 of the
Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_MAP.Txt script file. Map switches can be configured in this file, in
accordance with the Xilinx documentation.
Place and route
This stage invokes the Xilinx PAR tool and uses the NCD file output from the MAP process to place
and route. A placed and routed NCD file is produced, suitable for the bitstream generator. For more
information on options available with this process refer to chapter 10 of the Xilinx Development System
Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_PlaceAndRoute.Txt script file. PAR switches can be configured in this
file, in accordance with the Xilinx documentation.
Timing analysis
The Timing analysis stage invokes the Xilinx Trace (timing reporter and evaluator) tool. This conducts
static timing analysis on the design, based on the input timing constraint. It verifies that the design
meets the timing constraints, generating a report on the analysis. For more information on options
available with this process refer to chapter 13 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_Trace.Txt script file. Trace switches can be configured in this file, in
accordance with the Xilinx documentation. Timing analysis can be switched off if required, click on the
Timing Analysis Options icon.
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Make BIT file
This stage invokes the Xilinx BitGen tool to produce a bitstream (BIT) file from the placed and routed
design (NCD) file. The BIT file is used to download and program the FPGA, or to create a PROM file in
the Make PROM File stage. For more information on options available with this process refer to
chapter 15 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_BitGen.Txt script file. BitGen switches can be configured in this file, in
accordance with the Xilinx documentation.
Make PROM file
This optional stage is used to generate a program file for a Xilinx configuration device. It is available
once a target PROM has been selected by clicking on the Options icon. It invokes the Xilinx PromGen
tool, whose output format is dependent on the selected target device. For more information on options
available with this process refer to chapter 16 of the Xilinx Development System Reference Guide.
Advanced options that are not present when you click on the Options icon can be accessed in the
DefaultScript_Xilinx_PromGen.Txt script file. PromGen switches can be configured in this file,
in accordance with the Xilinx documentation.
Xilinx constraints entry
The DXP-based FPGA design environment supports a range of constraints that are device
independent. However, since not all FPGA families share the same technology there are also vendor
constraints that can be used. The Xilinx tools support a range of constraints that allow you to take
advantage of internal technology and other design options. For detailed information on Xilinx FPGA
constraints refer the Xilinx Constraints Guide.
Xilinx constraints can be included with your design by adding the Xilinx User Constraint (UCF) files to
the FPGA project. Multiple constraint files can be added, enable their use in the project by disabling the
Ignore UCF File option, accessed by clicking the Options button in the Translate Design stage of the
Build process.
Xilinx XST tools configuration
The system includes a powerful built-in synthesis engine, which is used by default. It also supports use
of the Xilinx XST synthesizer within the design environment. To enable an FPGA project to utilize the
Xilinx XST synthesis tool the project synthesis option must be set to XST Synthesizer. This is done by
selecting Project » Project Options from the menus, clicking on the Synthesis tab and choosing XST
Synthesizer from the dropdown Synthesizer list. Once this is selected you must indicate the folder
where the XST binary executable file resides using the Browse button. Various options can be
configured on the XST option page to best suit your design.
For advanced users, options that are not present on the Synthesis tab can be accessed from the
DefaultScript_XST_CPLD.Txt and DefaultScript_XST_FPGA.Txt script files located in the
\Altium2004\System folder. XST switches must be configured in accordance with the Xilinx XST
User Guide.
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Figure 2. Setting the XST synthesizer and options
If you are not familiar with the Xilinx synthesis tools it is recommended that you start designing with
the built-in DXP synthesis engine.
Revision History
Date
Version No.
Revision
19-Dec-2003
1.0
New product release
Software, documentation and related materials:
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