FPGA based Scalable Fixed Point QRD core using Dynamic Partial
Reconfiguration
Abstract:
This work presents an FPGA based scalable fixed point QRD architecture based on Givens
Rotation algorithm. The proposed QRD core utilizes an efficient pipelined and unfolded 2D
MAC based systolic array architecture with dynamic partial reconfiguration (DPR) capability.
An improved LUT based Newton-Rap son method is proposed for finding square root and
inverse square root which helps in reducing the area by 71% and latency by 50%, while
operating at a frequency 49% higher than the existing boundary cell architectures. The scalability
of the QRD core is achieved using DPR which results in reduction in dynamic power and area
utilization as compared to a static implementation. The proposed architecture is implemented on
Xilinx Virtex-6 FPGA for any real matrices of size m × n where, 4 ≤ n ≤ 8 and m ≥ n by
dynamically inserting or removing the partial modules. The evaluation results shows reduction in
latency, area and power as compared to CORDIC based architectures. The proposed scalable
QRD core is used for implementing a high performance adaptive equalizer (QRD-RLS
Algorithm) used in mobile receivers and the evaluation is done by transmitting BPSK symbols in
the training mode.
Existing Method:
Computational complexity of finding the inverse of an n×n matrix using the direct
method is O (n3) which increases with the order of the matrix. Also, a hardware implementation
of direct matrix inverse becomes a challenging problem. The computational stability and the fast
convergence rate is also a significant feature of QR decomposition.
Gram-Schmidt [GS]
algorithm offers reduced accuracy and stability in fixed precision environment. Householder
[HH] transformation suits well for dense matrices but it is difficult to carry out parallel
implementations since its working on entire column each time. Givens Rotation [GR] has the
capability of selectively annihilating individual matrix elements. An error analysis for computing
Further Details Contact: A Vinay 9030333433, 08772261612
Email: info@takeoffprojects.com | www.takeoffprojects.com
the inverse of a 4×4 matrix in fixed point environment is done for GS, HH, and GR in our
existing method.
Proposed Method:
This paper proposes an FPGA based scalable systolic array architecture for rotation
algorithm using the concept of Look-Up Table (LUT) based Newton Rap son method for inverse
square root and square root and achieves scalability using DPR. DPR allows for reconfiguring
parts of FPGA while rest of the device is still functioning and active. The major benefit of partial
reconfiguration is the time sharing of the resources thereby achieving considerable area and
power savings with a reduced reconfiguration time.
Applications:
1. Digital Signal Processing
2. Image processing…etc...
Advantages:
1. Area
2. Power consumption
System Configuration:In the hardware part a normal computer where Xilinx ISE 14.3 software can be easily
operated is required, i.e., with a minimum system configuration
HARDWARE REQUIREMENT
Processor
- Pentium –III
Speed
- 1.1 GHz
Further Details Contact: A Vinay 9030333433, 08772261612
Email: info@takeoffprojects.com | www.takeoffprojects.com
RAM
- 1 GB (min)
Hard Disk
- 40 GB
Floppy Drive
- 1.44 MB
Key Board
- Standard Windows Keyboard
Mouse
- Two or Three Button Mouse
Monitor
- SVGA
SOFTWARE REQUIREMENTS
 Operating System
:Windows95/98/2000/XP/Windows7
 Front End
: Modelsim 6.3 for Debugging and Xilinx 14.3 for
Synthesis and Hard Ware Implementation
 This software’s where Verilog source code can be used for design
implementation.
Further Details Contact: A Vinay 9030333433, 08772261612
Email: info@takeoffprojects.com | www.takeoffprojects.com
Further Details Contact: A Vinay 9030333433, 08772261612
Email: info@takeoffprojects.com | www.takeoffprojects.com