www.fairchildsemi.com
Deep Burst Mode Operation with Feedback
Impedance Modulation for Reducing Standby Power
Consumption of Switched-Mode Power Supplies
Abstract – Many electric appliances operate in standby
mode when not performing their main function. These
appliances consistently consume electric power and the
environmental impact of this power consumption has attracted
public attention. This paper presents “deep” burst mode
operation with feedback impedance modulation as a technique
to minimize standby power consumption. The proposed
method is verified with a 19V/65W prototype converter.
I.
INTRODUCTION
There are roughly 10 billion units of AC-DC
power supplies globally.[1] When an AC-DC
power supply is plugged to a power outlet without
loading, known as standby mode, it still consumes
energy to maintain its output voltage. As power
supplies are pervasive, the total power
consumption in standby mode is a considerable
portion of domestic energy consumption[2-3].
Consequently, regulatory agencies have started to
set standards for no-load power consumption for
these power supplies[4-5] and the regulations will
become stricter in the future.
There have been several attempts to reduce
standby power consumption of AC-DC switchedmode power supplies (SMPS), such as reviewing
industrial-available
techniques
of
SMPS
controllers[6], optimizing passive components[7],
applying additional circuitry[8], and modifying the
power converter topology[9]. The first two do not
change circuit topology, so are in favored by
SMPS manufacturers. The third and fourth
possibilities need variation on circuit topology or
additional part count, which takes time for
industrials to implement.
© 2012 Fairchild Semiconductor
In this paper, a novel method called “deep burst
mode” is introduced. With this method, the
conventional topology can be used without
additional circuitry. The next section analyzes
standby power consumption in typical AC-DC
SMPS. Deep burst mode is introduced in Section
III and an experiment result of a 19V/65W
prototype follows in Section IV. Section V
provides the conclusion of this paper.
II.
STANDBY POWER
CONSUMPTION OF SWITCHEDMODE POWER SUPPLIES
Figure 1 shows the typical structure of an
AC-DC SMPS with rated output power under
70W. The AC-DC SMPS mainly generates a DC
voltage output from universal AC inputs
(90~264Vrms). The SMPS is composed by
following parts: an electromagnetic interference
(EMI) filter used for meeting the EMI
requirements, a bridge rectifier rectifying AC
input voltage into a DC voltage on CBULK, a
flyback converter converting the DC voltage on
CBULK into specified DC output voltage, a PulseWidth Modulation (PWM) controller applied to
control the flyback converter, and a feedback
circuit taking the output-voltage information from
the secondary side into the PWM controller in the
primary side for regulation. For applying currentmode control, current information is sensed by a
current-sense resistor, RSENSE.
Deep Burst Mode Operation with Feedback Impedance Modulation for Reducing Standby Power Consumption of Switched-Mode Power Supplies
Flyback
Converter
Universal
AC Inputs
LLPF
NP NS
CX
Bridge
Rectifier
EMI Filter
LP
Feedback Circuit
cont.
SENSE 6
4 HV
RT 5
PWM
Controller
CFB
Primary Side
VDD 7
3 NC
NA
Secondary Side
Photo
coupler
GATE 8
2 FB
CLPF
-
MOSFET
1 GND
COUT
DC
Output
CBULK
RSENSE
Feedback Circuit
+
Shotcky
Diode
Photo
Coupler
cont.
Shunt
Regulator
Figure 1 General Structure of AC-DC SMPS under 70W
The SMPS operates in standby state when the
device connected to the DC output of the SMPS
does not perform its main function or when the
DC output is disconnected from any device. In
standby state, although outputs requires very low
or even no power, the SMPS still consumes some
power for maintaining its operation and the output
voltage. The major power losses are caused by:
Power Consumption in PWM Controller
Even when there is no load connected to the
output, the power supply should keep operating to
respond to the load variation of the output. To
keep the power supply operating, the PWM
controller should be properly biased, which results
in power consumption.
Power Consumption in Feedback Circuit
A typical feedback circuit for isolated SMPS is
shown in Figure 2. Because the primary side and
secondary side of the circuit need to be properly
biased for their operation, both of them consume
some power.
ZFB
FB
To
PWM
VOUT
Primary Secondary
Side
Side
VBIAS
IC
IF
RD
R1
Switching Loss
Every time the power MOSFET switches,
switching losses occur. The loss comes from
changing the state of the MOSFET from ON to
OFF or from OFF to ON. Generally, these power
losses are proportional to switching frequency.
Modern PWM controllers employ burst mode
operation to reduce switching loss.
Figure 3 gives typical operation of burst mode,
where the GATE signal is alternatively enabled
and disabled according to the feedback voltage.
tburst=1/fburst
VFB
VFB-ZDC
trest
GATE
Npulse
Time
Figure 3 Burst Mode Operation of PWM Controllers
In conventional AC-DC SMPS, there are
continuous losses in the startup circuit and X-Cap
(CX in Figure 1) bleeder circuit. With a state-ofthe-art PWM controller, these losses can be
reduced or eliminated by circuit integration.[10-11]
RF CF
VFB
PC817
Controller IC
KA431
R2
Figure 2 Typical Feedback Circuit of Isolated SMPS
© 2012 Fairchild Semiconductor
2
Deep Burst Mode Operation with Feedback Impedance Modulation for Reducing Standby Power Consumption of Switched-Mode Power Supplies
III.
DEEP BURST MODE
OPERATION PRINCIPLES
To lower the standby power consumption, the
power consumptions mentioned in Section II must
be reduced. Deep burst mode is an innovative
designed feedback-control mechanism. It is aimed
at reducing standby power losses in the feedback
circuit and switching process by modulating
internal parameters of the PWM controller;
nothing needs to change for other SMPS parts.
Varying feedback configuration can cause
negative effects on operation of the SMPS, so
deep burst mode activates only when the loading is
quite small. Figure 4 shows a conceptual flow of
deep burst mode to avoid negative impact.
Is loading
extra light?
B. Linear Operating Region of Shunt Regulators
Figure 5 shows circuitry around the shunt
regulator (KA431) in the feedback circuit. The
operation principle of shunt regulators is to adjust
IKA by monitoring VREF; higher VREF means larger
IKA. According to datasheets of shunt regulators;
for operating in linear range, VKA should be higher
than the internal reference voltage (2.5V in typical)
and IKA should be larger than minimum the
regulation current (IKA(MIN), 0.45mA in typical)[12].
As a result, the linear operating range can be
drawn as Figure 6.
VOUT
VF
IKA
Activate deep
burst mode
operation
YES
RD
VKA
VREF
Figure 5 Circuit Around a Shunt Regulator
IKA
NO
Normal
Operation
NO
Switch
MOSFET to
keep the
controller IC
working
YES
VOUT  VF  2.5
RD
Modulate ZFB to
be larger and
clamp VFB
internally
(VKA<VREF)
Linear
Region
Supply voltage of
controller is nearing its
lower boundary?
I KA( MIN )
Cut-off
Region
NO
Go back to
normal
operation
YES
Deep Burst Mode Operation
Figure 4 Conceptual Flow of Deep Burst Mode Operation
A. Activate Deep-Burst Mode Operation
To activate deep burst mode, the PWM
controller must ensure that loading of the SMPS is
very low. In no-load condition, most PWM
controllers operate in burst mode, as shown in
Figure 3, where GATE stops when VFB is lower
than VFB-ZDC. The non-switching time, trest,
increases as load decreases, thus trest is used as an
indicator for very light-load condition.
The dynamic load change might activate deepburst mode operation, which can lead to oscillation
of the output. Therefore, a delay is introduced to
avoid prematurely entering deep burst mode.
To explain the operation principle of deep burst
mode, characteristics of shunt regulator should be
explained. Then the configuration inside the
feedback-pin (FB-pin) of the PWM controller
needs to be discussed. With this background
understandings, the whole operation principle can
be described step-by-step.
© 2012 Fairchild Semiconductor
~ 2.5V
VREF
Figure 6 Characteristics of Shunt Regulator
Detect loading
being increased?
C. Configuration and Operation of PWM
Controller for Deep Burst Mode
In deep-burst mode, a new feedback impedance
(ZFB) modulation technique is employed.
Configuration of FB-pin internal circuitry is
shown in Figure 7. Once activated, the deep-burst
mode logic does the following manipulations .


Switch ZFB to a larger value
Connect RCLAMP between FB-pin and ground
VBIAS
VOUT
Deep-Burst
Logic
ZFB
FB
To
PWM
IC IF
VFB
RCLAMP
VDD
Controller IC
RD
R1
RF CF
PC817
VREF
KA431 R2
Figure 7 FB-Pin Configuration and Feedback Circuit
of Deep Burst Mode
The objectives of deep burst mode operation are:

Reduce power consumption in feedback
circuit by increasing ZFB impedance
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Deep Burst Mode Operation with Feedback Impedance Modulation for Reducing Standby Power Consumption of Switched-Mode Power Supplies


Prevent UVLO of PWM controller by
modulating ZFB impedance actively
Reduce switching loss by rising VFB-ZDC
With the controller cycling through these steps,
the supply voltage of controller is kept higher than
its allowable minimum level and output voltage is
regulated around its specified value.
Reducing Power Consumption in Feedback
Circuit
With the RCLAMP between FB-pin and ground,
VFB is essentially clamped as:
VFB CLAMPED 
RCLAMP
VBIAS
Z FB  RCLAMP
VOUT
Step 3
Step 2
Step 4
Step 1
time
(1)
Once VFB-CLAMPED is lower than VFB-ZDC, GATE
output is essentially terminated. Meanwhile, due to
GATE output stopping, output voltage drops and
the VREF of the shunt regulator drops. As a result,
IF drops to IKA(MIN) and the shunt regulator works
in the cut-off region (Figure 6). The large ZFB
reduces IC. These manipulations reduce power
consumption in the feedback circuit.
VDD
VDD-ZFBR
time
VFB rise due to
Modulating ZFB
VFB
VFB-ZDC
(normal mode)
VFB fall due to
VOUT rising
VFB-ZDC
(deep-burst mode)
VFB drop due to
abruptly switching ZFB
time
VGATE
time
Large-ZFB
state
Modulating-ZFB
state
Large-ZFB
state
Figure 8 Key-Waveform Diagram of Deep-Burst Mode Operation
Preventing UVLO of PWM Controller
Under no-load condition, power consumption of
the controller itself is a dominant factor of the total
power consumption of the power supply.
Therefore, maintaining the supply voltage of the
controller (VDD) as low as possible is critical to
reducing the standby power consumption.
As shown in Figure 4, as long as the load
remains at its minimum level, deep-burst mode
operation detects VDD to control the GATE output,
preventing UVLO. The procedure is implemented
by the following steps (corresponding waveforms
are shown in Figure 8):
 Step 1: Once deep burst mode is activated, ZFB
switches to large impedance, RCLAMP connects
to the FB-pin, and VFB-ZDC is heightened. VFBCLAMP is always lower than VFB-ZDC, so there
should be no GATE output.
 Step 2: Once VDD drops to VDD-ZFBR, which is
near the minimum operation voltage for the
controller, deep burst mode starts modulating
ZFB to smaller impedance.
 Step 3: Once ZFB is modulated to smaller
impedance, VFB-CLAMP and VFB both rise. When
VFB rises above VFB-ZDC, the GATE signal
starts to output. At this moment, both VDD and
VOUT get the required energy.
 Step 4: Rising output voltage causes VFB to
drop. Once VFB drops below VFB-ZDC, the
GATE signal stops and deep burst mode logic
switches ZFB to large impedance immediately.
© 2012 Fairchild Semiconductor
Reducing Switching Loss
Raised VFB-ZDC causes burst mode operation to
occur at higher VFB value. For peak-current mode
control, the peak value of primary-side current
(IPEAK) is proportional to VFB.
Figure 9 shows waveform of primary-side
current of a flyback converter operating in deep
burst mode, where the average switching
frequency is equivalent to:
f SW . AVG  f burst  N pulse
(2)
The relationship between IPEAK and the average
switching frequency (fSW.AVG) can be represented as:
1
PIN   LPRI  I PEAK 2 VBULK  f SW . AVG
2
(3)
where LPRI is the primary-side inductance, VBULK
is the voltage on CBULK, and PIN is input power of
the flyback converter.
For a specified PIN, higher IPEAK leads to lower
fSW.AVG. Thus, the increased VFB-ZDC reduces
average switching loss.
tburst=1/fburst
IPRI
K VFBZDC
K  VFB
Npulse
I PEAK
time
Figure 9 Primary-Side Current of Flyback Converter Operating
in Deep Burst Mode
4
Deep Burst Mode Operation with Feedback Impedance Modulation for Reducing Standby Power Consumption of Switched-Mode Power Supplies
D. Exiting Deep Burst Mode
Modifying the FB-pin configuration can affect
the feedback stability of SMPS since it can change
the location of the pole of the compensation
network. To minimize stability issues, changing
the feedback impedance only occurs in standby
state. As a result, the control algorithm to exit
deep burst mode needs to be carefully designed.
To exit deep burst mode, all the modifications to
the feedback impedance and control circuit should
be reset: recovering ZFB back to normal value,
disconnecting RCLAMP from the FB pin, and turning
VFB-ZDC to normal-mode value.
According to status of ZFB impedance through
the steps in Figure 8, the process can be
categorized into two states: large-ZFB state and
modulating-ZFB state. Two conditions for exiting
deep-burst mode are implemented in the deepburst mode logic:
1) When loading gradually increases from noload, the increased power requirement extends the
duration of modulating-ZFB state. This time
duration can be an indicator of increased load. As
the duration increases beyond a specific designed
threshold, the controller exits deep-burst mode.
2) If a drastic load transient occurs during
large-ZFB state, the PWM controller should
modulate ZFB immediately to start MOSFET
switching. In this situation, VFB rises quickly even
if clamped. Sudden rise of VFB can indicate a load
step change to exit deep burst mode during largeZFB state.
IV.
EXPERIMENTAL RESULTS
The deep burst mode operation discussed in this
paper was implemented in Fairchild’s mWSaver™
PWM controller FAN6756[10] and applied to a
19V/65W adaptor for laptop computers, whose
schematic is shown in Figure 1 and Figure 7.
Major parameters of the experimental prototype
are listed in Table 1. With this PWM controller,
the no-load power consumption of a 19V/65W
adaptor can be as low as 30mW.
Figure 10 Photograph of the Experiment Prototype
TABLE 1. PARAMETERS OF EXPERIMENT PROTOTYPE
Category
Power Stage
Passives
Semiconductor
Devices
Feedback
components
© 2012 Fairchild Semiconductor
Parameter
Value
Parameter
Value
LP
510µH
COUT
1000µF
NP
38
LLPF
1.6µF
NS
8
CLPF
470µF
NA
7
Controller
FAN6756
Photo Coupler
PC817A
Shunt Regulator
KA431
MOSFET
FQPF7N65C
Schottky Diode
MBR20150CT
R1
200kΩ
RD
1.2kΩ
R2
30kΩ
CFB
1nF
RF
4.7kΩ
RSENSE
0.176Ω
CF
2.2nF
5
Deep Burst Mode Operation with Feedback Impedance Modulation for Reducing Standby Power Consumption of Switched-Mode Power Supplies
Figure 11 shows waveforms of FAN6756 in
deep burst mode operation. In area I, the flyback
converter operates in full-load condition. In area II,
loading is decreased to no load, so the IC operates
in burst mode. The controller assures that loading
is quite low by checking tREST > 10ms. After
waiting for the 900ms delay, the controller
activates deep burst mode operation, shown in area
III. Where the VDD-ZFBR is 7V, VFB-ZDC is 2.55V
(outside deep-burst mode, it is 2.0V). Large ZFB
value is 90kΩ, normal ZFB value is 8.5kΩ. In the
last area of the figure, loading is changed back to
full load, so the controller exits deep burst mode
and resumes normal operation.
I II
III
IV
Full Load
No Load
VRD≈0.574V
IF≈0.478mA
VRD≈0.5V
IF≈0.417mA
VRD≈0.934V
IF≈0.778mA
ZFB=8.5kΩ
ZFB=90kΩ (most of the time)
Figure 12 Deep Burst Mode
and Voltage across
VRDOperation
≈0.574V
≈0.478mA
RD (C1: GATE, C2:IFV
FB, C3: VRD, 500ms/div)
The measured power consumption under noload condition of the experiment prototype is
shown in Table 2. For universal AC inputs from
90 to 264Vrms, the no-load power consumptions
are all below 30mW, which can meet most
international regulations and standards for standby
power consumption with enough margin.
TABLE 2. NO-LOAD POWER CONSUMPTION OF THE
EXPERIMENT PROTOTYPE
AC Input (Vrms)
No-Load Power
Consumption (mW)
90
18
115
19
230
24
264
27
Figure 11 Deep Burst Mode Operation of FAN6756 PWM
Controller (C1: GATE, C2: VFB, C3: VDD, C4: VOUT,
1s/div)
To get the IF of the photo coupler, voltage
across RD in Figure 7 is measured. During burst
mode, IF is around 0.778mA in this system. With
ZFB switched to a larger value, IF is reduced to
~0.417mA, which is almost the minimum
regulation current of the applied shunt regulator.
As IF is reduced, the coupled current IC decreases;
that is, power consumption in both primary and
secondary side of the feedback circuit is reduced.
© 2012 Fairchild Semiconductor
V.
CONCLUSIONS
This paper has proposed deep burst mode
operation, where the standby power consumption
of an AC-DC SMPS is dramatically reduced by
changing feedback circuit configuration and
adding a dedicated logic circuit. The experimental
prototype of a 19V/65W flyback converter
confirms the feasibility and effectiveness of deep
burst mode operation. Therefore, the mechanism is
suitable for reducing the standby power
consumption of AC-DC SMPS.
6
Deep Burst Mode Operation with Feedback Impedance Modulation for Reducing Standby Power Consumption of Switched-Mode Power Supplies
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[2]
[3]
[4]
[5]
[6]
[7]
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© 2012 Fairchild Semiconductor
Hang-Seok Choi; Huh, D.Y. , “Techniques to Minimize Power
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[9] Byoung-Hee Lee; Young-Do Kim; Gun-Woo Moon , “SingleSwitching Double-Powering Converter for Reducing Power
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[10] Fairchild Datasheet, “FAN6756 – mWSaver™ PWM
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[11] Shao-Chun Huang, “AX-CAP™ Technology,” Fairchild
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[8]
Walter Chiu received B.S. and M.S. degrees
in electrical engineering from National
Taiwan University, Taipei, Taiwan, in 2008
and 2010. He is currently an application
engineer in the Power Conversion group of
Fairchild Semiconductor Taiwan, where he
is involved in SSR flyback power
management ICs and the development of
mWSaver™-technology PWM controllers.
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