VHDL Math Tricks of
the Trade
by
Jim Lewis
Director of Training, SynthWorks Design Inc
Jim@SynthWorks.com
http://www.SynthWorks.com
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
VHDL Math Tricks of the Trade
MAPLD 2003
SynthWorks
VHDL is a strongly typed language. Success in VHDL
depends on understanding the types and overloaded
operators provided by the standard and numeric
packages.
The paper gives a short tutorial on:
• VHDL Types & Packages
• Strong Typing Rules
• Converting between Std_logic_vector, unsigned &
signed
• Ambiguous Expressions
• Arithmetic Coding Considerations
• Math Tricks
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P2
SynthWorks
Common VHDL Types
TYPE
Value
Origin
std_ulogic
std_ulogic_vector
std_logic
std_logic_vector
'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-'
array of std_ulogic
resolved std_ulogic
array of std_logic
std_logic_1164
std_logic_1164
std_logic_1164
std_logic_1164
unsigned
array of std_logic
signed
array of std_logic
numeric_std,
std_logic_arith
numeric_std,
std_logic_arith
boolean
character
string
integer
real
time
true, false
191 / 256 characters
array of character
-(231 -1) to (231 - 1)
-1.0E38 to 1.0E38
1 fs to 1 hr
Lewis
standard
standard
standard
standard
standard
standard
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
Packages for Numeric Operations
●
●
●
MAPLD 2003 P3
SynthWorks
numeric_std
-- IEEE standard
● Defines types signed, unsigned
● Defines arithmetic, comparison, and logic operators for these types
std_logic_arith
-- Synopsys, a defacto industry standard
● Defines types signed, unsigned
● Defines arithmetic, and comparison operators for these types
std_logic_unsigned
-- Synopsys, a defacto industry standard
● Defines arithmetic and comparison operators for std_logic_vector
Recommendation:
Use numeric_std for new designs
Ok to use std_logic_unsigned with numeric_std*
* Currently, IEEE 1076.3 plans to have a numeric package that permits
unsigned math with std_logic_vector
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P4
Packages for Numeric Operations
●
Using IEEE Numeric_Std
library
library ieee
ieee ;;
use
use ieee.std_logic_1164.all
ieee.std_logic_1164.all ;;
use
;;
numeric_std
use ieee.numeric_std.all
ieee.numeric_std.all
●
SynthWorks
Recommendation:
Recommendation:
Use
Use numeric_std
numeric_std for
for new
new designs
designs
Use
Use numeric_std
numeric_std or
or
std_logic_arith,
std_logic_arith, but
but
never
never both
both
Using Synopsys Std_Logic_Arith
library
library ieee
ieee ;;
use
ieee.std_logic_1164.all
use ieee.std_logic_1164.all ;;
use
;;
std_logic_arith
use ieee.std_logic_arith.all
ieee.std_logic_arith.all
use
use ieee.std_logic_unsigned.all
ieee.std_logic_unsigned.all ;;
Recommendation,
Recommendation, ifif you
you use
use Synopsys
Synopsys Packages:
Packages:
Use
Use std_logic_arith
std_logic_arith for
for numeric
numeric operations
operations
Use
Use std_logic_unsigned
std_logic_unsigned only
only for
for counters
counters and
and testbenches
testbenches
Don't
Don't use
use the
the package
package std_logic_signed.
std_logic_signed.
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
SynthWorks
Unsigned and Signed Types
●
Used to represent numeric values:
TYPE
unsigned
signed
●
MAPLD 2003 P5
Value
0 to 2NN - 1
(N-1) to 2(N-1)
(N-1) - 1
- 2(N-1)
Notes
2's Complement number
Usage similar to std_logic_vector:
signal A_unsigned
signal B_signed
signal C_slv
. . .
Lewis
: unsigned(3 downto 0) ;
: signed (3 downto 0) ;
: std_logic_vector (3 downto 0) ;
A_unsigned <= "1111" ;
== 15
15 decimal
decimal
B_signed
<= "1111" ;
== -1
-1 decimal
decimal
C_slv
<= "1111" ;
== 15
15 decimal
decimal only
only ifif using
using
std_logic_unsigned
std_logic_unsigned
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P6
SynthWorks
Unsigned and Signed Types
●
Type definitions identical to std_logic_vector
type UNSIGNED is array (natural range <>) of std_logic;
type SIGNED is array (natural range <>) of std_logic;
●
How are the types distinguished from each other?
●
How do these generate unsigned and signed arithmetic?
●
For each operator, a unique function is called
function "+" (L, R: signed) return signed;
function "+" (L, R: unsigned) return unsigned ;
●
This feature is called Operator Overloading:
● An operator symbol or subprogram name can be used
more than once as long as calls are differentiable.
Lewis
MAPLD 2003 P7
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
SynthWorks
Overloading Basics
●
Simplified view of overloading provided by VHDL packages
Operator
Operator
Logic
Logic
Left
Left
TypeA
TypeA
Right
Right
TypeA
TypeA
Result
Result
TypeA
TypeA
Numeric
Array
Array
Integer
Array
Integer
Array
Array1
Array1
Array1
Notes:
Notes:
Array
Array ==
TypeA
TypeA ==
unsigned,
unsigned, signed,
signed, std_logic_vector
std_logic_vector22
boolean,
boolean, std_logic,
std_logic, std_ulogic,
std_ulogic, bit_vector
bit_vector
std_logic_vector,
std_ulogic_vector,
std_logic_vector, std_ulogic_vector,
signed
signed33,, unsigned
unsigned33
Array
Array and
and TypeA
TypeA types
types used
used in
in an
an expression
expression must
must be
be the
the same.
same.
1) for comparison operators the result is boolean
2) only for std_logic_unsigned.
3) only for numeric_std and not std_logic_arith
●
For a detailed view of VHDL's overloading, get the VHDL Types and
Operators Quick Reference card at: http://www.SynthWorks.com/papers
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P8
SynthWorks
Overloading Examples
Signal
Signal
Signal
Signal
Signal
Signal
signal
signal
.. .. ..
A_uv,
A_uv, B_uv,
B_uv, C_uv,
C_uv, D_uv,
D_uv, E_uv
E_uv :: unsigned(7
unsigned(7 downto
downto 0)
0) ;;
R_sv,
R_sv, S_sv,
S_sv, T_sv,
T_sv, U_sv,
U_sv, V_sv
V_sv :: signed(7
signed(7 downto
downto 0)
0) ;;
J_slv,
:: std_logic_vector(7
J_slv, K_slv,
K_slv, L_slv
L_slv
std_logic_vector(7 downto
downto 0)
0) ;;
Y_sv
:: signed(8
Y_sv
signed(8 downto
downto 0)
0) ;;
--- Permitted
Permitted
A_uv
A_uv <=
<= B_uv
B_uv ++ C_uv
C_uv ;;
D_uv
D_uv <=
<= B_uv
B_uv ++ 11 ;;
E_uv
E_uv <=
<= 11 ++ C_uv;
C_uv;
--- Unsigned
Unsigned ++ Unsigned
Unsigned == Unsigned
Unsigned
--- Unsigned
Unsigned ++ Integer
Integer == Unsigned
Unsigned
--- Integer
Integer ++ Unsigned
Unsigned == Unsigned
Unsigned
R_sv
R_sv
U_sv
U_sv
V_sv
V_sv
-------
<=
<=
<=
<=
<=
<=
S_sv
S_sv ++ T_sv
T_sv ;;
S_sv
+
1
S_sv + 1 ;;
11 ++ T_sv;
T_sv;
J_slv
J_slv <=
<= K_slv
K_slv ++ L_slv
L_slv ;;
------Lewis
Signed
Signed
Signed
Signed
Integer
Integer
++
++
++
Signed
Signed
Integer
Integer
Signed
Signed
●
Signed
Signed
Signed
Signed
Signed
Signed
--- if
if using
using std_logic_unsigned
std_logic_unsigned
Illegal
Illegal Cannot
Cannot mix
mix different
different array
array types
types
Solution
persented
later
in
type
conversions
Solution persented later in type conversions
Y_sv
-Y_sv <=
<= A_uv
A_uv -- B_uv
B_uv ;;
-- want
want signed
signed result
result
MAPLD 2003 P9
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
Strong Typing Implications
●
==
==
==
SynthWorks
Size and type of target (left) = size and type of expression (right)
Each operation returns a result that has a specific size based on
rules of the operation. The table below summarizes these rules.
Operation
Y <= "10101010" ;
Y <= X"AA" ;
Y <= A ;
Y <= A and B ;
W <= A > B ;
Y <= A + B ;
Y <= A + 10 ;
V <= A * B ;
Size of Y = Size of Expression
number of digits in literal
4 * (number of digits)
A'Length = Length of array A
A'Length = B'Length
Boolean
Maximum (A'Length, B'Length)
A'Length
A'Length + B'Length
Some think VHDL is difficult because of strong typing
Master the above simple rules and it is easy
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P10
SynthWorks
Strong Typing Implications
signal A8, B8, Result8
signal Result9
signal Result7
. . .
-- Simple Addition, no
Result8 <= A8 + B8 ;
:
:
:
unsigned(7
unsigned(8
unsigned(6
downto
downto
downto
0)
0)
0)
;
;
;
carry out
-- Carry Out in result
Result9 <= ('0' & A8) + ('0' & B8) ;
-- For smaller result, slice input arrays
Result7 <= A8(6 downto 0) + B8(6 downto 0) ;
Strong Typing = Strong Error Checking Built into the Compiler
This means less debugging.
Without VHDL, you better have a good testbench and
lots of time to catch your errors.
Lewis
SynthWorks
Type Conversions
●
●
●
●
Lewis
MAPLD 2003 P11
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
VHDL is dependent on overloaded operators and conversions
What conversion functions are needed?
● Signed & Unsigned (elements)
<=> Std_Logic
●
Signed & Unsigned
<=> Std_Logic_Vector
●
Signed & Unsigned
<=> Integer
●
Std_Logic_vector
<=> Integer
VHDL Built-In Conversions
●
Automatic Type Conversion
●
Conversion by Type Casting
Conversion functions located in Numeric_Std
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P12
Automatic Type Conversion:
Unsigned, Signed <=> Std_Logic
●
SynthWorks
Two types convert automatically when both are subtypes of the same type.
subtype
subtype std_logic
std_logic is
is resolved
resolved std_ulogic
std_ulogic ;;
●
●
Converting between std_ulogic and std_logic is automatic
Elements of Signed, Unsigned, and std_logic_vector = std_logic
● Elements of these types convert automatically to std_ulogic or std_logic
Legal
Assignments
Implication:
A_sl
A_sl
B_sul
L_uv(0)
M_slv(2)
Y_sl
Y_sl <=
<=
Lewis
<=
<=
<=
<=
<=
J_uv(0)
J_uv(0) ;;
K_sv(7) ;
C_sl ;
N_sv(2) ;
A_sl
A_sl and
and B_sul
B_sul and
and
J_uv(2)
J_uv(2) and
and K_sv(7)
K_sv(7) and
and M_slv(2);
M_slv(2);
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P13
SynthWorks
Type Casting:
Unsigned, Signed <=> Std_Logic_Vector
●
Use type casting to convert equal sized arrays when:
●
●
●
Elements have a common base type (i.e. std_logic)
Indices have a common base type (i.e. Integer)
Unsigned, Signed < => Std_Logic_Vector
A_slv
A_slv
C_slv
C_slv
G_uv
J_sv
●
<=
<=
<=
<=
<=
<=
std_logic_vector(
std_logic_vector(
std_logic_vector(
std_logic_vector(
unsigned( H_slv )
signed(
K_slv )
)) ;;
)) ;;
Motivation, Unsigned - Unsigned = Signed?
signal
signal X_uv,
X_uv, Y_uv
Y_uv
signal
signal Z_sv
Z_sv
.. .. ..
Z_sv
Z_sv <=
<= signed('0'
signed('0'
Lewis
B_uv
B_uv
D_sv
D_sv
;
;
:: unsigned
unsigned (6
(6 downto
downto 0)
0) ;;
:: signed
(7
signed
(7 downto
downto 0)
0) ;;
&& X_uv)
X_uv) -- signed('0'
signed('0' && Y_uv)
Y_uv) ;;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P14
Numeric_Std Conversions:
Unsigned, Signed <=> Integer
SynthWorks
Converting to and from integer requires a conversion function.
● Unsigned, Signed => Integer
●
Unsigned_int
Unsigned_int
Signed_int
Signed_int
●
Integer
TO_INTEGER
TO_INTEGER (( A_uv
A_uv )) ;;
TO_INTEGER
TO_INTEGER (( B_sv
B_sv )) ;;
=> Unsigned, Signed
C_uv
C_uv
D_sv
D_sv
●
<=
<=
<=
<=
<=
<=
<=
<=
TO_UNSIGNED
TO_UNSIGNED (( Unsigned_int,
Unsigned_int, 88 )) ;;
TO_SIGNED
(
Signed_int,
TO_SIGNED ( Signed_int, 88 )) ;;
Array
Array
width
width == 88
Motivation (indexing an array of an array):
Data_slv
Data_slv <=
<=
signal
signal
signal
signal
signal
signal
signal
signal
A_uv,
A_uv, C_uv
C_uv
Unsigned_int
Unsigned_int
B_sv,
B_sv, D_sv
D_sv
Signed_int
Signed_int
::
::
::
::
ROM(
ROM(
TO_INTEGER(
TO_INTEGER( Addr_uv)
Addr_uv) )) ;;
unsigned
unsigned (7
(7 downto
downto 0)
0) ;;
integer
integer range
range 00 to
to 255
255 ;;
signed(
signed( 77 downto
downto 0)
0) ;;
integer
integer range
range -128
-128 to
to 127;
127;
Lewis
MAPLD 2003 P15
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
Std_Logic_Arith Conversions:
Unsigned, Signed <=> Integer
SynthWorks
Converting to and from integer requires a conversion function.
● Unsigned, Signed => Integer
●
Unsigned_int
Unsigned_int
Signed_int
Signed_int
●
Integer
=> Unsigned, Signed
C_uv
C_uv
D_sv
D_sv
●
<=
<= Conv_UNSIGNED
Conv_UNSIGNED (( Unsigned_int,
Unsigned_int, 88 )) ;;
<=
Conv_SIGNED
(
Signed_int,
<= Conv_SIGNED ( Signed_int, 88 )) ;;
Array
Array
width
width == 88
Motivation (indexing an array of an array):
Data_slv
Data_slv <=
<=
signal
signal
signal
signal
signal
signal
signal
signal
Lewis
<=
<= Conv_INTEGER
Conv_INTEGER (( A_uv
A_uv )) ;;
<=
<= Conv_INTEGER
Conv_INTEGER (( B_sv
B_sv )) ;;
A_uv,
A_uv, C_uv
C_uv
Unsigned_int
Unsigned_int
B_sv,
B_sv, D_sv
D_sv
Signed_int
Signed_int
::
::
::
::
ROM(
ROM( Conv_INTEGER(
Conv_INTEGER( Addr_uv)
Addr_uv) )) ;;
unsigned
unsigned (7
(7 downto
downto 0)
0) ;;
integer
integer range
range 00 to
to 255
255 ;;
signed(
signed( 77 downto
downto 0)
0) ;;
integer
integer range
range -128
-128 to
to 127;
127;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P16
Std_Logic_Vector <=> Integer
SynthWorks
●
Converting between std_logic_vector and integer is a two step process:
●
Numeric_Std:
Std_Logic_Vector => Integer
Unsigned_int
Unsigned_int <=
<=
Signed_int
<=
Signed_int
<=
to_integer(
to_integer(
to_integer(
to_integer(
Numeric_Std:
●
C_slv
C_slv
D_slv
D_slv
Integer
unsigned(
unsigned( A_slv
A_slv ));
));
signed(
signed( B_slv
B_slv ));
));
=> Std_Logic_Vector
<=
<= std_logic_vector(
std_logic_vector( to_unsigned(
to_unsigned( Unsigned_int,
Unsigned_int, 88 ));
));
<=
Signed_int,
<= std_logic_vector(
std_logic_vector( to_signed(
to_signed(
Signed_int, 88 ));
));
signal
signal
signal
signal
signal
signal
signal
signal
A_slv,
A_slv, C_slv
C_slv
Unsigned_int
Unsigned_int
B_slv,
B_slv, D_slv
D_slv
Signed_int
Signed_int
Lewis
::
::
::
::
std_logic_vector
std_logic_vector (7
(7 downto
downto 0)
0) ;;
integer
integer range
range 00 to
to 255
255 ;;
std_logic_vector(
std_logic_vector( 77 downto
downto 0)
0) ;;
integer
integer range
range -128
-128 to
to 127;
127;
SynthWorks
Ambiguous Expressions
●
●
MAPLD 2003 P17
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
An expression / statement is ambiguous if more than one operator
symbol or subprogram can match its arguments.
Std_Logic_Arith defines the following two functions:
function
function "+"
"+" (L,
(L, R:
R: SIGNED)
SIGNED) return
return SIGNED;
SIGNED;
function
"+"
(L:
SIGNED;
R:
UNSIGNED)
function "+" (L: SIGNED; R: UNSIGNED) return
return SIGNED;
SIGNED;
●
The following expression is ambiguous and an error:
Z_sv
Z_sv
<=
<=
A_sv
A_sv
++ "1010"
"1010" ;;
Is
Is "1010"
"1010" Signed
Signed or
or Unsigned
Unsigned
"1010" =
●
●
Lewis
-6 or 10
Issues typically only arise when using literals.
How do we solve this problem?
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P18
SynthWorks
Std_Logic_Arith:
Ambiguous Expressions
●
VHDL type qualifier (type_name') is a mechanism that specifies the type
of an operand or return value of a subprogram (or operator).
Z_sv
Z_sv
●
<=
<=
A_sv
A_sv
++ signed("1010")
signed("1010") ;;
<=
<=
A_sv
A_sv
++ signed(B_slv)
signed(B_slv) ;;
Recommended solution, use integer:
Z_sv
Z_sv
<=
<=
A_sv
A_sv
Lewis
-- 66 ;;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
Addition Operators:
-
Arrays with Arrays:
Add_uv
Add_uv
Sub_uv
Sub_uv
●
+
MAPLD 2003 P19
SynthWorks
Addition Operators
●
Effects
Effects all
all numeric
numeric
operators
operators in
in
std_logic_arith
std_logic_arith
Without ', it is type casting. Use type casting for:
Z_sv
Z_sv
●
++ signed'("1010")
signed'("1010") ;;
Leaving out the ' is an error:
--- Z_sv
Z_sv <=
<=
●
A_sv
A_sv
<=
<= A_uv
A_uv ++ B_uv
B_uv ;;
<=
<= C_uv
C_uv -- D_uv
D_uv ;;
•• Size
Size of
of result
result ==
•• Size
Size of
of largest
largest array
array operand
operand
•• Size
of
Add
=
maximum(A,
Size of Add = maximum(A, B)
B)
•• Shorter
Shorter array
array gets
gets extended.
extended.
Arrays with Integers:
Inc_uv
Inc_uv
Y_uv
Y_uv
<=
<= Base_uv
Base_uv ++ 11 ;;
<=
<= A_uv
A_uv ++ 45
45 ;;
•• Caution:
Caution: Integers
Integers must
must fit
fit into
into an
an
array
the
same
size
as
the
result.
array the same size as the result.
•• Extra
Extra MSB
MSB digits
digits are
are lost
lost
•• A
A must
must be
be at
at least
least 66 bits
bits
By convention the left most bit is the MSB
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P20
Use Integers with Care
●
SynthWorks
Synthesis tools create a 32-bit wide resources for unconstrained integers
signal
signal Y_int,
Y_int, A_int,
A_int, B_int
B_int :: integer
integer ;;
.. .. ..
Y_int
Y_int <=
<= A_int
A_int ++ B_int
B_int ;;
●
●
Do not use unconstrained integers for synthesis
Specify a range with integers:
signal
signal A_int,
A_int, B_int:
B_int: integer
integer range
range -8
-8 to
to 7;
7;
signal
signal Y_int
Y_int :: integer
integer range
range -16
-16 to
to 15
15 ;;
.. .. ..
Y_int
Y_int <=
<= A_int
A_int ++ B_int
B_int ;;
●
Recommendation: Use integers only as constants or literals
Y_uv
Y_uv <=
<= A_uv
A_uv ++ 17
17 ;;
Lewis
Comparison Operators
Comparison Operators:
●
●
●
MAPLD 2003 P21
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
SynthWorks
= /= > >= < <=
Comparison operators return type boolean
Std_Logic is our basic type for design.
● How do we convert from boolean to std_logic?
Arrays with Arrays:
AGeB
AGeB <=
<= '1'
'1' when
when (A_uv
(A_uv >=
>= B_uv)
B_uv) else
else '0';
'0';
AEq15
<=
'1'
when
(A_uv
=
"1111"
)
else
AEq15 <= '1' when (A_uv = "1111" ) else '0';
'0';
●
Arrays with Integers (special part of arithmetic packages):
DEq15
DEq15 <=
<= '1'
'1' when
when (D_uv
(D_uv == 15
15 )) else
else '0';
'0';
Result
Result == Boolean
Boolean
Lewis
Input
Input arrays
arrays are
are extended
extended to
to be
be the
the same
same length
length
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P22
Multiplication and Division
Multiplication Operators:
●
SynthWorks
* / mod rem
Array Multiplication
signal
:: unsigned(
signal A_uv,
A_uv, B_uv
B_uv
unsigned( 77 downto
downto 0)
0) ;;
signal
:: unsigned(15
signal Z_uv
Z_uv
unsigned(15 downto
downto 0)
0) ;;
.. .. ..
Z_uv
Z_uv <=
<= A_uv
A_uv ** B_uv;
B_uv;
•• Size
Size of
of result
result ==
•• Sum
Sum of
of the
the two
two input
input arrays
arrays
●
Array with Integer (only numeric_std)
Z_uv
Z_uv <=
<= A_uv
A_uv ** 22 ;;
•• Size
Size of
of result
result ==
•• 22 ** size
size of
of array
array input
input
Note:
Note: "/
"/ mod
mod rem"
rem" not
not well
well supported
supported by
by synthesis
synthesis tools.
tools.
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
SynthWorks
Adder with Carry Out
Unsigned Code:
Unsigned Algorithm:
'0',
A(3:0)
'0',
A(3:0)
++ '0',
B(3:0)
'0',
B(3:0)
------------------------------------CarryOut,
CarryOut, Result(3:0)
Result(3:0)
signal
signal
signal
signal
signal
signal
Lewis
MAPLD 2003 P23
Y5
Y5 <=
<=
('0'
('0' && A)
A) ++ ('0'
('0' && B);
B);
YY <=
<= Y5(3
Y5(3 downto
downto 0)
0) ;;
Co
Co <=
<= Y5(4)
Y5(4) ;;
A,
A, B,
B, YY :: unsigned(3
unsigned(3 downto
downto 0);
0);
Y5
:: unsigned(4
Y5
unsigned(4 downto
downto 0)
0) ;;
Co
:
std_logic
;
Co
: std_logic ;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P24
SynthWorks
Adder with Carry In
signal
signal A,
A, B,
B, YY :: unsigned(3
unsigned(3 downto
downto 0);
0);
signal
:: unsigned(4
signal Y5
Y5
unsigned(4 downto
downto 0)
0) ;;
signal
signal CarryIn
CarryIn :: std_logic
std_logic ;;
Desired Result:
Algorithm
A(3:0)
A(3:0) ++ B(3:0)
B(3:0) ++ CarryIn
CarryIn
A(3:0),
A(3:0), '1'
'1'
++ B(3:0),
B(3:0), CarryIn
CarryIn
------------------------------------Result(4:1),
Result(4:1), Unused
Unused
Example: Carry = 0
Carry = 1
0010,
0010, 11
0001,
0001, 00
--------------0011,
0011, 11
0010,
0010, 11
0001,
0001, 11
--------------0100,
0100, 00
Result
Result
Code:
Y5
Y5
YY
<=
<= (A
(A && '1')
'1') ++ (B
(B && CarryIn);
CarryIn);
<=
<= Y5(4
Y5(4 downto
downto 1)
1) ;;
Lewis
SynthWorks
ALU Functions
●
ALU1:
OpSel
00
01
10
11
●
MAPLD 2003 P25
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
●
Function
A+B
C+D
E+F
G+H
Three implementations
●
Tool Driven Resource Sharing
●
Code Driven Resource Sharing
●
Defeating Resource Sharing
Since OpSel can select only one
addition at a time, the operators
are mutually exclusive.
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P26
SynthWorks
Possible Solutions to ALU 1
As Specified:
Optimal results:
A
A
C
E
G
B
C
D
E
F
i0
i1
O
i2
i3
sel
Z
G
H
OpSel
i0
i1
i2 o
i3
sel
OpSel
B
D
F
H
Z
i0
i1
i2 o
i3
sel
OpSel
●
This transformation of operators is called Resource Sharing
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
ALU 1: Tool Driven
MAPLD 2003 P27
SynthWorks
ToolDrvnProc
ToolDrvnProc :: process
process (OpSel,A,B,C,D,E,F,G,H)
(OpSel,A,B,C,D,E,F,G,H)
begin
begin
case
case OpSel
OpSel is
is
when
ZZ <=
when "00"
"00" =>
=>
<= AA ++ BB ;;
when
ZZ <=
when "01"
"01" =>
=>
<= CC ++ DD ;;
when
"10"
=>
Z
<=
when "10" =>
Z <= EE ++ FF ;;
when
ZZ <=
when "11"
"11" =>
=>
<= GG ++ HH ;;
when
others
=>
Z
<=
when others =>
Z <= (others
(others =>
=> 'X')
'X') ;;
end
end case
case ;;
end
end process
process ;; --- ToolDrvnProc
ToolDrvnProc
●
●
Lewis
Important: to ensure resource sharing, operators must be coded in the
same process, and same code (case or if) structure.
Any potential issues with this?
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P28
SynthWorks
ALU 1: Code Driven
XX <=
<= Mux4(OpSel,
Mux4(OpSel, A,
A, C,
C, E,
E, G)
G) ;;
YY <=
<= Mux4(OpSel,
Mux4(OpSel, B,
B, D,
D, F,
F, H)
H) ;;
ZZ <=
<= XX ++ YY ;;
●
Best Synthesis, use for:
● Sharing arithmetic operators
● Sharing comparison operators
● Sharing complex function calls
● Resource sharing often is not possible when using third party
arithmetic logic.
Lewis
MAPLD 2003 P29
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
SynthWorks
ALU 1:
Defeating Resource Sharing *
●
Bad Code will defeat Resource Sharing.
BadAluProc:
BadAluProc:
begin
begin
if
if (OpSel
(OpSel
if
if (OpSel
(OpSel
if
(OpSel
if (OpSel
if
if (OpSel
(OpSel
end
end process
process
process
process (OpSel,
(OpSel, A,
A, B,
B, C,
C, D,
D, E,
E, F,
F, G,
G, H)
H)
==
==
==
==
;;
"00")
"00")
"01")
"01")
"10")
"10")
"11")
"11")
then
then
then
then
then
then
then
then
ZZ
ZZ
ZZ
ZZ
<=
<=
<=
<=
<=
<=
<=
<=
AA
CC
EE
GG
++
++
++
++
B;
B;
D;
D;
F;
F;
H;
H;
end
end
end
end
end
end
end
end
if;
if;
if;
if;
if;
if;
if;
if;
Uses
Uses "end
"end if",
if", rather
rather than
than "elsif"
"elsif"
●
Lewis
* Not Recommended,
synthesis tool may create a separate resource for each adder.
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P30
Defeating Resource Sharing
●
When does this happen?
case
case StateReg
StateReg is
is
when
when S1
S1 =>
=>
if
if (in1
(in1 == '1')
'1') then
then
ZZ <=
<= AA ++ BB ;;
.. .. ..
end
end if
if ;;
when
when S2
S2 =>
=>
if
if (in2
(in2 == '1')
'1') then
then
ZZ <=
<= CC ++ DD ;;
.. .. ..
end
end if
if ;;
.. .. ..
when
when Sn
Sn =>
=>
.. .. ..
when
when others
others =>
=>
Lewis
●
SynthWorks
Separate statemachines and
resources
Statemach
Statemach :: process(...)
process(...)
begin
begin
--- generate
generate function
function
--- select
select logic
logic (OpSel)
(OpSel)
end
end process
process ;;
Resources
Resources :: process(...)
process(...)
begin
begin
--- code:
code:
-arithmetic
-- arithmetic operators
operators
--- comparison
comparison operators
operators
end
end process
process ;;
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P31
SynthWorks
More Information
There is work in progress to extend VHDL's math capability.
For more information see the following IEEE working groups
websites:
Group
IEEE 1164
IEEE 1076.3/numeric std
IEEE 1076.3/floating point
Website
http://www.eda.org/vhdl-std-logic
http://www.eda.org/vhdlsynth
http://www.eda.org/fphdl
Also see the DVCon 2003 paper, "Enhancements to VHDL's
Packages" which is available at:
http://www.synthworks.com/papers
Lewis
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P32
SynthWorks
Author Biography
Jim Lewis, Director of Training, SynthWorks Design Inc.
Jim Lewis, the founder of SynthWorks, has seventeen years of
design, teaching, and problem solving experience. In addition
to working as a Principal Trainer for SynthWorks, Mr. Lewis
does ASIC and FPGA design, custom model development,
and consulting. Mr. Lewis is an active member of IEEE
Standards groups including, VHDL (IEEE 1076), RTL
Synthesis (IEEE 1076.6), Std_Logic (IEEE 1164), and
Numeric_Std (IEEE 1076.3). Mr. Lewis can be reached at
jim@SynthWorks.com, (503) 590-4787, or
http://www.SynthWorks.com
Lewis
MAPLD 2003 P33
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
SynthWorks VHDL Training
SynthWorks
Comprehensive VHDL Introduction 4 Days
http://www.synthworks.com/comprehensive_vhdl_introduction.htm
A design and verification engineers introduction to VHDL syntax,
RTL coding, and testbenches.
Our designer focus ensures that your engineers will be productive
in a VHDL design environment.
VHDL Coding Styles for Synthesis 4 Days
http://www.synthworks.com/vhdl_rtl_synthesis.htm
Engineers learn RTL (hardware) coding styles that
produce better, faster, and smaller logic.
VHDL Testbenches and Verification 3 days
http://www.synthworks.com/vhdl_testbench_verification.htm
Engineers learn how create a transaction-based
verification environment based on bus functional models.
For additional courses see:
Lewis
http://www.synthworks.com
Copyright © 2003 SynthWorks Design Inc. All Rights Reserved.
MAPLD 2003 P34