FORDHAM UNIVERSITY
Fordham College Lincoln Center
Dept. of Computer and Info. Science
CISC 3593
Computer Organization
Spring, 2011
The Binary Adder
1
Introduction
The binary adder circuit is an important building block of digital arithmetic circuits.
Its purpose is to form the sum of two binary numbers. In this article we will see how to
design a binary adder out of basic gates.
2
Binary Addition
The design of a binary adder begins by considering the process of addition in base 2,
illustrated in Figure 1. In this example, the two numbers to be added, 1101 + 0110, are
written one above the other. The carries from one position to the next (called internal
carries) are written above them. The result is the 5-bit number 10011. Interpreting the
values of the binary numbers, this sum corresponds to the decimal addition 13 + 6 = 19.
From this example, we observe that the problem of adding two 4-bit numbers can be
reduced to the problem of adding a column of two or three bits and passing the carry
along to the next column. (For the sake of regularity, we can fill in a 0 as the input
carry in the rightmost column, so then each column is always the sum of three bits.)
3
One-bit Full-Adder
A circuit that adds a column of three bits is called a full-adder. (The name full-adder
comes from the fact that it can be constructed by combining two half-adders, each of
which adds only two bits, in a way that we shall see shortly.) We can design such a
circuit by making a table listing the outputs for all possible input combinations. Note
that in each column there is a sum bit which is put at the bottom and a carry bit
that is taken to the next column. So we need to specify two output bits for each input
combination. Let us call the two data bits x and y. (These are the bits in the two
+
1
1
0
0
1
0
0
1
1
0
0
1
1
1
0
1
Figure 1: Sample 4-bit binary addition problem. The carries are shown above the two
numbers being added.
1
x
0
0
0
0
1
1
1
1
z
y
+x
CS
y
0
0
1
1
0
0
1
1
z
0
1
0
1
0
1
0
1
C
0
0
0
1
0
1
1
1
S
0
1
1
0
1
0
0
1
Figure 2: Symbolic addition of a column of three bits, and truth table specifying the
results for each possible combination of inputs.
bottom rows of the sum, corresponding to the given numbers to be added.) We call the
input carry z. The output bits will be S for the sum bit and C for the output carry.
The summation is shown symbolically in Figure 2, together with the table giving the
outputs for each input combination. Each row of the table is filled in simply by writing
in binary the sum of the three bits x + y + z, using 0 = 00, 1 = 01, 2 = 10, and 3 = 11.
3.1
Sum-of-minterms design
From the truth-table, we can immediately write the two functions C and S as sums of
minterms by following the rule that the included minterms are those that correspond to
the rows where the function is 1:
C
=
Σ(3, 5, 6, 7)
S
=
Σ(1, 2, 4, 7)
Writing out the minterms as product terms, these sums correspond to
C
= xyz + xyz + xyz + xyz
S
= xyz + xyz + xyz + xyz
The corresponding circuit diagrams are shown in Figure 3.
3.2
More economical design
The circuit shown in Figure 3 is not the simplest in terms of number of gates. If we
measure cost by the number of gate inputs (which is roughly proportional to the number
of transistors needed), the circuit has a cost of 32 gate inputs, but at least it is of depth
2, the minimum depth for any circuit except for rare special cases.
One obvious economization is obtained by noting that C and S share minterm 7, so
it can be generated only once and fanned out to both OR gates. This reduces the count
of gate inputs by 3, to 29. A larger improvement can be obtained by noting that one
can rewrite C as
C = xy + yz + xz
2
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
x
y
z
C
x
y
z
x
y
z
S
Figure 3: Full-adder implementation via sum of minterms form.
y
+x
cs
x
0
0
1
1
y
0
1
0
1
c
0
0
0
1
s
0
1
1
0
Figure 4: Symbolic addition of a column of two bits, and truth table specifying the
results for each possible combination of inputs.
The circuit implementing this expression has only 9 gate inputs as compared to 16 for the
C circuit in Figure 3, so the combined C and S circuits would have only 25 gate inputs.
This turns out to be the most economical depth-2 implementation of the full-adder,
since S cannot be simplified beyond the sum-of-minterms form.
3.3
Design based on half-adder
A more economical circuit can be obtained if we allow the depth to be greater than 2.
We begin this design by introducing the half-adder, which adds just two bits instead of
3. The truth-table for the half-adder is shown in Figure 4.
A full-adder can be constructed from two half-adders and an OR gate, as shown in
Figure 5. The explanation of why this works is as follows. (In this paragraph, + denotes
addition, not the OR operation.) Consider the addition of x+y +z. This can be grouped
as (x + y) + z where (x + y) represents the output of the half-adder that receives x and
y. This partial sum is added to z by the other half-adder, yielding the complete sum bit
S. As for C, consider that there are two possible ways to make C = 1: first, if x + y = 2,
then adding z can only make the total sum 2 or 3, and either way C = 1. In this case,
the first half-adder’s carry-out is a 1. Second, if x + y = 1, then C will be 1 only if
z = 1 to make the total sum 2. In this case, the second half-adder’s carry output will
be 1. Thus we see that C = 1 if and only if at least one of the half-adders produces a
carry-out of 1. This corresponds to the OR of the two partial carry bits.
Now, to complete the design we need only construct the half-adder out of basic gates.
The straightforward design methodology will not yield the simplest design. Instead we
use some cleverness that will allow c and s to share some logic.
3
x
x
y
y
c
HA
s
x
y
z
c
HA
s
C
S
Figure 5: Block diagram of full-adder implementation via a pair of half-adders.
r
x
y
z
r
r
r
C
r
r
S
Figure 6: Full-adder implementation via a pair of half-adders, expanded in terms of
gates. The two half-adders are indicated by the dashed boxes.
From the truth-table for the half-adder, we see
c =
Σ(3) = x · y
s =
Π(0, 3) = (x + y)(x + y)
Using DeMorgan’s laws we can write the complement of s as
s =
(x · y) + (x · y) = (x · y) + c
Taking the complement of the last expression will yield s. Using this design for the
half-adder, the circuit shown in Figure 5 can be implemented in terms of basic gates as
shown in Figure 6. This circuit has 14 gate inputs, a large reduction from the previous
design, but its depth is 4 (the longest path from input to output passes through 4 gates).
The extra depth means it is slower than the depth-2 design. However, in the context of a
multi-bit binary adder design using the fast carry technique, this extra depth turns out
not to matter much because the carry propagation is the limiting factor for the overall
depth of the adder, so this design is quite competitive.
4
Ripple Adder
With the full-adder design in hand, we can now construct an n-bit adder simply by
stringing full-adders together. Each full-adder adds the bits in one bit position, say i,
where i = 0, 1, ..., n − 1. Thus the i-th full-adder receives the data bits Ai and Bi from
the two numbers to be added. It also receives a carry-in Ci from the full-adder in the
4
C0
A0
B0
S0
+
C1
A1
B1
+
A2
B2
+
A3
B3
+
S1
C2
S2
C3
S3
C4
Figure 7: Four-bit binary adder implemented by connecting 4 full-adders together.
next-lower-numbered bit position. It produces bit Si of the sum, and sends a carry-out
Ci+1 to the full-adder in the next-higher-numbered bit position. The full-adder for the
least-significant bit, i = 0, is an exception: it receives its carry-in from an external
source. The full-adder for the most-significant bit, i = n − 1, is also an exception: its
carry-out is sent out externally as the end-carry Cn .
Figure 7 shows such a design for n = 4. This design is called a ripple-adder because
the internal carries “ripple” down the chain from one full-adder to the next. It is
an economical design in terms of the number of gate inputs needed, but suffers the
disadvantage that the depth increases linearly with the number of bits in the operands.
To sum operands of 16 or more bits, such a design would be too slow to be competitive.
The speed of the adder can be increased by using a fast-carry technique. Such techniques
increase the speed with which the internal carries are generated, but at the expense
of increasing the number of gate inputs needed to implement the circuit. Fast-carry
techniques are not discussed here, since they are covered by Patterson and Hennessy
in Section C.6. Here we will only note that the circuit of Figure 6 produces the carry
generate and propagate functions discussed there from the half-adder that receives x
and y. The generate function is x · y which is the output of the upper AND gate, and
the propagate function is x + y which is the complement of the output of the lower AND
gate. So that circuit is well suited to be used in a design based on a fast-carry technique.
5
Exercises
The correctness of the full-adder design based on half-adders was justified informally in
section 3.3. Give a formal proof that the circuit in Figure 6 is a full-adder,
1. by constructing a truth table showing the intermediate signals and the outputs,
propagating the logic relationships specified by the circuit diagram.
2. by obtaining the boolean expressions for C and S that correspond to the circuit
diagram, and simplifying them using the various laws of boolean algebra until
they are recognizably the same as one of the other expressions obtained earlier
(e.g. sum-of-minterms form).
5