ISSN: 2319-5967
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International Journal of Engineering Science and Innovative Technology (IJESIT)
Volume 4, Issue 1, January 2015

Implementation of Integer Square Root
Addanki Purna Ramesh1, I. JAYARAM KUMAR2
Department of ECE, Sri Vasavi Engineering College, Pedatadepalli, Tadepalligudem, India
Abstract— Square root plays a major role in applications like computer graphics, image processing. To increase the
performance of computation, many algorithms have been proposed to carry out the computation task in hardware instead
of software. One very common and relatively quick method for finding the square root of a number is the Newton-Raphson
method which requires extensive use of division to produce results and its implementation on hardware is difficult as it
requires large area. In this paper we implemented Integer square root by using square and compare, successive subtraction
of odd integer’s and modified non-restoring methods. The three methods are implemented using Verilog HDL and
Xilinx12.1. The results show that modified non-restoring method has less delay and area.
Index Terms— Integer, square root, non-restoring, Verilog HDL
I. INTRODUCTION
Square root is one of the most useful and vital operation in computer graphics and scientific calculation
applications, such as digital signal processing (DSP) algorithms, math coprocessor, data processing and control
and even multimedia applications. It is a classical problem in computational number theory and often encountered,
which is a hard task to get an exact result. A lot of square root algorithms were implemented. The iterative methods
for square root starts with an initial guess value and improve accuracy of the result with each iteration. This
algorithm needs a seed generator for generating initial guess value using a ROM table. In each iteration,
multiplications and additions, subtractions are needed to speed up the multiplier.
Ross M. Fosler [1] implemented integer square root of a number using a multiplication and subtraction at each
iteration stage. This method occupies more area. In EC-130 logic calculator, integer square root was implemented
using subtraction operations on input number, such that successive odd integers are subtracted from input number.
The method is suitable for small numbers but for large numbers subtract cycles drastically increases. In EC-132 [2]
logic calculator, the integer square root was implemented, using couplet formation of the input number. In couplet
formation subtraction operation is performed on the split version of successive odd numbers.
Digit by digit calculation is classified in to two algorithms namely restoring and non-restoring. As the restoring
algorithm has a big limitation at restoring step in the regular flow. Yamin and Wanming [3, 4] implemented a
non-restoring algorithm with fully pipelined and iterative version that requires neither multipliers nor multiplexors.
Samavi [7] implemented non-restoring algorithm using (CAS) carry add and subtract module.
II. IMPLEMENTATION
Integer square root is implemented by using three methods, namely
 Square and compare method.
 Successive subtraction of odd integers.
 Modified non-restoring algorithm.
A. Integer Square Root Using Square and Compare Method
The integer square root is implemented using subtractor and multiplier method. In this each digit in a binary
number represents a power of two. By successively rotating through each bit or power of two and testing the result
against the desired value, i.e. squaring the guess and checking if it is greater than the original argument, the
approximate root gets closer and closer to the actual value. In conjunction with this, the value is achieved quickly.
The flow chart for square and compare method is shown in figure 1. For 8-bit integer input, only four program
loops required to complete test and to obtain the output. The table 1 gives the steps for an 8-bit integer square root
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input A = 1100 0100 (in decimal 196) using square and compare method. The architecture of 8-bit integer square
root is shown figure2, where HS and FS are the half subtractor and full subtractor. For 16-bit and higer bits the
integer square root needs a multiplier also.
Start
Input binary
n bits
Initial i = n/2
A = (n/2) zero bits
i
Integer
square root = A
0
i = i -1
stop
Set i th bit to
1 in A
Set i th
To 0 in A
A2 > input
i = i -1
Fig 1: Flow Chart of Integer Square Root Using Square and Compare Method
Table 1: 8-Bit Integer Square Root Implementation Steps Using Square and Compare Method
Step
1
A
0000
2
1000
3
1100
4
1110
Description
This squared is (0000 0000 = 0) less than input, start next
cycle with a new bit
New bit
This squared is (0100 0000 = 64) less than input, start next
cycle with a new bit
New bit
This squared is (0100 0000 = 144) less than input, start
next cycle with a new bit
New bit
This squared is (1100 0100 = 196) equal to input then stop
the process, otherwise process continues
B. Integer Square Root using Successive Subtraction of Odd Integers
In this method subtraction operation is performed on input, such that successive odd integers are subtracted from
the input number until to get the square root.
Example:
 16 - 1 = 15
 15 - 3 = 12
 12 - 5 = 7
7 -7 = 0
From the above example the numbers of subtractions are four, so 4 is square root of 16. If a large number to count
the number of subtractions, a simple formula is (n+1)/2, where n = last odd number subtracted. In the above
example (7+1)/2 = 4, therefore 4 is square root of 16. This method is valid for small numbers, but for large numbers
it is cumbersome. Table 2 gives the step procedure for integer square root using successive subtraction of odd
integer‟s method.
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X(7)
X(6)
HS
HS
X(7)
X(6)
FS
HS
X(7)
FS
FS
X(6)
FS
O(2)
O(1)
X(5)
X(4)
HS
HS
0
X(5) X(4)
X(3)
X(2)
HS
HS
X(6)
X(7)
O(3)
0
FS
FS
HS
X(5)
X(4)
FS
FS
X(3)
FS
X(2)
HS
0
X(1)
HS
X(0)
HS
0
O(0)
Fig 2: Architecture Of 8-Bit Integer Square Root Using Square and Compare Method
Table 2: Step Procedure for Integer Square Root using Successive Subtraction of Odd Integers Method
Normal Method
Modified Method
Subtract Cycle Odd Integer Subtract Cycle
Odd Integer
1
1
1st pair 1
(1) 0
2
0+1=1
2
3
2nd pair 3
(1) 1
4
1+1=2
3
5
3rd pair 5
(3) 2
6
2+1=3
4
7
4th pair 7
(4) 3
8
3+1=4
5
9
4th pair 9
(5) 4
10
4+1=5
Starting at decimal point, the input number is divided into pairs of digits, called “couplets”. Beginning at the most
significant couplet the answer can be derived, one digit being produced for each couplet.
1. Input number 225 is extracted into couplets 02 25
2. First step is to operate upon the most significant couplet (02) by subtracting with modified successive integers.
2
2
1
0
-
0
1
1
2
=
=
=
=
2
1
0
negative
3. Last subtracted number is 1 (since should not consider pair which resultant a negative). This is the first digit in
the final root. Remainder is 1 this is appended at the front to the 2nd couplet 25 as 125. Now operate subtraction on
new number 125. The obtained root for first couplet is appended in front of the numbers to be subtracted form 125
as shown below. 1‟ is the root of first couplet. Final root is 15. Hence this is the square root of 225.
125 - 10
= 115
115
-
=
11
107
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104 - 11
= 93
93 - 12
= 81
81 - 12
= 69
69 - 13
= 56
56 - 13
= 43
43 - 14
= 29
29 - 14
= 15
15 - 15
= 0
0 - 15
= negative
The block diagram to implement above needs the combined operation on a couplet along with a subtraction pair
known as subtract BEC is shown in figure 3. A subtractor module is combination of full subtractor in a chain, +1 is
the bit 1 incremented to the input b. A NOR gate is used which functions as a signal that is required to set the output
bit and difference that should be passed to next couplet operation. The block diagram of 8-bit integer square root
using successive subtraction of odd integers is shown in figure 4.
2
2
1
0
-
0
1
1
2
=
=
=
=
2
1
0
-ve
Fig 3: Block Diagram of Subtract BEC
Fig 4: Block Diagram of 8-Bit Integer Square Root using Successive Subtraction of Odd Integers
First block performs operation on first couplet and generates an output 4-bits and a remainder (difference) of 8-bit.
The output and remainder from block „a‟ is fed to input and bits to be subtracted to block „b‟ via computation block.
The „set lines‟ module sets its output to 4-bits (0000 to 1001) according to its input 9 lines. In the computation
block 4-bits input are multiplied by 1010 and then added to „b‟ bits to be subtracted input, and the remainder is
multiplied by 01100100 and added to second couplet. A binary to BCD converter is used for formation of couplets
for large bit lengths. Double Dabble algorithm is used in binary to BCD converter.
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C. Integer Square Root Using Modified Non-Restoring Method
In digit-by-digit calculation method, each digit of the square root is found in a sequence where it only one digit of
the square root is generated at each iteration. In general, this method can be divided in two classes, i.e. restoring and
non-restoring digit-by-digit algorithm
1 0 0 1
01 01 11
01
-1
-----------00 01
-1
01
← Positive : 1st bit is a 1
← Developed root is “1”;
affixed 01; subtract
------------11 00 11
+
10 01
-----------------11 11 10
+
1
00
← negative : 2nd bit is a 0
← Developed root is “10”; affix
11; and add
01
01
--------------------------1
00 00 11 00
← negative : 3rd bit is a 0
← Developed root is “100”;
affix 11; and add
← overflow: 4th bit is a 1
Fig 5: Example of Non-Restoring Algorithm Operation for Finding Integer Square Root [10]
1 0 0 1
01 01 11
-1
-----------00 01
-1
01
------------01 11
10 01
------------------
01
Choose 1 squared, subtract,
keep if positive
Shift two bits at a time
← Square root so far with 01
affixed : 2nd bit is a 0
No subtract
← Square root so far with 01
affixed : 3rd bit is a 0
No subtract because result
would be negative
01 11 01
-1
00 01
---------------------11 00 ← Positive: 4th bit is a 1
Fig 6: Example of Modified Non-Restoring Algorithm Operation for Finding Integer Square [10]
In restoring algorithm, the square root is obtained by, appending 01 to it and subtracting it, properly shifted, from
the current remainder. The 0 in 01 corresponds to multiplying by 2, the 1 is a new guess bit. The new root bit
developed is truly 1, if the resulting remainder is positive, and vice versa is 0, which the remainder must be restored
by adding the quantity just subtracted. Where as in non-restoring algorithm does not restore the subtraction if the
result was negative. Instead, it appends an 11 to the root developed so far and on the next iteration it performs an
addition. If the addition causes an overflow, then on the next iteration you go back to the subtraction mode. The
restoring algorithm has a big limitation at restoring step in the regular flow.
Non-restoring algorithm operation for finding integer square root and its modification as shown in figures 5 and 6
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respectively. Modified algorithm operation as only subtract and affix 01 instead of performing an add and affix 11
operation at each stage. Improved classical non-restoring digit-by-digit square root circuit by eliminate redundant
blocks. The circuit is referred to as the reduced area non-restoring circuit. However, it still based on constant digit
of 01 or 11 and add-subtract. A simple alternative solution that it only uses subtracts operation and appends 01. As
consequent, the subtract-multiplex is used as the block figure 7. The block diagram of integer square root using
modified non-restoring method with sm blocks is shown in figure 8. 8 input is 8- bit given at p [7:0] and the output
is obtained at u [3:0] is the resultant square root. It is a combination of a full subtractor and a 2x1 multiplexer. The
sm module is a controlled subtract multiplex module which controls the subtraction process. Multiplexor is used to
control the output difference passing to the next module. If subtraction result is positive the result is passed
otherwise the input x is passed instead when subtraction result is negative.
Fig 7: Basic Controlled Subtract Multiplexor (Sm) Module [10]
Fig 8: 8-Bit Architecture of Integer Square Root Using Modified Non-Restoring Method with sm Blocks [10].
Algorithm:
Step 1: Start
Step 2: Initialize the radicand (M) which is 2n bit number. Divide the radicand in two bits beginning at decimal
point in both directions.
Step 3: Beginning on the left (most significant), select the first group of one or two bits. (If n is odd then first
group has one bit, else two bits.)
Step 4: Select the first group of bits and subtract‟ 01‟ from it. If borrow is zero, result is positive then quotient is
1
otherwise it is 0.
Step 5: Append 01(to be subtracted next two bits of dividend) and quotient to subtract from remainder of
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previous stage.
Step 6: If result of subtraction is negative, write previous remainder as it is and quotient is considered as 0,
else write the difference as remainder and quotient as 1.
Step 7: Repeat step 5 and step 6 until end group of two bits.
Step 8: End.
D. 8-Bit Integer Square Root using Modified Non-Restoring Method Outputs Integer and Decimal Part
The block diagram of 8-bit integer square root using modified non-restoring method with integer and decimal part
outputs as shown in figure 9. Ex: if input is 255, then output is 15.946, displayed as integer part = 15, decimal part
= 946.
Fig 9: Block Diagram of 8-Bit Integer Square Root using Modified Non-Restoring Method with Integer and Decimal
Part Outputs
III. SIMULATION RESULTS
The simulation results of 8-bit, 16-bit integer square root and 8-bit integer square root using modified non-restoring
method integer and decimal part outputs is shown in figures 10, 11 and 12 respectively. The device utilization
summery of 8-bit input successive subtraction of odd integers, square and compare and modified non- restoring
methods (area, delay) and 16-bit input successive subtraction of odd integers, square and compare and modified
non- restoring methods (area, delay) is given in tables 3 and 4 respectively.
Fig 10: Simulation Result of 8-Bit Integer Square Root
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Fig 11: Simulation Result of 16-Bit Integer Square Root
Fig 12: Simulation Result of 8-Bit Integer Square Root using Modified Non-Restoring Method Outputs Integer and
Decimal Part
Table 3: Comparison of 8-Bit Input Successive Subtraction of Odd Integers, Square and Compare and Modified NonRestoring Methods (Area, Delay)
Integer Square Root
Device Spartan 3E
Successive Subtraction of
Square and
Modified Non(XC3S500E-5PQ208 -5)
Odd Integers
Compare
Restoring
No. of slices
101
10
10
No. of 4 input LUT‟s
177
17
17
No. of bonded I/O‟s
Total Delay (ns)
12
30.179
12
9.110
12
9.215
Table 4: Comparison of 16-Bit Input Successive Subtraction of Odd Integers, Square and Compare and Modified NonRestoring Methods (Area, Delay)
Integer Square Root
Device Spartan 3E
Successive Subtraction of
Square and
Modified Non- Restoring
(XC3S500E-5PQ208 -5)
Odd Integers
Compare
No. of slices
556
158
39
No. of 4 input LUT‟s
975
278
71
No. of bonded I/O‟s
24
24
24
82.941
59.816
37.166
Total Delay (ns)
IV. CONCLUSION
In this work, the square and compare method, successive subtraction of odd integer‟s method and modified
non-restoring method are implemented in Verilog HDL and synthesized by using Xilinx 12.1. The code is routed
on Spartan3E. The results showed that modified non-restoring method has less delay and area.
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FPGA for Custom Computing Machines, Napa, California, USA, 1996, pp. 226-232.
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[4] L. Yamin and C. Wanming, "Parallel-array implementations of a non-restoring square root algorithm," in Computer
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